JP2011192346A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device that reduces power consumption and can be integrated highly. <P>SOLUTION: Memory cells disposed in a matrix are included, a word line is connected to a gate of the memory cells, a local bit line LBLd is connected to a drain, and a first or second local bit line LBLS is connected a source. When reading a memory cell MC2, a read-out voltage Vread is applied to a local bit line LBLd1 selected by a bit line selection transistor TRd1, and 0 v is applied to a first local bit line LBLs0 selected by a first selection transistor TRs0. A source of an adjacent memory cell MC3 is clamped to fixed potential by a second selection transistor TRs4, and 0 v is applied to a source of an adjacent memory cell MC1 by a bit line selection transistor TRd0. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory (semiconductor memory device), and more particularly to a virtual ground nonvolatile semiconductor memory.

  As a nonvolatile semiconductor memory, an EPROM that can be electrically programmed and an EEPROM that can be electrically programmed and erased are known. Further, flash-type EEPROMs, which have further evolved EEPROMs and made it possible to erase data at once, have been widely put into practical use. Flash type EEPROMs (hereinafter referred to as flash memories) are roughly classified into NAND type and NOR type. A NAND flash memory has a memory cell array composed of a NAND string in which a plurality of memory cells are connected in series. Since this flash memory forms a bit line contact with the NAND string, the area occupied by the memory cells per bit can be effectively reduced, and a highly integrated memory cell array can be realized. Such a NAND flash memory is mainly used for a storage device that stores a large amount of data.

  On the other hand, the NOR type flash memory has a configuration in which one memory cell is arranged between a bit line and a source line, so that random access to one memory cell is possible, but a contact is made for each memory cell. Therefore, the occupied area of the memory cell per bit is larger than that of the NAND type. The NOR type flash memory is mainly used for a program memory of an electronic device such as a mobile phone by taking advantage of high-speed random access and low power consumption.

  In the NOR type flash memory, a virtual ground method or a multi-value method is adopted in order to improve the degree of integration. In a typical virtual ground system, the source / drain of a memory cell transistor (hereinafter referred to as a memory cell) is formed in common with the source / drain of a memory cell adjacent in the row direction, and each common source and drain is a bit line. As electrically connected. When reading is performed, the source of the selected memory cell is applied to the ground potential, the drain is applied to the read voltage, and the source / drain of the adjacent memory cell is brought into a floating state to prevent leakage current to the adjacent memory cell. (Patent Document 1, Patent Document 2).

  In the multi-value method, a plurality of threshold values are set in a memory cell by controlling charges to a floating gate or a charge storage region that traps charges. For example, Patent Document 3 discloses a mirror bit type nonvolatile semiconductor memory as a charge trap type multi-value memory. In this semiconductor memory, an ONO of an oxide film-nitride film-oxide film is formed between the surface of the silicon substrate and the gate electrode, and charges are captured at the interface between the oxide film and the nitride film. By switching the voltage applied to the source / drain, charges are held on the source side and the drain side of the nitride film (charge storage layer), respectively, and 2-bit information is stored in one memory cell. In addition, a configuration has been proposed in which a separate ONO film is formed in the vicinity of both ends of the gate electrode to physically separate the charge accumulation region.

JP 2003-100092 A Japanese Patent Laid-Open No. 11-110987 JP 2009-283740 A

  However, in the conventional nonvolatile semiconductor memory as described in the above-mentioned patent document, when the size of the memory cell is reduced by the miniaturization processing technique, the channel length is shortened, and it is difficult to accumulate charges near both ends of the gate electrode. Become. If the charge accumulation is inaccurate, it may cause a read error or a write error.

  FIG. 1 shows a circuit diagram of some blocks ARRAY0 and ARRAY1 of a memory array of a conventional virtual ground flash memory. Word lines WL00, WL01,... WL0n, WL10, WL11,... WL1n are connected to the gates of memory cells MC0, MC1,... MC4, and local bits are connected to the source and drain of each memory cell. Lines LBL00, LBL01,... LBL05 are connected. However, the local bit line may be a diffusion region common to the source / drain. Local bit lines LBL00, LBL01,... LBL05 are divided from global bit lines GBL0, GBL1,... GBL5 via block selection transistors SG0, SG1. Global bit lines GBL0, GBL1,... GBL5 are laid out in the column direction on each block so as to be used in common for the local bit lines of each block.

  When reading data in the memory cell MC2 of the block ARRAY0, the word line WL00 is applied to the read voltage Vcg, the block selection transistor SG0 is turned on, and the data is read to the drain of the memory cell MC2 via the global bit line GBL3 and the local bit line LBL03. A voltage Vread is applied. A ground potential (GND) is applied to the source of the memory cell MC2 via the global bit line GBL2 and the local bit line LBL02. The source of the memory cell MC3 adjacent to one of the selected memory cells MC2 is brought into a floating state by the global bit line GBL4 and the local bit line LBL04, and the drain of the memory cell MC1 adjacent to the other is the global bit line GBL1 and local Floating state or GND is made by the bit line LBL01. Similarly, the source of the memory cell MC0 is also brought into a floating state or GND. The global bit lines GBL4 and later are brought into a floating state. Thus, the read current of the selected memory cell MC2 is prevented from leaking from the adjacent memory cell.

  When writing data to the memory cell MC2, the program word line voltage Vpp is applied to the word line WL00, the block selection transistor SG0 is turned on, and the drain of the memory cell MC2 is passed through the global bit line GBL3 and the local bit line LBL03. Program voltage Vprog is applied, and a ground potential (GND) is applied to the source of memory cell MC2 via global bit line GBL2 and local bit line LBL02. The sources of the adjacent memory cells MC3 and MC1 are set to a floating state or GND as in the case of reading, and the global bit line GBL4 and subsequent ones are set to a floating state.

  However, in such a memory cell array configuration, when the source of an adjacent memory cell is brought into a floating state, the block selection transistor SG0 is turned on, so that not only the local bit line but also the global bit line GBL must be made floating. Don't be. The local bit line LBL04 is changed from a precharged state to a floating state so that the adjacent memory cell MC3 is not turned on. This is repeated so that the precharge level gradually decreases in several local bit lines LBL05, LBL06,..., And the last local bit line is set to GND, but the global bit line GBL is connected to each block ARRAY00, ARRAY01. ,... Is large, the load capacity is large, a large amount of power is required for precharging, and the power consumption increases.

  On the other hand, the global bit line GBL is common to the local bit lines LBL of each block, and it is desirable to widen the wiring width in order to reduce the resistance. However, as the memory cell size is reduced, the source / drain line is reduced. When the interval (gate length) is narrowed, the wiring pitch of the local bit lines LBL is narrowed. Since the global bit lines must be laid out at the same pitch as the local bit lines, if the pitch of the global bit lines is reduced, the interval between the global bit lines is reduced and there is a risk of short circuit.

  The present invention solves the above-described conventional problems, and an object thereof is to provide a nonvolatile memory device that can achieve low power consumption and high integration.

  The semiconductor memory according to the present invention has a plurality of memory cells arranged in a matrix, and each memory cell has a first conductivity type semiconductor region and a second conductivity type first and second diffusion region. Including a memory cell array in which the first or second diffusion region of the memory cell is common to the first or second diffusion region of another memory cell adjacent in the row direction, and extending in the row direction of the memory cell array, and A plurality of word lines connected to the gates of the memory cells, a plurality of first local bit lines extending in the column direction of the memory cell array and electrically connected to a first diffusion region of each memory cell; and a memory A plurality of second local bit lines extending in the column direction of the cell array, adjacent to the first side of the first local bit line, and electrically connected to a second diffusion region of each memory cell; Memory cell array column A plurality of third regions extending in a direction, adjacent to a second side opposite to the first side of the first local bit line, and electrically connected to a second diffusion region of each memory cell. A local bit line, a plurality of global bit lines extending in the column direction of the memory cell array, at least one first common line, at least one second common line, and the plurality of first local bit lines A first selection circuit that electrically connects the selected first local bit line to a corresponding global bit line; and a second selected local bit line in the plurality of second local bit lines. A second selection circuit electrically connected to one common line; and a second selection circuit electrically connecting a third local bit line selected in the plurality of third local bit lines to a second common line. 3 selection circuit and memory cell Read control means for reading data, and the read control means applies a first read voltage to the first local bit line selected by the first selection circuit for the selected memory cell. The second read voltage is applied to the second local bit line selected by the second selection circuit, and the third memory cell adjacent to the selected memory cell in the row direction is A third read voltage is precharged to the third local bit line selected by the selection circuit, and the second memory cell adjacent to the selected memory cell in the row direction is selected by the first selection circuit. The same voltage as that of the second local bit line is applied to the first local bit line.

  The semiconductor memory further has write control means for writing data to the selected memory cell, and the write control means has the first memory circuit selected by the first selection circuit for the selected memory cell. A first write voltage is applied to the local bit line, a second write voltage is applied to the second local bit line selected by the second selection circuit, and it is adjacent to the selected memory cell in the row direction. For the first memory cell, the third local bit line selected by the third selection circuit is precharged to the third write voltage, and the second memory cell adjacent to the selected memory cell in the row direction Is applied to the first local bit line selected by the first selection circuit with the same voltage as the second local bit line.

  Preferably, the third selection circuit includes a MOS transistor connected in series between the second common line and the third local bit line, and the MOS transistor is turned on and supplied from the second common line. Based on the potential, the third local bit line is precharged to a constant potential prior to reading or writing. Preferably, the memory cell array includes a plurality of blocks each including a plurality of memory cells, the plurality of global bit lines being common to local bit lines of the plurality of blocks, and the plurality of first local bit lines. The first common line and the second common line are parallel to the plurality of word lines. Preferably, the semiconductor memory further includes a plurality of sense amplifiers respectively connected to the plurality of global bit lines, and the sense amplifier detects data read from the selected memory cell. Preferably, the first selection circuit includes a first MOS transistor connected in series between the global bit line and the first local bit line, and the second selection circuit includes the second selection circuit. A second MOS transistor connected in series between the local bit line and the first common line, and the third selection circuit includes the third local bit line and the second common line. A third MOS transistor connected in series between the first MOS transistor and the first MOS transistor may have a breakdown voltage greater than that of the second and third MOS transistors. The source and drain of the memory cell can be changed in shape. Further, the first read voltage may be higher than the second read voltage, or the first read voltage may be lower than the second read voltage. The first write voltage may be higher than the second write voltage. Preferably, the memory cell is formed of a trap type transistor that traps charges between the gate and the surface of the silicon substrate.

  According to the present invention, when reading and writing data, it is possible to prevent the occurrence of a leak current and a write error to a memory cell adjacent to the selected memory cell. Furthermore, since local bit lines of adjacent memory cells can be precharged in units of local bit lines, power consumption can be reduced and high-speed read / write operations can be realized. Furthermore, it is possible to increase the wiring pitch of the global bit lines and suppress the occurrence of a short circuit between the global bit lines.

It is a figure which shows the circuit structure of the one part block of the conventional non-volatile semiconductor memory of a virtual ground system. It is a figure which shows the circuit structure of the one part block of the non-volatile semiconductor memory of a virtual ground system based on the Example of this invention. It is a table which shows the basic applied voltage at the time of read-out operation | movement and write-in operation | movement of the non-volatile semiconductor memory of a present Example. FIG. 10 is a diagram for explaining a read operation of the memory cell MC2. FIG. 10 is a diagram for explaining a write operation of the memory cell MC2. It is a table showing an example of voltages applied to each part when reading and writing the memory cell MC2. It is a figure which shows the physical structural example of the non-volatile semiconductor memory which concerns on the Example of this invention. 1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory according to an embodiment of the present invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, a virtual ground nonvolatile semiconductor memory is illustrated. It should be noted that the drawings are drawn for ease of explanation of the invention, and the scale of each part shown in the drawings does not necessarily match the scale of an actual device.

  FIG. 2 is a diagram showing a circuit configuration of a main part of the nonvolatile semiconductor memory according to the first embodiment of the present invention. FIG. 2 shows one block when the memory array is divided into a plurality of blocks. A partial array configuration is shown.

  One memory cell preferably includes a p-type silicon substrate or a p-type well, and includes a source and a drain made of an n-type diffusion region in the p-type semiconductor region. An oxide film-nitride film-oxide film (ONO) that can function as a region for trapping charges is formed on the substrate surface, and a gate electrode made of conductive polysilicon or metal is formed thereon. Is formed. The memory cell is preferably programmed by trapping hot electrons generated when a current is passed between the source / drain in the ONO film. However, other than that, charges may be trapped in the ONO film by Fowler-Nordheim (FN) tunneling. The trapped charge can be erased by, for example, FN tunneling or hot hole injection.

  Each memory cell is arranged in a matrix, and the source of one memory cell is formed in common with the source of one memory cell adjacent in the row direction, and the drain of the one memory cell is adjacent in the row direction. It is formed in common with the drain of the other memory cell. The drain of each memory cell is electrically connected to local bit lines LBLd0, LBLd1,... LBLd7 extending in the column direction, and the sources are the first local bit lines LBLs0, LBLs2, LBLs4, LBLs6 and the second local bit lines. The bit lines LBLs1, LBLs3, LBLs5, and LBLs7 are electrically connected alternately. Preferably, the local bit lines LBLd0, LBLd1,... LBLd7, and the first and second local bit lines LBLs0, LBLs1,..., LBLs7 are configured by buried diffusion regions in the substrate, similar to the source / drain. Is done. However, the local bit line may be constituted by a conductive layer wired on the substrate. The memory array configured as described above is operated by a virtual ground method. 2 includes eight local bit lines LBLd0, LBLd1,... LBLd7, first local bit lines LBLs0, LBLs2, LBLs4, LBLs6, and second local bit lines LBLs1, LBLs3, LBLs5. , LBLs7 are illustrated, but it should be noted that these are part of the block, and more local bit lines can be included in one block. Here, for convenience of explanation, description will be made using reference numerals shown in FIG.

  The gates of the memory cells in the row direction are connected to word lines WL_0, WL_1,... WL_4,. The local bit line LBLd0 extends in the column direction so as to be connected to the common drain of the memory cells MC0 and MC1, and the local bit line LBLd1 is connected to the common drain of the memory cells MC2 and MC3. Similarly, the local bit lines LBLd2, LBLd3,... LBLd7 extend in the column direction so as to be connected to the common drain of the memory cells. One end of each of the local bit lines LBLd0, LBLd1, LBLd2, LBLd3 is connected in series with the bit line selection transistors TRd0, TRd1, TRd2, TRd3, and the bit line selection transistors TRd0, TRd1, TRd2, TRd3 have global bits. Lines GBL_0, GBL_1, GBL_2, and GBL_3 are connected, and selection signals SSEL_0, SSEL_1, SSEL_2, and SSEL_3 are connected to the gates of these transistors. Furthermore, one end of each of the local bit lines LBLd4, LBLd5, LBLd6, LBLd7 is connected in series to the bit line selection transistors TRd4, TRd5, TRd6, TRd7, and the bit line selection transistors TRd4, TRd5, TRd6, TRd7 have global Bit lines GBL_4, GBL_5, GBL_6, and GBL_7 are connected, and selection signals SSEL_0, SSEL_1, SSEL_2, and SSEL_3 are connected to the gates of these transistors. In this way, a common selection signal SSEL_0, SSEL_1, SSEL_2, SSEL_3 is applied to every four bit line selection transistors, so that every fourth local bit line LBLd can be selected simultaneously. It has become. Each bit line selection transistor TRd1, TRd1,... TRd7 is composed of an n-channel MOS transistor, and selection signals SSEL_0, SSEL_1, SSEL_2, SSEL_3 applied to the gate are supplied from a column decoder (not shown).

  Although only one block is shown in FIG. 2, the global bit lines GBL_0, GBL_1,... GBL_7 are bit lines for the local bit lines LBLd0, LBLd1,. Connected via select transistors TRd1, TRd1,... TRd7. That is, the global bit line is common to the local bit lines connected to the memory cells of each block. Sense amplifiers (not shown) are connected to the other ends of the global bit lines GBL_0, GBL_1,... GBL_7, respectively. Senses and amplifies potential.

  A first local bit line LBLs0 on the source side extends in the column direction between the local bit lines LBLd0 and LBLd1, and the first local bit line LBLs0 is connected to a common source of the memory cells MC1 and MC2. . A second local bit line LBLs1 on the source side extends in the column direction between the local bit lines LBLd1 and LBLd2, and the second local bit line LBLs1 is connected to a common source of the memory cells MC3 and MC4. . Thus, the first local bit lines and the second local bit lines on the source side are alternately arranged in the column direction.

  The ends of the first local bit lines LBLs0, LBLs2, LBLs4, LBLs6 are connected in series to the first selection transistors TRs0, TRs1, TRS2, TRs3, and the first selection transistors TRs0, TRs1, TRS2, TRs3 are Commonly connected to one first global source line GARVSS_0. Selection signals SELS_0, SELS_1, SELS_2, and SELS_3 are connected to the gates of the first selection transistors TRs0, TRs1, TRS2, and TRs3.

  On the other hand, end portions of the second local bit lines LBLs1, LBLs3, LBLs5, LBLs7 are connected in series to the second selection transistors TRs4, TRs5, TRs6, TRs7, and further, the second selection transistors TRs4, TRs5, TRs6, TRs7 is commonly connected to one second global source line GARVSS_1. Selection signals SELS_4, SELS_5, SELS_6, and SELS_7 are connected to the gates of the second selection transistors TRs4, TRs5, TRs6, and TRs7. The first and second selection transistors TRs0, TRs1,... TRs7 are composed of n-channel MOS transistors, and selection signals SELS_0, SELS_1,... SELS_7 applied to the gates are supplied from a column decoder (not shown). The Preferably, the first and second global source lines GARVSS_0, GARVSS_1 extend in the row direction in parallel with the word lines WL_0, WL_1,... WL_n.

  Next, read and write operations of the memory cell array of this embodiment will be described. FIG. 3 is a table showing the voltage application conditions of each part when reading and writing of memory cells. When reading data from a memory cell, the voltage Vcg is applied to the gate of the selected memory cell via the word line, and the read voltage Vread is applied to the drain via the local bit line LBLd and the global bit line GBL. Then, GND is applied to the source via the first or second local bit line LBLs. The drain of an adjacent memory cell having the same word line and source as the selected memory cell is set to GND (the same potential as the first or second local bit line LBLs) via the local bit line LBLd and selected. The source of an adjacent memory cell having a common word line and drain with the memory cell is precharged to a constant potential via the first or second local bit line LBLs.

  When writing data to the memory cell, the voltage Vpp is applied to the gate of the selected memory cell via the word line, the program voltage Vprog is applied to the drain via the local bit line LBLd, 0.5v or GND is applied to the source via the first or second local bit line LBLs. The drain of an adjacent memory cell that has the same word line and source as the selected memory cell is set to 0.5 v or GND via the local bit line LBLd, and the selected memory cell and the word line and drain are common The sources of adjacent memory cells are precharged to a constant potential via the first or second local bit line LBLs.

  Next, a specific operation when the memory cell MC2 shown in FIG. 2 is read will be described. FIG. 4 shows only the relevant part of the memory cell MC2 extracted from FIG. 2 for ease of explanation. When reading the memory cell MC2, a voltage of Vcg = 4v is applied to the word line WL_1, and the memory cell in the row direction is selected. The other word lines remain at 0v or GND. At the same time, the bit line selection transistor TRd1 (SSEL_1 = 4v) is turned on, the local bit line LBLd1 is connected to the global bit line GBL_1, and a read voltage Vread of 0.9 v is applied to the global bit line GBL_1. The adjacent bit line selection transistor TRd0 (SSEL_0 = 4v) is also turned on, the local bit line LBLd0 is connected to the global bit line GBL_0, and 0v is applied to the global bit line GBL_0. Thereby, the local bit line LBLd0 is connected to the ground potential. The other bit line selection transistors TRd2, TRd3 (SSEL_2, SSEL_3 = 0V) are in an off state, and the local bit lines LBLD2, LBLd3 are disconnected from the global bit lines GBL_2, GBL_3.

  On the other hand, the first selection transistor TRs0 (SELS_0 = Vdd) is turned on, and the first local bit line LBLs0 is connected to the first global source line GARVSS_0. At this time, 0 v is supplied to the first global source line GARVSS_0. As a result, the first local bit line LBLs0 is connected to GND. The second selection transistor TRs4 (SELS_4 = Vdd−Vth) is turned on, and the second local bit line LBLs1 is connected to the second global source line GARVSS_1. At this time, since the voltage Vdd is supplied to the second global source line GARVSS_1, the second local bit line LBLs1 is precharged from 0v to a constant potential, and is constant by the second selection transistor TRs4. To be clamped.

  When charge is stored in the selected memory cell MC2, the threshold value of the memory cell MC2 becomes relatively high, so the memory cell MC2 is in an off state, and current flows from the drain to the source of the memory cell MC2. Absent. Since the source of the memory cell MC3 adjacent to the memory cell MC2 is precharged to a constant potential by the second selection transistor TRs4, a leakage current passing through the memory cell MC3 is prevented. Since 0 v is applied to the source of the memory cell MC1 adjacent to the memory cell MC2 on the other side by the first local bit line LBLs0 and 0 v is applied to the drain by the local bit line LBLd0, the memory cell MC1 The source / drain has substantially the same potential, and leakage current flowing through the memory cell MC1 is prevented. Accordingly, the potentials of the global bit line GBL_1 and the local bit line LBLd1 hardly change.

  When no charge is accumulated in the selected memory cell, the threshold value is relatively low, so that the memory cell MC2 is turned on and a current flows from the drain to the source. A sense amplifier (not shown) is connected to the global bit line GBL_1, and the on-current of the memory cell MC2 is detected by the sense amplifier. Also in this case, the source / drain of the adjacent memory cells MC3 and MC1 are substantially at the same potential, and leakage current is prevented. The voltage application conditions to the other transistors in FIG. 2 are as shown in the table of FIG.

  FIG. 5 is a diagram for explaining the operation when data is written (programmed) in the memory cell MC2, and only the relevant part of the memory MC2 is shown as in FIG. At the time of writing to the memory cell MC2, the write voltage Vpp = 9v is applied to the word line WL_1, and the memory cell in the row direction is selected. The other word lines remain at 0v. At the same time, the bit line selection transistor TRd1 (SSEL_1 = 9v) is turned on, the local bit line LBLd1 is connected to the global bit line GBL_1, and the write voltage Vprog is applied to the global bit line GBL_1. Also, adjacent bit line selection transistors TRd0, TRd2 (SSEL_0, SSEL_2 = Vdd) are turned on, and the local bit lines LBLd0, LBLd2 are connected to the global bit lines GBL_0, GBL_2. At this time, 0 v (or 0.5 v) is applied to the global bit line GBL_0, and a voltage Vdd is applied to the global bit line GBL_2. The bit line selection transistor TRd3 is in an off state, and the local bit line LBLd3 is disconnected from the global bit line GBL_3.

  On the other hand, the first selection transistor TRs0 (SEL_0 = Vdd) is turned on, and the first local bit line LBLs0 is connected to the first global source line GARVSS_0. At this time, 0 v (or 0.5 v) is supplied to the first global source line GARVSS_0. As a result, the first local bit line LBLs0 is connected to GND. The second selection transistor TRs4 (SELS_4 = Vdd) is turned on, and the second local bit line LBLs1 is connected to the second global source line GARVSS_1. At this time, the voltage Vdd is supplied to the second global source line GAAVSS_1, whereby the second local bit line LBLs1 is precharged from 0v to a constant potential, and is constant by the second selection transistor TRs4. To be clamped.

  When data is written to the selected memory cell MC2, the write voltage Vprog of the global bit line GBL_1 is applied. The memory cell MC2 is turned on, a current flows from the drain to the source, and hot electrons generated in the channel are trapped in the charge storage layer (ONO). Since the source of the memory cell MC3 adjacent to the memory cell MC2 is clamped at a constant potential by the second selection transistor TRs4, it is possible to prevent the memory cell MC3 from conducting and writing erroneous data. .

  Since 0v is applied to the source of the memory cell MC1 adjacent to the memory cell MC2 on the other side by the first local bit line LBLs0, there is a potential difference sufficient to turn on between the source and the drain of the memory cell MC1. It does not occur and no current flows through the memory cell MC1. Note that the voltage application conditions to the other transistors and the like shown in FIG. 2 are as shown in the table of FIG.

  There are two methods for erasing data held in a selected memory cell. One is a method of discharging charges trapped in the nitride film to the substrate by FN tunneling. For example, by setting the gate voltage of the selected memory cell to -7v, the substrate voltage to + 8v, and the source and drain to be in a floating state, electrons are tunneled through the oxide film and emitted to the substrate. The other is a method in which hot holes are injected into the nitride film and combined with the trapped charge to neutralize it. In this case, hot holes can be injected into the interface of the nitride film by setting the gate voltage of the selected memory cell to −6 v, the drain to +5 v, and the source in a floating state.

  FIG. 7 shows a physical configuration example of the memory cell array shown in FIG. In a p-type silicon substrate or p-type well 100, n + diffusion regions 102 and 104 for forming source / drain are formed. The diffusion region 102 extends in a strip shape in the column direction in the silicon substrate or well, functions as a source of each memory cell in the column direction, and forms first and second local bit lines LBLs. The diffusion region 104 extends in a strip shape in the column direction in the silicon substrate or well, functions as a drain of each memory cell in the column direction, and forms a local bit line LBLd.

  A plurality of polysilicon layers extending in a strip shape in the row direction are formed on the substrate. The polysilicon layer is doped with, for example, an n-type impurity and functions as a gate electrode of a memory cell and also functions as a word line. Immediately below the polysilicon layer, an oxide film-nitride film-oxide (ONO) charge storage region 106 is formed. A plurality of local bit lines LBLs and LBLd extending in a strip shape in the column direction are formed on the polysilicon layer via the interlayer insulating film 110. The local bit lines LBLs and LBLd are made of, for example, a metal material, extend in parallel with the source / drain diffusion regions 102 and 104, and are electrically connected to the diffusion regions 102 and 104 at regular intervals. By forming the local bit lines LBLs and LBLd, the electrical resistance of the local bit line formed of the diffusion region is reduced. Further, a plurality of global bit lines GBL extending in the column direction are formed on the local bit lines LBLs and LBLd via the interlayer insulating film 112. Since the pitch of the global bit line GBL is larger than the pitch of the local bit lines LBLs and LBLd, the wiring width of the global bit line GBL can be increased and the electrical resistance can be reduced. The global bit line GBL is connected to the bit line selection transistor TRd in a region not shown, for example, from a metal material.

  In the memory cell array of this embodiment, when writing to the memory cell, a high voltage is applied to the drain side and a low voltage is applied to the source side, so that the withstand voltage of the first and second selection transistors TRs is set to a bit. The breakdown voltage of the line selection transistor TRd can be lowered. Furthermore, the device parameters can be optimized by changing the shapes of the first diffusion region 102 and the second diffusion region 104. For example, the second diffusion region (drain) 104 has a lower concentration than the first diffusion region (source) 102, or the second diffusion region (drain) 104 is wider than the first diffusion region (source) 102. Can be formed.

  According to the nonvolatile semiconductor memory of this embodiment, when reading or writing a memory cell, the local bit lines of adjacent memory cells can be controlled in units of local bit lines. The time required can be shortened and the power consumption can be reduced. In addition, since the global bit line GBL wiring pitch can be laid out twice as large as the local bit line wiring pitch, the global bit line GBL wiring width is increased to reduce electrical resistance and short circuit between global bit lines. Can be prevented.

FIG. 8 is a block diagram illustrating a schematic configuration example of the nonvolatile semiconductor memory. The address buffer 200 receives address data supplied from the address bus ADDBUS and provides column address data to the source side bit line decoder 210 and the drain side bit line decoder 220. The source side bit line decoder 210 decodes the column address data, and selects the selection signals to the first and second selection transistors TRs0, TRs1,... TRs7 based on the result.
SELS_0, SELS_1,... SWL_7 are supplied, and the drain-side bit line decoder 220 supplies selection signals SSEL_0, SSEL_1, SSEL_7 of the bit line selection transistors TRd0, TRd1,. The word line decoder 230 receives row address data from the address buffer 200 and selects a word line based on the decoding result. A read voltage Vcg or a write voltage Vpp is supplied to the selected word line under the control of the read / write control circuit 260.

  Memory array cell 240 includes memory cells arranged in a matrix. Preferably, the memory cell array is divided into a plurality of blocks or sectors, and the memory cells can be selected in units of blocks or sectors. The input / output circuit 250 is connected to the data bus DATABUS, outputs data read from the memory cell array, and writes received data to the memory cells. Further, the command from the data bus is decoded by the read / write control circuit 260, and the read / write control circuit 260 controls the voltage supplied to the word line WL, the global bit line GBL, and the first and second global source lines GAAVSS_0 and GAAVSS_1. To do. The read / write control circuit 260 includes a sense amplifier for sensing data read from the memory cell and a voltage generation circuit for generating voltages such as a read voltage Vread, a write voltage Vprog, a row selection voltage Vcg, and a drain voltage Vdd. be able to.

  Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

  In the above embodiment, data is read and written from the global bit line GBL side, but it is also possible to read and write data from the opposite side by switching the source and drain of the memory cell. When reading data from the memory cell, for example, the read voltage Vread = 0.9v is applied to the first global source line GAAVSS_0 and the first local bit line LBLs0, and the global bit line GBL_1 and the local bit line LBLd1 are applied. May be grounded and the source / drain of an adjacent memory cell may be precharged.

  Furthermore, in the above embodiment, the memory cell of the type that traps electric charge is illustrated, but the present invention is not limited to this, and a memory cell in which a floating gate is formed between the control gate and the silicon substrate surface and other random access are possible. The present invention can be applied to all types of non-volatile or volatile memories.

100: p-type silicon substrate (p-well)
102: First diffusion region (source)
104: Second diffusion region (drain)
106: charge trapping regions 110, 112: interlayer insulating film

Claims (11)

A plurality of memory cells arranged in a matrix, each memory cell including first and second diffusion regions of the second conductivity type in the semiconductor region of the first conductivity type; A memory cell array in which the second diffusion region is common to the first or second diffusion region of other memory cells adjacent in the row direction;
A plurality of word lines extending in the row direction of the memory cell array and connected to the gates of the memory cells;
A plurality of first local bit lines extending in the column direction of the memory cell array and electrically connected to the first diffusion region of each memory cell;
A plurality of second local bit lines extending in the column direction of the memory cell array, adjacent to the first side of the first local bit line, and electrically connected to a second diffusion region of each memory cell; ,
A plurality extending in the column direction of the memory cell array, adjacent to the second side opposite to the first side of the first local bit line, and electrically connected to a second diffusion region of each memory cell A third local bit line of
A plurality of global bit lines extending in the column direction of the memory cell array;
At least one first common line;
At least one second common line;
A first selection circuit for electrically connecting a selected first local bit line in the plurality of first local bit lines to a corresponding global bit line;
A second selection circuit for electrically connecting a selected second local bit line in the plurality of second local bit lines to a first common line;
A third selection circuit for electrically connecting a selected third local bit line in the plurality of third local bit lines to a second common line;
Read control means for reading data of the memory cell,
The read control means applies a first read voltage to the first local bit line selected by the first selection circuit for the selected memory cell, and selects the first memory cell selected by the second selection circuit. A second read voltage is applied to the two local bit lines, and the first memory cell adjacent to the selected memory cell in the row direction is applied to the third local bit line selected by the third selection circuit. A second local bit is applied to the first local bit line selected by the first selection circuit for the second memory cell precharged with the third read voltage and adjacent to the selected memory cell in the row direction. A semiconductor memory that applies the same voltage as a line. The semiconductor memory further has write control means for writing data to the selected memory cell,
The write control means applies a first write voltage to the first local bit line selected by the first selection circuit for the selected memory cell, and selects the first memory cell selected by the second selection circuit. A second write voltage is applied to two local bit lines, and the third local bit line selected by the third selection circuit is applied to the first memory cell adjacent to the selected memory cell in the row direction. A second local bit is applied to the first local bit line selected by the first selection circuit for the second memory cell precharged to the third write voltage and adjacent to the selected memory cell in the row direction. The semiconductor memory according to claim 1, wherein the same voltage as that of the line is applied. The third selection circuit includes a MOS transistor connected in series between the second common line and the third local bit line, and is supplied from the second common line by turning on the MOS transistor. 3. The semiconductor memory according to claim 1, wherein the third local bit line is precharged to a constant potential before reading or writing based on the potential. The memory cell array includes a plurality of blocks each including a plurality of memory cells, and the plurality of global bit lines are common to local bit lines of the plurality of blocks, and are parallel to the plurality of first local bit lines. 4. The semiconductor memory according to claim 1, wherein the first and second common lines are parallel to the plurality of word lines. 5. 5. The semiconductor memory according to claim 1, further comprising a plurality of sense amplifiers respectively connected to the plurality of global bit lines, wherein the sense amplifier detects data read from a selected memory cell. The semiconductor memory as described in any one. The first selection circuit includes a first MOS transistor connected in series between the global bit line and the first local bit line, and the second selection circuit includes the second local circuit. A second MOS transistor connected in series between the bit line and the first common line; and the third selection circuit is configured to connect the third local bit line and the second common line to each other. 6. The device according to claim 1, further comprising a third MOS transistor connected in series therebetween, wherein the first MOS transistor has a withstand voltage greater than that of the second and third MOS transistors. Semiconductor memory. 7. The semiconductor memory according to claim 1, wherein the shape of the source and drain of the memory cell is not the same. The semiconductor memory according to claim 1, wherein the first read voltage is higher than the second read voltage. The semiconductor memory according to claim 1, wherein the first read voltage is lower than the second read voltage. The semiconductor memory according to claim 1, wherein the first write voltage is higher than the second write voltage. 11. The semiconductor memory according to claim 1, wherein the memory cell includes a trap-type transistor that traps electric charge between a gate and a surface of a silicon substrate.

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