KR20110024603A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a manufacturing method thereof are provided to reduce the level difference of an overlapping part by forming a dummy pattern on an upper part of a signal line and prevent shortcut of the signal line of a GIP-type liquid crystal display device. CONSTITUTION: A gate line(113) and a data line are formed in a display area of a first substrate. A thin film transistor is connected to the gate line and the data line. An image pixel is connected to the thin film transistor. A plurality of first signal lines is formed in a non-display area of the first substrate. A plurality of second signal lines is crossed with the first signal line. A first dummy pattern is formed in the upper part of the first signal line. A circuit block is connected to the gate line.

Description

Liquid Crystal Display Device And Method Of Fabricating The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a gate in panel (GIP) type liquid crystal display device having a gate driver formed on an array substrate, and a manufacturing method of the liquid crystal display device.

Recently, as the information society has evolved rapidly, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption, among which a liquid crystal display device has a resolution. It is widely used in laptops and desktop monitors due to its excellent color display and image quality.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the two electrodes face each other, injects liquid crystal between the two electrodes, and then applies liquid crystal to the liquid crystal molecules by applying a voltage to the two electrodes. By moving, it is an apparatus for representing an image by the transmittance of light that varies accordingly.

Such a liquid crystal display device includes a liquid crystal panel including two bonded substrates and a liquid crystal layer therebetween, a backlight unit disposed under the liquid crystal panel to supply light, and a plurality of signals disposed outside the liquid crystal panel to drive the liquid crystal panel. And a driving unit for supplying power.

Typically, the driving unit is implemented on a printed circuit board (PCB), which is divided into a gate driver connected to the gate wiring of the liquid crystal panel and a data driver connected to the data wiring, so that the gate PCB and the data are used for the gate. The printed circuit board for the gate and the printed circuit board for the data may include a gate pad formed on one side of the liquid crystal panel and connected to the gate wiring, and the gate pad formed thereon. It is formed on the other side orthogonal to the side and may be mounted in a tape carrier package (TCP) on each of the data pads connected to the data line.

However, when the gate printed circuit board and the data printed circuit board are mounted on the gate pad and the data pad, respectively, the volume and the weight increase.

Accordingly, some of the gate drivers formed on the gate driver printed circuit board, such as a shift register, are directly formed on the array substrate of the liquid crystal panel, and the remaining circuits of the gate driver and the circuit of the data driver are combined. A gate in panel (GIP) type liquid crystal display device, which is implemented as a printed circuit board and is connected to only one side of the liquid crystal panel, has been proposed.

1 is a plan view of a conventional GIP type liquid crystal display, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

As shown in FIG. 1 and FIG. 2, the GIP type liquid crystal display device 10 is formed between the lower array substrate 20, the upper color filter substrate 50, and the two substrates 20 and 50. The liquid crystal layer 70 is included.

 In this case, the GIP type liquid crystal display device 10 includes a display area DA in which an image is displayed and a non-display area NDA surrounding the display area DA.

The display area DA on the array substrate 20 is connected to the gate wiring 13 and the data wiring 28 and the gate wiring and the data wiring 13 and 28 that cross each other to define the pixel area P. The thin film transistor Tr, which is a switching element, and the pixel electrode 43 connected to the thin film transistor Tr are formed.

That is, the gate electrode 15 is formed on the array substrate 20, the gate insulating layer 21 is formed on the gate electrode 15, and the gate insulating layer 21 corresponding to the gate electrode 15 is formed on the gate electrode 15. The semiconductor layer 23 including the active layer 23a and the ohmic contact layer 23b is formed on the semiconductor layer 23, and the source and drain electrodes 30 and 32 spaced apart from each other are formed on the semiconductor layer 23 to form the thin film transistor Tr. ), A protective layer 38 having a drain contact hole 41 exposing the drain electrode 32 is formed on the thin film transistor Tr, and a drain contact hole 41 is formed on the protective layer 38. The pixel electrode 43 in contact with the drain electrode 32 is formed.

In FIG. 2, although the thin film transistor Tr is formed in only one pixel region P, the thin film transistor Tr is formed in the pixel region P, and the thin film transistor Tr is formed in all pixel regions P. do.

The display area DA of the color filter substrate 50 facing the array substrate 20 corresponds to the gate wiring 13, the data wiring 28, and the thin film transistor Tr of the array substrate 20. A first black matrix 53a is formed, and a color filter layer 58 is formed below the first black matrix 53a and the lower color filter substrate 50 exposed through the first black matrix 53a. The common electrode 60 of the transparent conductive material is formed on the lower front surface.

The color filter layer 58 includes red, green, and blue color filter patterns 58a, 58b, and 58c that are sequentially formed for each pixel area P in sequence.

On the other hand, in the non-display area NDA on the array substrate 20, a plurality of circuit blocks 48, a plurality of first signal wirings 18, a plurality of second signal wirings 35, and a plurality of The data pad 46 and a plurality of gate pads 47 are formed.

Each of the plurality of circuit blocks 48 may be a combination of a plurality of switching elements, capacitors, etc. constituting one stage of a shift register, and each of the plurality of second signal lines 35 and displays. It is connected to the gate wiring 13 of the area DA.

A plurality of data pads 46 and a plurality of gate pads 47 are formed at one edge of the non-display area NDA, and each of the plurality of data pads 46 is formed on the data line 28 of the display area DA. Connected to transfer data signals received from an external printed circuit board (not shown), and the plurality of gate pads 47 are connected to the plurality of first signal lines 18 of the non-display area NDA, respectively. Delivers start signal, clock signal, etc. input from

The plurality of first signal wires 18 and the plurality of second signal wires 35 are connected through a connection pattern 44. For this purpose, a plurality of first signals in the non-display area NDA of the array substrate 20 is provided. The wiring 18 is formed, the gate insulating layer 21 is formed on the plurality of first signal wirings 18, and the gate crossing layer 21 intersects the plurality of first signal wirings 18 on the gate insulating layer 21. The second signal wiring 35 is formed, and the protective layer 38 is formed on the plurality of second signal wiring 38.

A first connection contact hole 42a exposing a plurality of first signal wires 18 is formed in the gate insulating layer 21 and the protective layer 38, and a plurality of second signal wires ( A second connection contact hole 42b exposing 35 is formed.

When the connection pattern 44 corresponding to the first connection contact hole 42a and the second connection contact hole 42b is formed on the protective layer 38, the connection pattern 44 is formed in the first connection contact hole 42a. The first signal wiring 18 and the second signal wiring 18 by contacting the plurality of first signal wirings 18 through the plurality of first signal wirings 18 and the second signal wirings 35 through the second connection contact holes 42b. 35 are connected to each other.

In the non-display area NDA of the color filter substrate 50, a second black matrix 53b for preventing light leakage and a common electrode 60 made of a transparent conductive material are sequentially formed.

After the array substrate 20 and the color filter substrate 50 are completed, the GIP type liquid crystal display device 10 is completed by bonding the two substrates by pressing and heating and forming the liquid crystal layer 70 between the two substrates. For this purpose, a seal pattern 80 is formed in the non-display area NDA between the array substrate 20 and the color filter substrate 50.

The seal pattern 80 is formed to overlap the plurality of first signal wires 18 and the plurality of second signal wires 35 in the non-display area NDA of the array substrate 20. In the process, the plurality of first signal wirings 18, the gate insulating layer 21, the plurality of second signal wirings 35 or the protective layer 38 may be deteriorated, which will be described with reference to the drawings.

3 is an enlarged plan view of a portion A of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

3 and 4, a plurality of first signal wires 18 are formed in the non-display area NDA on the array substrate 20, and a plurality of first signal wires 18 are formed on the front surface of the plurality of first signal wires 18. A gate insulating layer 21 is formed, a plurality of second signal wirings 35 are formed on the gate insulating layer 21, and a protective layer 38 is formed on the entire upper surface of the plurality of second signal wirings 35. In addition, a connection pattern 44 for connecting the plurality of first signal wires 18 and the plurality of second signal wires 35 is formed on the passivation layer 38.

In this case, the plurality of first signal wires 18 and the plurality of second signal wires 35 cross each other to form a plurality of overlapping portions OP, and each of the plurality of overlapping portions OP has a higher level than other portions. Has

That is, when the plurality of first signal wires 18 and the plurality of second signal wires 35 have the first thickness t1 and the second thickness t2, respectively, the uppermost surface of the plurality of overlapping parts OP It becomes higher by the sum of the first thickness t1 and the second thickness t2 than the other parts.

Therefore, when the seal pattern 80 is formed and pressurized in the non-display area NDA between the array substrate 20 and the color filter substrate 50, the plurality of overlapping portions OP may have relatively greater pressure than other portions. Will receive.

That is, the first pressure P1 acting on the plurality of overlapping portions OP having a high height is larger than the second pressure P2 acting on another portion having a low height. (P1> P2)

This concentration of pressure may be caused by disconnection of the plurality of second signal wires 35 of the plurality of overlapping parts OP or the breakdown of the gate insulating layer 21 of the plurality of overlapping parts OP. It causes a defect such as a shortage between the signal wiring 18 and the plurality of second signal wirings 35.

Since the second signal wiring 35 or the gate insulating layer 21 is not destroyed immediately during the bonding process, the plurality of second signal wirings 35 or the gate insulating layer 21 are degraded. Defects such as this may occur.

The present invention is to solve the above problems, in the GIP type liquid crystal display device, by forming a dummy pattern on the plurality of signal wirings to reduce the step difference of the overlapping portion, by dispersing the pressure concentration during the bonding process, GIP type An object of the present invention is to prevent defects such as disconnection and short circuit of a plurality of signal wirings of a liquid crystal display device.

In addition, in the GIP type liquid crystal display device, by using a dummy pattern formed on the plurality of signal wires as a repair line, another object of the GIP type liquid crystal display device is to repair defects of the plurality of signal wires of the GIP type liquid crystal display device. .

In order to achieve the above object, the present invention provides a display device comprising: first and second substrates facing each other and spaced apart from each other and defining a display area and a non-display area surrounding the display area; Gate wirings and data wirings formed in the display area of the first substrate and crossing each other to define pixel areas; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; A plurality of first signal wires formed in the non-display area of the first substrate; A plurality of second signal wires crossing the plurality of first signal wires; A plurality of first dummy patterns formed on the plurality of first signal wires and spaced apart from the plurality of second signal wires; A circuit block connected to the plurality of second signal wires and the gate wires; A black matrix, a color filter layer, and a common electrode sequentially formed below the second substrate; A seal pattern formed in the non-display area between the first and second substrates; A GIP (gate-in-panel) type liquid crystal display device including a liquid crystal layer formed between the pixel electrode and the common electrode is provided.

The seal pattern overlaps the plurality of first signal wires and the plurality of second signal wires.

The GIP type liquid crystal display device may further include a gate insulating layer between the gate line and the data line, and a protective layer between the data line and the pixel electrode, wherein the plurality of first signal lines may include the gate. The plurality of second signal lines and the plurality of first dummy patterns may be made of the same layer and the same material as the data line.

The GIP type liquid crystal display further includes a plurality of connection patterns formed on the protective layer and connecting the plurality of first signal wires and the plurality of second signal wires 1: 1. A plurality of second dummy patterns may be further formed on the layer and spaced apart from the plurality of connection patterns.

In addition, the plurality of connection patterns and the plurality of second dummy patterns may be formed of the same layer and the same material as the pixel electrode.

On the other hand, the present invention comprises the steps of forming a gate wiring and a data wiring in the display area above the first substrate to define a pixel area crossing each other; Forming a thin film transistor connected to the gate line and the data line; Forming a pixel electrode connected to the thin film transistor; Forming a plurality of first signal wires in a non-display area surrounding the display area of the first substrate; Forming a plurality of second signal wires crossing the plurality of first signal wires and a plurality of first dummy patterns spaced apart from the plurality of second signal wires; Forming a circuit block connected to the plurality of second signal wires and the gate wires; Sequentially forming a black matrix, a color filter layer, and a common electrode under a second substrate in which the display area and the non-display area are defined; Forming a seal pattern in a non-display area between the first and second substrates; Bonding the first and second substrates so that the pixel electrode and the common electrode face each other; A method of manufacturing a gate-in-panel type liquid crystal display device comprising forming a liquid crystal layer between the pixel electrode and the common electrode.

The first and second substrates may be bonded to each other by pressing, and in the method of manufacturing the GIP type liquid crystal display device, the plurality of first signal wires and the plurality of second signal wires are connected 1: 1. The method may further include forming a plurality of connection patterns, and a plurality of second dummy patterns spaced apart from the plurality of connection patterns.

As described above, in the GIP type liquid crystal display device according to the present invention, by forming a dummy pattern on the plurality of signal wirings overlapping the seal pattern, the step difference is reduced and the pressure concentration in the bonding process is alleviated. There is an advantage that the defect is prevented.

In addition, in the GIP type liquid crystal display device according to the present invention, by using a dummy pattern formed on the plurality of signal wires as a repair line, there is an advantage that the defects of the plurality of signal wires can be repaired.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

5 is a plan view of a GIP type liquid crystal display device according to a first embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 5.

As shown in FIG. 5 and FIG. 6, the GIP type liquid crystal display device 110 includes a lower first substrate 120, an upper second substrate 150, and first and second substrates 120 and 150. And a liquid crystal layer 170 formed between the layers.

 In this case, the GIP type liquid crystal display 110 includes a display area DA in which an image is displayed and a non-display area NDA surrounding the display area DA.

In the display area DA on the first substrate 120, the gate line 113 and the data line 128 and the gate line and the data line 113 and 128 intersect each other to define the pixel area P. A thin film transistor Tr, which is a switching element to be connected, and a pixel electrode 143 connected to the thin film transistor Tr are formed.

That is, the gate electrode 115 is formed on the first substrate 120, the gate insulating layer 121 is formed on the gate electrode 115, and the gate insulating layer 121 corresponding to the gate electrode 115 is formed. A semiconductor layer 123 including an active layer 123a and an ohmic contact layer 123b is formed on the top, and source and drain electrodes 130 and 132 spaced apart from each other are formed on the semiconductor layer 123 to form a thin film transistor ( Tr, a protective layer 138 having a drain contact hole 141 exposing the drain electrode 32 is formed on the thin film transistor Tr, and the drain contact hole 41 is formed on the protective layer 38. The pixel electrode 143 in contact with the drain electrode 32 is formed.

In FIG. 2, the thin film transistor Tr is formed only in one pixel region P, but this is due to a difference according to the cutting plane, and the thin film transistors Tr are formed in practically all pixel regions P, respectively. .

In the display area DA of the second substrate 150 facing the first substrate 120, the gate wiring 113, the data wiring 128, and the thin film transistor 1Tr of the first substrate 120 are disposed. A corresponding first black matrix 153a is formed, and a color filter layer 158 is formed below the first black matrix 153a and below the second substrate 150 exposed through the first black matrix 153a. The common electrode 160 of the transparent conductive material is formed on the entire lower surface of the color filter layer 158.

The color filter layer 158 includes red, green, and blue color filter patterns 158a, 158b, and 158c which are sequentially and repeatedly formed in each pixel area P. FIG.

Meanwhile, in the non-display area NDA on the first substrate 120, a plurality of circuit blocks 148, a plurality of first signal wires 118, a plurality of second signal wires 135, and a plurality of The dummy pattern 137, the plurality of data pads 146, and the plurality of gate pads 147 are formed.

Each of the plurality of circuit blocks 148 may be a combination of a plurality of switching elements, capacitors, and the like that constitute one stage of a shift register, and each of the plurality of second signal wirings 135 and the display. It is connected to the gate wiring 113 of the area DA to supply a gate signal.

The plurality of data pads 146 and the plurality of gate pads 147 are formed at one edge of the non-display area NDA, and the plurality of data pads 146 are respectively formed on the data line 128 of the display area DA. Connected to transfer data signals received from an external printed circuit board (not shown), and the plurality of gate pads 147 are connected to the plurality of first signal lines 118 of the non-display area NDA, respectively. A plurality of driving signals such as a start signal and a clock signal received from a driving circuit such as a printed circuit board are transferred.

The plurality of first signal lines 118 crossing the plurality of second signal lines 135 are connected to the plurality of data pads 146, the plurality of gate pads 147, and the plurality of second signal lines 135. The plurality of driving signals are transmitted to the plurality of circuit blocks 148.

The plurality of first signal wires 118 and the plurality of second signal wires 135 are connected 1: 1 to each other through the connection pattern 144. A plurality of first signal wirings 118 are formed, a plurality of gate insulating layers 121 are formed on the plurality of first signal wirings 118, and a plurality of first signal wirings 18 are disposed on the gate insulating layer 121. ) A plurality of second signal wires 135 and a plurality of dummy patterns 137 corresponding to the plurality of first signal wires and spaced apart from the plurality of second signal wires are formed, and the plurality of second signal wires ( The protective layer 138 is formed on the 138 and the plurality of dummy patterns 137.

The first insulating contact hole 142a exposing the plurality of first signal wires 118 is formed in the gate insulating layer 121 and the protective layer 138, and the plurality of second signal wires are formed in the protective layer 138. A second connection contact hole 142b exposing the 135 is formed.

When the connection pattern 144 corresponding to the first connection contact hole 142a and the second connection contact hole 142b is formed on the protective layer 138, the connection pattern 144 is formed in the first connection contact hole 142a. The first signal wiring 118 and the second signal wiring 118 by contacting the plurality of first signal wirings 118 through the plurality of second signal wirings 135 through the second connection contact hole 142b. 135 are electrically connected to each other.

In the non-display area NDA of the color filter substrate 150, a second black matrix 153b for preventing light leakage and a common electrode 160 made of a transparent conductive material are sequentially formed.

After the first substrate 120 and the second substrate 150 are completed, the first and second substrates 120 and 150 are bonded to each other by pressing and heating, and between the first and second substrates 120 and 150. By forming the liquid crystal layer 170, the GIP type liquid crystal display device 110 is completed. A seal pattern 180 is formed in the non-display area NDA between the first and second substrates 120 and 150. .

The seal pattern 180 overlaps the plurality of first signal wires 118, the plurality of second signal wires 135, and the plurality of dummy patterns 137 in the non-display area NDA of the first substrate 120. In the GIP type liquid crystal display device 110 according to the first embodiment of the present invention, a plurality of second signal wires may be formed at portions corresponding to the plurality of first signal wires 118 on the gate insulating layer 121. Due to the plurality of dummy patterns 137 formed to be spaced apart from each other, the step difference caused by the plurality of second signal wires 135 is alleviated to prevent defects such as disconnection and short circuits.

7 is an enlarged plan view of a portion B of FIG. 5, and FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7.

As shown in FIG. 7 and FIG. 8, a plurality of first signal wires 118 are formed in the non-display area NDA on the first substrate 120, and a plurality of first signal wires 118 are formed on the upper surface of the non-display area NDA. A gate insulating layer 121 is formed on the gate insulating layer 121, and a plurality of second signal wirings 135 and a plurality of dummy patterns 137 are formed on the gate insulating layer 121, and a plurality of second signal wirings 135 and A protective layer 138 is formed on the upper surface of the plurality of dummy patterns 137, and a connection for connecting the plurality of first signal wires 118 and the plurality of second signal wires 135 on the protective layer 138. Pattern 144 is formed.

In this case, the plurality of first signal wires 118 and the plurality of second signal wires 135 cross each other to form a plurality of overlapping portions OP, and a plurality of second signal wirings of the plurality of overlapping portions OP. By forming a plurality of dummy patterns 137 spaced apart from the plurality of second signal wires 135 in a portion adjacent to the 135, the stepped by the plurality of second signal wires 135 of the plurality of overlapping portions OP. Is relaxed.

That is, when the plurality of first signal wires 118 and the plurality of second signal wires 135 have a first thickness t1 and a second thickness t2, respectively, the uppermost surfaces of the plurality of overlapping parts OP Is higher than the other portion by the sum of the first thickness t1 and the second thickness t2, but the plurality of dummy patterns 137 also have a second thickness t2, so that the plurality of dummy patterns 137 are formed. The uppermost surface of is also higher than the remaining portion by the sum of the first thickness t1 and the second thickness t2, so that the step difference between the plurality of second signal wires 135 and the plurality of dummy patterns 137 is removed.

Therefore, when the seal pattern 180 is formed and pressed in the non-display area NDA between the first and second substrates 120 and 150, the pressure concentrated on the plurality of overlapping portions OP is dispersed.

That is, the first pressure P1 acting on the second signal wires 135 of the plurality of overlapping portions OP is the second pressure P2 acting on the plurality of dummy patterns 137 having similar heights. Is substantially the same value as. (P1-P2)

Due to the dispersion of the pressure, a plurality of open circuits of the plurality of second signal wires 135 of the plurality of overlapping parts OP or a plurality of breakdowns of the gate insulating layer 121 of the plurality of overlapping parts OP are destroyed. A defect such as a shortage between the first signal wire 118 and the plurality of second signal wires 135 is prevented.

In the GIP type liquid crystal display device 110 of FIGS. 7 and 8, the first signal wiring 118 of the non-display portion NDA is formed on the same layer as the gate wiring 113 and the gate electrode 115 of the display portion DA. The second signal line 135 and the dummy pattern 137 of the non-display portion NDA are formed of the same material, and are the same as the data line 128, the source electrode 130, and the drain electrode 132 of the display portion DA. Although the layer and the same material are formed, the connection pattern 144 of the non-display portion NDA is formed of the same layer and the same material as the pixel electrode 143 of the display portion DA, but the GIP according to another embodiment is described. In the type liquid crystal display device, it is also possible to form the first signal wiring on the same layer and the same material as the data wiring, and the second signal wiring and the dummy pattern on the same layer and the same material as the gate wiring.

In addition, the plurality of dummy patterns 137 are formed on the plurality of first signal lines 118 with the gate insulating layer 121 interposed therebetween, and forming a contact hole in the gate insulating layer 121 to form the plurality of dummy patterns 137. The plurality of driving signals may be electrically connected to one signal wiring 118 or may be maintained in an electrically floating state without forming any contact holes in the gate insulating layer 121.

In addition, the plurality of dummy patterns 137 may be used as a repair line when an open occurs in the plurality of first signal lines 118. For example, as shown in FIG. When a disconnection occurs in one signal line 118, a plurality of first signal lines 118 and a plurality of dummy patterns 137 are irradiated to the C and D points through a gate insulating layer 121. By disconnecting the signals, disconnections of the plurality of first signal wires 118 can be repaired.

Meanwhile, in another embodiment, the pressure of the bonding process may be concentrated on the plurality of dummy patterns by forming the plurality of dummy patterns higher than the plurality of second signal wires of the overlapping part, which will be described with reference to the drawings. do.

9 is an enlarged plan view of a non-display area of a GIP type liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along the cutting line X-X of FIG.

Since the GIP type liquid crystal display of FIGS. 9 and 10 is the same as the GIP type liquid crystal display of FIGS. 5 and 6 except for the second dummy pattern, a description of the same parts will be omitted.

9 and 10, a plurality of first signal wires 218 are formed in the non-display area NDA on the first substrate 220, and the front surfaces of the plurality of first signal wires 218. A gate insulating layer 221 is formed on the gate insulating layer 221, and a plurality of second signal wirings 235 and a plurality of first dummy patterns 237 are formed on the gate insulating layer 221, and a plurality of second signal wirings 235 is formed thereon. ) And a plurality of first signal patterns 218 and a plurality of second signal lines 235 on the upper surface of the plurality of first dummy patterns 237. A connection pattern 244 and a plurality of second dummy patterns 245 for connecting are formed.

In this case, the plurality of first signal wires 218 and the plurality of second signal wires 235 cross each other to form a plurality of overlapping portions OP, and a plurality of second signal wirings of the plurality of overlapping portions OP. A plurality of first dummy patterns 237 spaced apart from the plurality of second signal wires 235 are formed in a portion adjacent to 235.

In addition, a plurality of second dummy patterns 245 spaced apart from the plurality of connection patterns 244 may be formed at portions corresponding to the plurality of first dummy patterns 237 except for the plurality of overlapping portions OP of the upper portion of the protective layer 238. ) Is formed.

That is, the plurality of second dummy patterns 245 and the plurality of first dummy patterns 237 may overlap each other to have the same shape.

Accordingly, the step difference due to the plurality of second signal wires 235 of the plurality of overlapping portions OP is reversed by the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245, and thus, the plurality of overlapping parts OP may be reversed. The pressure concentrated on the second signal wiring 235 of the plurality is rather concentrated on the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245.

That is, when the plurality of first signal wires 218 and the plurality of second signal wires 235 each have a first thickness t1 and a second thickness t2, the top surfaces of the plurality of overlapping parts OP may be Although the first thickness t1 and the second thickness t2 are higher than the other portions, the plurality of first dummy patterns 237 have the second thickness t2 and the plurality of second dummy patterns 245 Since the first and second dummy patterns 237 and 245 have the third thickness t3, the uppermost surfaces of the portions in which the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245 are formed are the first thickness t1 and the second thickness t2. The first dummy pattern 237 and the second dummy pattern 245 are higher than the plurality of second signal lines 235.

Therefore, when the seal pattern 280 is formed and pressurized in the non-display area NDA between the first and second substrates 220 and 250, the pressure concentrated on the plurality of overlapping portions OP is rather increased. It is concentrated in one dummy pattern 237 and a plurality of second dummy patterns 245.

That is, the first pressure P1 acting on the second signal wiring 235 of the plurality of overlapping portions OP may include a plurality of first dummy patterns 237 having a higher height and a plurality of second dummy patterns ( 245 is lower than the second pressure P2 acting. (P1 <P2)

Due to the dispersion and reversal of the pressure, disconnection of the plurality of second signal wires 235 of the plurality of overlapping portions OP or breakage of the gate insulating layer 221 of the plurality of overlapping portions OP may be caused. Defects such as shortages of the plurality of first signal lines 218 and the plurality of second signal lines 235 are prevented.

In the GIP type liquid crystal display device 210 of FIGS. 9 and 10, the first signal wiring 218 of the non-display portion NDA is formed of the same layer and the same material as the gate wiring and the gate electrode of the display portion, and the non-display portion ( The second signal wiring 235 and the first dummy pattern 237 of the NDA are formed of the same layer and the same material as the data wiring of the display unit, the source electrode and the drain electrode, and the connection pattern 244 of the non-display unit NDA. ) And the second dummy pattern 245 are formed of the same layer and the same material as the pixel electrode of the display unit DA. However, in the GIP type liquid crystal display according to another exemplary embodiment, the first signal wiring is connected to the data wiring. It is also possible to form the same layer and the same material, and to form the second signal wiring and the first dummy pattern on the same layer and the same material as the gate wiring.

In addition, the plurality of first dummy patterns 237 are formed on the plurality of first signal lines 218 with the gate insulating layer 221 interposed therebetween, and the plurality of second dummy patterns 245 are the gate insulating layers. 221 and a protective layer 238 are formed on the plurality of first signal wirings 218, and contact holes are formed in the gate insulating layer 221 and the protective layer 238 to form a plurality of first holes. The plurality of driving signals may be electrically connected to the signal wires 218 or may be electrically floating without forming any contact holes in the gate insulating layer 121 and the protective layer 238.

In addition, the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245 may be used as a repair line when an open occurs in the plurality of first signal lines 218. .

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a plan view of a conventional GIP type liquid crystal display device.

2 is a cross-sectional view taken along the line II-II of FIG. 1.

3 is an enlarged plan view of a portion A of FIG. 1;

4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

5 is a plan view of a GIP type liquid crystal display device according to a first embodiment of the present invention;

6 is a cross-sectional view taken along the line VI-VI of FIG. 5.

7 is an enlarged plan view of a portion B of FIG. 5;

8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7.

9 is an enlarged plan view of a non-display area of a GIP type liquid crystal display device according to a second embodiment of the present invention;

10 is a cross-sectional view taken along the line X-X of FIG. 9.

Claims (10)

First and second substrates facing each other and spaced apart from each other and defining a display area and a non-display area surrounding the display area, respectively; Gate wirings and data wirings formed in the display area of the first substrate and crossing each other to define pixel areas; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; A plurality of first signal wires formed in the non-display area of the first substrate; A plurality of second signal wires crossing the plurality of first signal wires; A plurality of first dummy patterns formed on the plurality of first signal wires and spaced apart from the plurality of second signal wires; A circuit block connected to the plurality of second signal wires and the gate wires; A black matrix, a color filter layer, and a common electrode sequentially formed below the second substrate; A seal pattern formed in the non-display area between the first and second substrates; Liquid crystal layer formed between the pixel electrode and the common electrode GIP (gate-in-panel) type liquid crystal display device comprising a. The method of claim 1, And the seal pattern overlaps the plurality of first signal wires and the plurality of second signal wires. The method of claim 1, And a gate insulating layer between the gate line and the data line, and a protective layer between the data line and the pixel electrode. The method of claim 3, wherein The plurality of first signal wires are made of the same layer and the same material as the gate wires, and the plurality of second signal wires and the plurality of first dummy patterns are of the same layer and the same material as the data wires. LCD display device. The method of claim 4, wherein And a plurality of connection patterns formed on the protective layer and connecting the plurality of first signal wires and the plurality of second signal wires 1: 1. The method of claim 5, And a plurality of second dummy patterns formed on the passivation layer and spaced apart from the plurality of connection patterns. The method of claim 6, And the plurality of connection patterns and the plurality of second dummy patterns are made of the same layer and the same material as the pixel electrode. Forming a gate line and a data line in the display area above the first substrate, the gate line and the data line crossing each other to define the pixel area; Forming a thin film transistor connected to the gate line and the data line; Forming a pixel electrode connected to the thin film transistor; Forming a plurality of first signal wires in a non-display area surrounding the display area of the first substrate; Forming a plurality of second signal wires crossing the plurality of first signal wires and a plurality of first dummy patterns spaced apart from the plurality of second signal wires; Forming a circuit block connected to the plurality of second signal wires and the gate wires; Sequentially forming a black matrix, a color filter layer, and a common electrode under a second substrate in which the display area and the non-display area are defined; Forming a seal pattern in a non-display area between the first and second substrates; Bonding the first and second substrates so that the pixel electrode and the common electrode face each other; Forming a liquid crystal layer between the pixel electrode and the common electrode Method of manufacturing a GIP (gate-in-panel) type liquid crystal display comprising a. The method of claim 8, And the first and second substrates are bonded by pressure. The method of claim 9, The method may further include forming a plurality of connection patterns connecting the plurality of first signal wires and the plurality of second signal wires in a 1: 1 manner, and a plurality of second dummy patterns spaced apart from the plurality of connection patterns. Manufacturing method of GIP type liquid crystal display device.

Images