KR20110024468A - Image sensor and method for manufacturing thefeof - Google Patents

Abstract

An image sensor according to an embodiment includes a gate formed on a semiconductor substrate; A photodiode formed inside the semiconductor substrate to be aligned with one side of the gate; A floating diffusion formed in the semiconductor substrate to be aligned with the other side of the gate; A lower insulating layer formed on the semiconductor substrate including the gate; An ion diffusion layer formed inside the lower insulating layer; And a metal wiring layer formed on the lower insulating layer, wherein the ions of the ion diffusion layer diffuse to the surface region of the semiconductor substrate.

Image Sensor, Dangling Bond

Description

Image sensor and its manufacturing method {IMAGE SENSOR AND METHOD FOR MANUFACTURING THEFEOF}

Embodiments relate to an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is mainly a charge coupled device (CCD) and CMOS (Complementary Metal Oxide Silicon) image sensor (CIS). ).

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method of forming a photodiode and a transistor in a unit pixel.

Image defects that occur in the image sensor include a dark level, a defect, and the like.

Among these, the dark level is that a charge (generally referred to as a "dark current") is output by heat in a state in which the generated charge is accumulated in the photodiode and is not caused by a photoelectric reaction, and is not an illumination condition. This is mainly caused by thermal components around the junction of the photodiode.

The generation of the dark current causing the dark level will be described in more detail. Continued use of the completed CMOS image sensor results in thermal component generation by joule heating. The generated heat produces parasitic hole-electron pairs.

Since the surface of the semiconductor substrate is subjected to excessive damage or stress by a process such as etching or ion implantation, many crystal defects and dangling bonds are distributed.

The generated electrons are captured at the crystal defect and the dangling bond site, and then some of the captured electrons are diffused into the photodiode so that the electrons are collected in the photodiode. The dark current that generates the dark level flows by the electrons collected in the photodiode.

The embodiment provides an image sensor and a method of manufacturing the same that can improve dark current characteristics.

An image sensor according to an embodiment includes a gate formed on a semiconductor substrate; A photodiode formed inside the semiconductor substrate to be aligned with one side of the gate; A floating diffusion formed in the semiconductor substrate to be aligned with the other side of the gate; A lower insulating layer formed on the semiconductor substrate including the gate; An ion diffusion layer formed inside the lower insulating layer; And a metal wiring layer formed on the lower insulating layer, wherein the ions of the ion diffusion layer diffuse to the surface region of the semiconductor substrate.

According to one or more exemplary embodiments, a method of manufacturing an image sensor includes: forming a gate on a semiconductor substrate; Forming a photodiode inside the semiconductor substrate to be aligned with one side of the gate; Forming a floating diffusion in the semiconductor substrate to be aligned with the other side of the gate; Forming an interlayer insulating layer including a metal wiring formed on the lower insulating layer; And forming an ion diffusion layer in the lower insulating layer.

In example embodiments, an ion diffusion layer may be formed in an upper region of a semiconductor substrate. Therefore, it is possible to remove dangling bonds generated at the interface of the semiconductor substrate, thereby improving dark current and noise characteristics.

In addition, the ion diffusion layer may be formed in the upper region of the gate to prevent attack on the gate insulating layer, thereby improving reliability of the device.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, when described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

5 is a cross-sectional view illustrating an image sensor according to an embodiment.

Referring to FIG. 5, the gate 30 formed on the semiconductor substrate 10, the photodiode 40 formed inside the semiconductor substrate 10 to be aligned with one side of the gate 30, and the gate 30. A floating diffusion part 50 formed inside the semiconductor substrate 10 and a lower insulating layer 60 and a lower insulating layer formed on the semiconductor substrate 10 including the gate 30 so as to be aligned with the other side of the semiconductor substrate 10. An ion diffusion layer 90 formed inside the 60 and a metal wiring layer 70 formed on the lower insulating layer 60 are included. In addition, the ions of the ion diffusion layer 90 may diffuse to the surface region of the semiconductor substrate 10.

For example, the ion diffusion layer 90 may be formed of hydrogen (H) ions.

As described above, an ion diffusion layer 60 formed of hydrogen (H) ions is formed in the lower insulating layer 60, and the hydrogen (H) ions are dangling generated in the surface region of the semiconductor substrate 10. It can be combined with a dangling bond.

As a result, the trap level of the image sensor is reduced, thereby improving dark singnal and noise characteristics.

1 to 5, a manufacturing method of an image sensor according to an embodiment will be described in detail.

1 is a layout illustrating a unit pixel of an image sensor.

The unit pixel may include a photodiode (PD) that receives light and generates photocharges, and a transfer transistor (Tx) that transfers photocharges collected from the photodiode (PD) to the floating diffusion region (FD); Addressing is performed by a reset transistor Rx for resetting the floating diffusion region FD, a drive transistor Dx serving as a source follower buffer amplifier, and a switching role. May include a select transistor (Sx).

2 is a cross-sectional view taken along the line A-A of FIG.

Referring to FIG. 2, a unit pixel including a photodiode 40 is formed on the semiconductor substrate 10.

The semiconductor substrate 10 is a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities. For example, the semiconductor substrate may be a p-type (p ++) substrate.

An epitaxial process may be performed on the semiconductor substrate 10 to form a low concentration p-type epi layer (p-epi).

An epitaxial process is to grow a low concentration silicon layer on a high concentration silicon substrate. The reason why the epi layer is used is that the epi layer of low concentration exists, so that the depletion region of the device can be increased greatly and deeply. In addition, when the silicon substrate having a high degree of density is provided under the epi layer, the electrons recombine quickly before electrons diffuse into neighboring unit cells, thereby reducing random diffusion of electrons.

An isolation layer 20 is formed on the semiconductor substrate 10 to define an active region. The device isolation layer 20 may be formed by a shallow trench isolation (STI) process.

The device isolation layer 20 is formed by forming a trench and gap-filling an insulating material, and a damage region may be formed on the surface of the semiconductor substrate during an etching process for forming an isolation trench. The damaged area may include crystal defects and dangling bonds.

Therefore, such a damaged area becomes a dark signal source and therefore the removal of the damaged area is required.

The gate 30 is formed on the semiconductor substrate 10. The gate 30 may be a gate of a transfer transistor.

The gate 30 may be formed by depositing and patterning a gate insulating film and an entire gate coating film on the semiconductor substrate 10. For example, the gate insulating layer may be an oxide layer. The gate conductive layer may be formed of a conductive material such as polysilicon, a metal material such as tungsten, or a metal silicide in a single layer or a plurality of layers.

The photodiode 40 is formed inside the semiconductor substrate 10 to be aligned with one side of the gate 30. The photodiode 40 forms a mask pattern (not shown) exposing the semiconductor substrate 10 corresponding to one side of the gate 30, and then ionizes a first impurity in a deep region of the semiconductor substrate 10. Implantation to form the first doped region n−. The second dopant region p0 is formed by implanting a second impurity into the shallow region of the semiconductor substrate 10 so as to contact the first doped region n−.

Thus, the photodiode 40 may have a PNP junction.

Next, a floating diffusion 50 is formed in the semiconductor substrate 10 to be aligned with the other side of the gate 30. The floating diffusion part 50 forms a mask pattern (not shown) that exposes the semiconductor substrate 10 corresponding to the other side of the gate 30, and then has a first concentration (high concentration) of impurities on the semiconductor substrate 10. n +) may be formed by ion implantation.

As described above, the unit pixel including the photodiode 40 is formed through an etching process and an implant process, and a damage region is generated on the surface of the semiconductor substrate 10 by the etching process. Can be.

The damaged area may include crystal defects and dangling bonds. This damaged area becomes a dark signal source, and thus the damaged area needs to be removed.

Referring to FIG. 3, a lower insulating layer 60 is formed on the semiconductor substrate 10 including the unit pixel. The lower insulating layer 60 may insulate the metal line from the transistor and may be a PMD (Pre Metal Dielectric).

For example, the lower insulating layer 60 may be formed of a single layer or a double layer of Phosphorus Silicate Glass (PSG), Boro-Phosphours Silicat Glass (BPSG), or PE-TEOS.

Although not shown, a contact plug may be formed through the lower insulating layer 60 to be connected to the unit pixel.

An interlayer insulating layer 70 and a metal line are formed on the lower insulating layer 60. The wire may be electrically connected to the unit pixel. The wiring may include a first metal M1 and a second metal M2, but is not limited thereto.

After forming the interlayer insulating layer corresponding to the first metal M1, the interlayer insulating layer corresponding to the second metal M2 may be formed.

Although not shown, the first metal M1 and the second metal M2 may be connected to each other through a metal contact.

For example, the first metal M1 and the second metal M2 may be formed of various conductive materials including metals, alloys, or silicides. The interlayer insulating layer 70 may be formed of an insulating film such as an oxide film or a nitride film.

Referring to FIG. 4, an ion implantation layer 80 is formed inside the lower insulating layer 60. The ion implantation layer 80 may be formed by performing an ion implant process.

For example, the ion implantation layer 80 may be hydrogen (H) ions. The ion implantation layer 80 may be formed of 1 × 10 ¹⁰ to 1 × 10 ¹⁶ atoms / cm 2.

The ion implantation layer 80 may perform an ion implantation process by ion implantation energy that does not reach the surface of the semiconductor substrate 10.

The ion implantation layer 80 may be formed inside the lower insulating layer 60 to prevent the occurrence of dark current.

In addition, since the ion implantation layer 80 is formed inside the lower insulating layer 60 to be parallel to the semiconductor substrate 10, the gate insulating layer may be prevented from being attacked.

Referring to FIG. 5, an ion diffusion layer 90 is formed inside the interlayer insulating layer 70.

The ion diffusion layer 90 may be formed by a heat treatment process for the ion implantation layer 80.

The heat treatment process of the ion diffusion layer 90 may be performed at 100 ~ 500 ℃.

By the heat treatment process, the hydrogen (H) ions of the ion diffusion layer 90 may be diffused to the upper and lower portions.

Hydrogen (H) ions diffused toward the semiconductor substrate 10 may be combined with dangling bonds generated in the semiconductor substrate 10 to reduce a trap level.

That is, the hydrogen (H) ions are combined with the dangling bonds in the damaged region generated at the interface between the device isolation layer 20 and the photodiode 40 (Si-H bonding), so that the dangling bonds can be removed. have.

Accordingly, it is possible to improve the dark signal and noise characteristics of the image sensor, thereby improving image characteristics.

In addition, the ion diffusion layer 90 may be formed between the semiconductor substrate 10 and the interlayer insulating layer 70 to prevent the gate insulating layer from being attacked by hydrogen (H) ions.

As described above with reference to the drawings illustrating an image sensor and a manufacturing method according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, those skilled in the art within the technical scope of the present invention Of course, various modifications may be made.

1 is a layout diagram of a unit pixel according to an exemplary embodiment.

2 to 5 are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment.

Claims (7)

A gate formed on the semiconductor substrate; A photodiode formed inside the semiconductor substrate to be aligned with one side of the gate; A floating diffusion formed in the semiconductor substrate to be aligned with the other side of the gate; A lower insulating layer formed on the semiconductor substrate including the gate; An ion diffusion layer formed inside the lower insulating layer; And A metal wiring layer formed on the lower insulating layer, The ions of the ion diffusion layer is diffused to the surface area of the semiconductor substrate. The method of claim 1, The ion diffusion layer is an image sensor formed of hydrogen ions. Forming a gate on the semiconductor substrate; Forming a photodiode inside the semiconductor substrate to be aligned with one side of the gate; Forming a floating diffusion in the semiconductor substrate to be aligned with the other side of the gate; Forming an interlayer insulating layer including a metal wiring formed on the lower insulating layer; And Forming an ion diffusion layer on the lower insulating layer. The method of claim 3, The ion diffusion layer is a method of manufacturing an image sensor formed of hydrogen ions. The method of claim 3, Forming the ion diffusion layer, Performing an ion implantation process inside the lower insulating layer to form an ion implantation layer; And The method of manufacturing an image sensor comprising the step of performing a heat treatment process for the ion implantation layer. The method of claim 5, The heat treatment process is a manufacturing method of an image sensor comprising the proceeding at 100 ~ 500 ℃. The method of claim 5, The dose amount is 1 x 10 ¹⁰ to 1 x 10 ¹⁶ atoms / cm 2 when the ion implantation layer is formed.

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