KR20110021042A - Tunneling field effect transistor having traps - Google Patents

Abstract

PURPOSE: A tunneling field effect transistor having the trap is provided to restrain the current leakage due to the voltage variation of a gate by forming the doping layer of low density additionally on an area to restrain the tunneling. CONSTITUTION: A filling oxide layer(10) is formed on a semiconductor substrate. A channel region(20) is formed on the filling oxide layer. A P+ domain(22) and a N+ domain(26) are formed on both sides of a semiconductor device with the channel are in-between. A gate insulating layer(40) is formed on the channel area.

Description

Tunneling field effect transistor with traps {TUNNELING FIELD EFFECT TRANSISTOR HAVING TRAPS}

The present invention relates to a tunneling field effect transistor, and more particularly, to form a trap layer at a portion where tunneling occurs on one side of the channel region to improve driving current, and to suppress leakage current when the transistor is turned off on the other side. The present invention relates to a tunneling field effect transistor having a trap capable of realizing low power and high energy efficiency.

Tunneling Field Effect Transistors (TFETs) were first proposed at Hitachi in Japan and Cambridge University in the UK.However, in the 1990s, tunneling was not possible because the reduction of existing MOSFETs was inevitable and the energy problem was not serious. Transistors have not been widely studied.

However, in the 2000s, as the limit of MOSFET miniaturization was imminent and the energy problem became serious, the tunneling transistor research came into the spotlight as one solution.

This is because as power consumption increases due to the smaller size of semiconductor devices and improved performance, there is a need for developing devices to replace or supplement existing MOSFETs.

Conventional MOSFETs have a physical limitation that the subthreshold swing (SS) cannot be lowered below 60mV / dec at room temperature, and there is a fundamental problem that a significant performance degradation occurs when the driving voltage is lowered.

However, the tunneling field effect transistor controls the flow of electrons or holes in a tunneling scheme different from that of conventional MOSFETs, so that a small change in the input voltage (driving voltage) can lead to a large change in the output current.

This suggests that the change of ON / OFF state occurs very rapidly in accordance with the change of the gate voltage, and it means that the lower SS may be lower than the threshold voltage SS.

Therefore, the tunneling field effect transistor is expected to be able to operate normally even at a very low driving voltage of 1V or less. Therefore, the tunneling transistor can achieve similar performance to that of a conventional MOSFET while consuming less power. It is expected that semiconductor devices can be implemented.

The tunneling field effect transistor basically has a structure in which the source 22 / drain 26 are formed of impurities having opposite polarities to both sides of the channel region 20, unlike the conventional MOSFET.

For example, in the case of an N-channel TFET, a source 22 is formed as a P + region and a drain 26 is formed as an N + region on both sides of the channel region 20 on a P-type SOI substrate on the buried oxide film 10. Here, the P + region refers to the P-type high concentration doping layer, and the N + region refers to the N-type high concentration doping layer (hereinafter, the same).

In the above structure, when + driving voltage is applied to the gate 50 on the gate insulating film 40 and reverse bias voltage is applied to the source 22 and the drain 26, respectively, as shown in FIG. In addition, a junction having a sharp energy band inclination is formed between the channel region 20 and the source 22 so that a driving current I _ON due to quantum mechanical tunneling flows.

However, since the driving current of the tunneling field effect transistor is due to the tunneling phenomenon, there has been a problem of having a lower current value than that of the MOSFET.

In addition, the tunneling field effect transistor has a structure in which a reverse bias voltage is applied to a pinned diode having a gate, so that the leakage current is basically lower than that of the MOSFET, but ambipolar operation is possible, thereby driving the gate as shown in FIG. When the voltage is moved from positive to negative (i.e., when OFF voltage is applied), the tunneling part is changed from the P + region to the N + region, resulting in an increase in leakage current due to tunneling in an unintended region. It has been pointed out that the problem of lowering the OFF current ratio.

As a method of increasing the foregoing driving current, US Patent Publication No. 20070178650 discloses a technique for replacing any one of the P + region and the N + region with silicon germanium or germanium instead of silicon, but it increases the complexity of the process and increases the cost. There is a problem.

On the other hand, in order to solve the leakage current problem due to the ambipolar operation later, US Patent Publication No. 20080224224 discloses a method of isolating any one of the P + region and the N + region so as not to overlap the gate, but also the area according to the separation There is a problem that the loss is large, and therefore it is difficult to employ a preferred solution.

Therefore, there is a continuing need for the structure and process development of a tunneling field effect transistor that can replace the existing MOSFETs by solving the above two problems without additional area loss without complicating the manufacturing process.

It is an object of the present invention to provide a novel tunneling field effect transistor structure for solving the problems of low driving current and high leakage current of a conventional tunneling field effect transistor without increasing process complexity or area loss.

In order to achieve the above object, a tunneling field effect transistor having a trap according to the present invention is a channel region having a semiconductor substrate, a gate formed on the semiconductor substrate with a gate insulating film interposed therebetween, and the semiconductor substrate positioned under the gate as a channel region. A tunneling field effect transistor comprising a P + region and an N + region formed on both sides of the semiconductor substrate with the channel region interposed therebetween, the trap layer between the P + region and the channel region or between the N + region and the channel region. Characterized in that formed.

In addition, the low concentration doping layer along the polarity of the adjacent high concentration doping layer is further formed between the N + region and the channel region opposite the trap layer is formed between the P + region and the channel region.

The semiconductor substrate may be formed by epitaxially growing silicon on a material layer having a different lattice constant, such as germanium, silicon germanium, or silicon carbon, or as a strained silicon-on-insulator (SSOI) substrate to reduce energy between bands. It is another feature to do.

The present invention has the effect of increasing the driving current by using a modified silicon substrate that is artificially trapped or epitaxially grown so that the lattice constant is different for the junction where tunneling should occur.

In addition, by separately forming a low concentration doping layer in the region to suppress the tunneling, there is also an effect to suppress the leakage current due to the voltage fluctuation of the gate to the maximum.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view showing an N-channel TFET structure according to the present invention, in which an N + region 26 / N-region 28 / P-type body 20 / trap layer 24 is formed from a left side on a P-type SOI or SSOI substrate. 3 illustrates a P-channel TFET structure according to the present invention. FIG. 3 is a cross-sectional view showing a P-channel TFET structure according to the present invention. 34) / N-type body 30 / P-region 38 / P + region 36 are exemplarily shown, and FIG. 4 shows reverse bias to source / drain and + to gate in N-channel TFET structure. FIG. 5 is an energy band diagram comparing tunneling currents (ON CURRENT: I _ON ) when there is no trap layer in the channel region adjacent to the P + region when voltage is applied (a) and when (b). Leakage current in (a) and (b) absence of low concentration doping regions when reverse bias is applied to source / drain and -voltage (or OFF voltage) is applied to gate in TFET structure, respectively (OFF CURRENT: I _OFF ) is an energy band diagram, and FIG. 6 shows changes in energy between bands when silicon germanium (Si _1-x Ge _X ) having a different germanium content is used as a buffer layer and epitaxially grown silicon thereon. Figure showing.

In the above, the N-region 28 refers to the N-type low concentration doping layer, and the P-region 38 refers to the P-type low concentration doping layer (hereinafter, the same).

First, a tunneling field effect transistor having a trap according to the present invention basically includes a semiconductor substrate, a gate formed on the semiconductor substrate with a gate insulating film interposed therebetween, and the semiconductor substrate positioned below the gate as a channel region. In a tunneling field effect transistor including a P + region and an N + region formed on both sides of the semiconductor substrate with a channel region interposed therebetween, a trap layer is formed between the P + region and the channel region or between the N + region and the channel region. It is characterized by.

That is, in the conventional N-channel TFET structure as shown in FIG. 1, as shown in FIG. 2, the P + region 22 and the channel region 20, and in the conventional P-channel TFET structure (not shown) as shown in FIG. 3, the N + region. It is a key technical feature of the present invention to improve the drive current by the trap layer by forming trap layers 24 and 34 between the 32 and channel regions 30, respectively.

As understood from FIG. 4, in the case of the N-channel TFET, when the reverse bias is applied to the source / drain and the + voltage is applied to the gate, a narrow hole is formed between the P + region and the P + region by the inversion electron. A pip layer is formed. When there is no separate trap layer between the channel region 20 and the P + region 22 in which the depletion layer is formed (a), only band-to-band tunneling 1 is performed. It will exist.

However, as in the present invention, when there is a separate trap layer 24 between the channel region 20 and the P + region 22 (b), not only band-to-band tunneling 1 More tunneling by trap-assisted tunneling (2) and field-emission (3) in the trap occurs, resulting in an increase in the overall tunneling current, which is driving current. (ON CURRENT: I _ON ) can be made much higher than before.

Furthermore, in order to further improve the driving current, it is preferable to use a substrate as a modified substrate (eg, a semiconductor substrate formed of a material layer having a different lattice constant).

This is because when the lattice constant epitaxially grows the semiconductor material in the buffer material layer, the epitaxial layer may be increased or decreased at atomic intervals of the buffer layer. In the present invention, by reducing the energy between bands using the same, It is possible to increase the tunneling current I _T.

I _T = A x exp (-Eg / 2k _B T)

In the above equation, A is the proportional constant and Eg is the energy between bands.

Specifically, since the interatomic spacing of germanium is larger than that of silicon, when the germanium or silicon germanium is used as the buffer layer of the substrate, and the epitaxial silicon is grown thereon, the interatomic spacing of silicon is increased, which is an N-channel TFET. when used as the substrate, by reducing the energy between the bands of only the modified silicon substrate (see Fig. 6) by increasing the tunnel current (I _T), it is possible to further increase the drive current.

In contrast, in the case of a P-channel TFET substrate, silicon may be epitaxially grown using a material layer (eg, SiC) having a smaller atomic spacing than silicon as a buffer layer.

Accordingly, the substrate according to the present invention is a silicon-on-insulfer (SOI) substrate or a germanium-on-sulfur (GOI) in which single crystal silicon or single crystal germanium is formed on the buried oxide film 10 as shown in FIGS. 2 and 3. In addition to an insultor substrate, preferably silicon-grown silicon-grown silicon oxide grown on a germanium-on-insulfer (GOI) substrate, an SiGe-on-insulfer (SGOI) substrate, and a silicon-on-insulfer (SCOI) substrate, respectively. -On-Insultor (SGOI), Silicon-SiGe-On-Insultor (SSGOI) substrates and Silicon-SiC-On-Insultor (SSCOI) substrates are preferred, and furthermore, silicon may be used as the SGOI substrate, the SSGOI substrate or the SSCOI substrate. It is preferable that the epitaxial growth is a strained-silicon-on-insulator (SSOI) substrate in which a thick insulating film is deposited on the silicon substrate, and then the GOI, SGOI or SCOI is removed.

Of course, the silicon epi layer on the bulk semiconductor material can be used as an active region to reduce the drive current.

On the other hand, when the same negative voltage (or OFF voltage) as the source is applied to the gate while maintaining the reverse bias state applied to the source / drain in the same N-channel TFET, as shown in FIG. As a narrow depletion layer is formed between the accumulated holes and the opposite N + region by PN junctions, there has been a problem that tunneling current (leakage current, OFF CURRENT: I _OFF ) is generated at an undesired site.

However, in the present invention, by further forming an N− low concentration doping layer between the channel region and the N + region, as shown in FIG. 5 (b), the width of the depletion layer formed between the accumulated holes and the N + region of the channel region is increased. By suppressing tunneling between them, leakage current is drastically reduced.

Although the N-channel TFET has been mainly described so far, if the P-channel TFET is also considered symmetrically, those skilled in the art will easily understand and implement the description thereof.

1 is a cross-sectional view showing the basic structure of a conventional tunneling field effect transistor.

FIG. 2 is a cross-sectional view showing an N-channel TFET structure according to the present invention, in which an N + region 26 / N-region 28 / P-type body 20 / trap layer 24 is formed from a left side on a P-type SOI or SSOI substrate. For example, the / P + region 22 is formed.

3 is a cross-sectional view showing a P-channel TFET structure according to the present invention, in which an N + region 32 / trap layer 34 / N-type body 30 / P-region 38 is located on an N-type SOI or SSOI substrate from the left. For example, the / P + region 36 is formed.

FIG. 4 shows the tunneling current (ON) when there is no trap layer in the channel region adjacent to the P + region when the reverse bias is applied to the source / drain and the + voltage is applied to the gate in the N-channel TFET structure. Energy band diagram comparing CURRENT: I _ON ).

FIG. 5 shows the leakage current (OFF) when there is no low doping region (a) and (b) when the reverse bias is applied to the source / drain and the -voltage (or OFF voltage) is applied to the gate in the N-channel TFET structure. : Energy band diagram comparing I _OFF ).

FIG. 6 is a graph showing changes in energy between bands when silicon germanium (Si _1-x Ge _X ) having a different germanium content is used as a buffer layer and epitaxially grown on silicon.

<Explanation of symbols for the main parts of the drawings>

10: investment oxide film 20: channel region (P type body)

22, 36: P + region 24, 34: trap layer

26, 32: N + region 28: N- region

30: Channel area (N-type body) 38: P- area

40: gate insulating film 50: gate

Claims (4)

A semiconductor substrate, a gate formed on the semiconductor substrate with a gate insulating film interposed therebetween, and a P + region and an N + region formed on both sides of the semiconductor substrate with the channel region sandwiched between the semiconductor substrate positioned under the gate; In the tunneling field effect transistor configured to include, And a trap layer is formed between the P + region and the channel region or between the N + region and the channel region. The method of claim 1, A tunneling field effect transistor having a trap further comprising a low concentration doping layer along the polarity of an adjacent high concentration doping layer between the N + region and the channel region opposite to the trap layer and between the P + region and the channel region. . The method according to claim 1 or 2, And the semiconductor substrate is formed of a material layer having a different lattice constant to reduce energy between bands. The method of claim 4, wherein The semiconductor substrate is a tunneling field effect transistor having a trap, characterized in that the epitaxial growth of silicon on any one of germanium, silicon germanium and silicon carbon or a SSOI (Strained-Silicon-On-Insulator) substrate.

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