KR102033324B1 - Tunneling field effect transistor having a gate overlap the source and drain - Google Patents

Abstract

The present invention relates to a tunneling field effect transistor having a gate structure overlapping a source and a drain. More particularly, the present invention relates to a tunneling field effect transistor having an extension gate structure overlapping each of a source region and a drain region of a tunneling field effect transistor. The present invention relates to a tunneling field effect transistor having a gate structure overlapping a source and a drain that eliminates the hump phenomenon caused by the tunneling. The tunneling field effect transistor having a gate structure overlapping the source and the drain according to the present invention has a structure of an extension gate extending over the source and the drain and overlapping a part of the source and the drain, unlike a TFET having a single gate structure. Through the structure of the extension gate, line tunneling is activated while reducing reverse current, thereby eliminating the hump phenomenon and ensuring high performance.

Description

Tunneling field effect transistor having a gate overlap the source and drain}

The present invention relates to a tunneling field effect transistor having a gate structure overlapping a source and a drain. More particularly, the present invention relates to a tunneling field effect transistor having an extended gate structure overlapping each of a source region and a drain region of a tunneling field effect transistor. The present invention relates to a tunneling field effect transistor having a gate structure overlapping a source and a drain that eliminates the hump phenomenon caused by the tunneling.

Since the creation of the world's first transistor by Shockley in 1947, under Moore's Law, the performance of integrated circuits (ICs) has increased every year, and with the miniaturization of tens of nanoscales, the integration density has increased dramatically. . However, increasing the integration density has also resulted in an increase in power consumption, and the need for low power device development is increasing for stable miniaturization. The low power device is a device that is driven under a low supply voltage and a gate voltage.

Subthreshold swing (SS) is required to increase the driving voltage in the low voltage state. However, MOSFETs that are commonly used today cannot overcome the limit of 60 mV / dec due to their physical characteristics. In addition, MOSFETs are experiencing difficulty in miniaturization due to increased drain induced barrier lowering (DIBL) and leakage current due to short channel effects.

In order to overcome this problem, researches on tunneling field-effect transistors (TFETs) using band to band tunneling (BTBT) in the valence band, which is a quantum mechanical phenomenon, are being actively conducted. Tunneling refers to a phenomenon in which electrons in an energetic valence band move to a conduction band. Tunneling in a TFET can be divided into line tunneling and point tunneling.

Point tunneling occurs when the energy band in the channel region rises or falls by the gate electric field at the junction between the source and the channel or the channel and the drain. Line tunneling occurs when the valence band and conduction band become equal by the gate electric field at the gate oxide-source junction, and shows higher efficiency than point tunneling in terms of SS and driving current.

Research by TFETs has already demonstrated higher performance than MOSFETs in SS and off-current. However, there is a lot of difficulties in practical use due to the drawback of DIBT due to short channel effect at low driving current and channel length less than 10nm. Therefore, researches on TFET structures such as L-Shape and U-Shape using tunneling phenomena, or heterogeneous TFETs (H-TFETs) and two-dimensional TFETs (2D-TFETs) using channel materials other than silicon It's going on.

The gate of a conventional TFET is a structure on the channel, which has a hump phenomenon where point tunneling and line tunneling coexist and point tunneling occurs before line tunneling.

Therefore, there is a need for a structure in which line tunneling occurs first to remove the hump phenomenon.

Korea Patent Registration No. 10-1058370

According to the present invention, a heterogeneous gate TFET overlapping a region of a source and a drain using a different material for a gate of a source region and a gate of a drain region and a gate of a channel region in a structure in which a gate of an existing TFET overlaps a source and a drain region. Suggest.

In an embodiment, a tunneling field effect transistor having a gate structure overlapping a source and a drain may include a first source and a drain, and a channel formed between the source and the drain and an upper portion of the region of the source. A plurality of gates including a plurality of gates including a second extension gate formed to overlap a portion of an upper portion of the region of the drain and the region of the drain, and a plurality of gates including a main gate formed above the region of the channel; At least one of the work function of may be characterized in that it is configured to have a different work function.

As an example related to the present disclosure, at least one gate having a different work function among the plurality of gates may be characterized in that a degree of doping or a material of doping is different from another gate.

As an example related to the present invention, the first extension gate formed to overlap the source may be configured to have a work function lower than the work function of the main gate formed on the channel so that line tunneling occurs before point tunneling. It can be characterized in that it is configured to prevent the hump phenomenon.

As an example related to the present invention, the work function of the second extension gate formed to overlap the drain may be configured to be different from the work function of the main gate to reduce the reverse current.

As an example related to the present invention, the gate part may further include a gate oxide layer for insulating the gate part from the source, the drain, and the channel.

As an example related to the present invention, the gate oxide layer may be formed of HfO ₂ .

As an example related to the present invention, the first and second extension gates may be configured independently from the gate, or may extend to the gate and be configured as a single gate together with the gate.

The tunneling field effect transistor having a gate structure overlapping the source and the drain according to the present invention has a structure of an extension gate extending over the source and the drain and overlapping a part of the source and the drain, unlike a TFET having a single gate structure. Through the structure of the extension gate, line tunneling is activated while reducing reverse current, thereby eliminating the hump phenomenon and ensuring high performance.

In addition, the tunneling field effect transistor having a gate structure overlapping the source and drain according to the present invention can increase the performance by reducing the leakage current compared to the conventional tunneling field effect transistor.

1 is a block diagram of a tunneling field effect transistor having a gate structure overlapping a source and a drain according to an embodiment of the present invention.
2 shows the structure of a single gate TFET, a double gate TFET and a triple gate TFET according to the present invention.
3 shows the tunneling distribution of each of the single gate TFET, the double gate TFET and the triple gate TEET according to the present invention.
4 to 6 show energy bands and silicon bulk energy bands on the silicon surface of each of the single gate TFET and the double gate TFET and the triple gate TFET according to the present invention.
7 to 9 show the tunneling rates of each of the single gate TFET, the double gate TFET and the triple gate TFET according to the present invention.
10 shows a current-voltage characteristic curve of each of a single gate TFET, a double gate TFET and a triple gate TFET according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a tunneling field-effect transistor (TFET) having a gate structure overlapping a source and a drain according to an embodiment of the present invention. A drain 102 and a channel 103 may be included. The gate unit 110 may include a main gate 111 and a plurality of extension gates 112 and 113.

In this case, the channel 103 may be configured between the source 101 and the drain 102, and each of the plurality of extension gates and the main gate may operate (or be formed) as a gate of a transistor.

In addition, the gate part 110 overlaps a portion of an upper portion (or an upper surface or an upper portion) of each of the source region of the source 101 and the drain region of the drain 102. , 113, and a main gate 111 formed on an upper portion (or an upper surface or an upper portion) of the channel 103.

In this case, a first extension gate 112 of the plurality of extension gates 112 and 113 may be formed to face (or overlap) a portion of an upper portion of the region of the source 101. The second extension gate 113 of the 112 and 113 may be formed to face (overlap) a portion of an upper portion of the region of the drain 102, and the main gate 111 may be an area of the channel 103. It may be formed to face the top (or top or top).

In addition, the extension gates 112 and 113 may extend on one side of the main gate 111 to be configured as a single gate together with the main gate 111, and may be configured independently of the main gate 111. It may be.

In this case, the plurality of extension gates 112 and 113 and the main gate 111 are integrally formed so that the gate part 110 configured as a single gate is connected to the first extension gate 112 of the gate part 110. A corresponding portion thereof is formed to face a portion of an upper (or upper or upper) region of the source 101, and a portion of the gate portion 110 corresponding to the second extension gate 113 is the drain ( It may be formed to face some of the upper (or upper or upper) region of the 102.

In addition, the tunneling field effect transistor (TFET) according to the present invention further comprises a gate oxide film 104 to electrically insulate the gate portion 110 from the source 101, the channel 103 and the drain 102. It can be configured to include.

Accordingly, the gate oxide layer 104 may be formed between the first extension gate 112 and the source 101, and a lower portion (or lower surface or bottom surface) of the first extension gate 112 may be formed. An overlap may be formed to face a portion of the top (or top or top) of the source 101 to be formed on the top (or top or top) of the gate oxide layer 104.

In addition, the gate oxide layer 104 may be formed between the second extension gate 113 and the drain 102, and a lower portion (or a lower surface or a lower surface) of the second extension gate 113 may be formed. An overlap may be formed to face a portion of an upper portion (or an upper surface or an upper portion) of the drain 102 to be formed on the upper portion (or an upper surface or an upper portion) of the gate oxide layer 104.

In addition, the gate oxide layer 104 may be positioned between the main gate 111 and the channel 103.

In addition, all or part of each of the source 101, the drain 102, the channel 103, the gate portion 110, and the gate oxide layer 104 may be formed on a substrate (not shown).

On the other hand, source 101 is operable to inject carriers into a channel of a tunneling field effect transistor (hereinafter referred to as a TFET), as generally understood in the art. Similarly, drain 102 is operable to remove carriers from channel 103 of the TFET, as generally understood in the art.

In the embodiment of FIG. 1, the source 101 functions to inject carriers into the channel 103 and the drain 102 functions to remove carriers from the channel 103. Source 101 and drain 102 may each be coupled to one or more source and drain contacts (not shown).

Further, source 101 and drain 102 may each be formed of any suitable n or p type semiconductor material.

In addition, channel 103 generally forms a source-channel interface between source 101 and drain 102 and is operable to prevent or allow carriers to flow from source 101 to drain 102.

In addition, the gate oxide film 104 generally functions to insulate the source 101, the channel 103, the drain 102, and the gate portion 110 from each other. Therefore, gate oxide film 104 may be formed of any suitable electrically insulating material.

For example, the gate oxide film may be composed of any one of HfO 2 and SiO 2, but is preferably composed of HfO 2.

Based on the above-described configuration, the present invention provides a tunneling field effect transistor (hereinafter referred to as a triple gate TFET) according to the present invention having an overlapping gate structure in each of a source region and a drain region, thereby forming a single gate formed only on top of an existing channel. It operates to easily remove the hump (hump) phenomenon occurring in a single gate TFET having a will be described in detail with reference to the following drawings.

First, Figure 2 (a) is a view showing the structure of a typical single gate TFET, Figure 2 (b) is a structure of a double gate TFET having a gate structure overlapping the source region for comparison with the triple gate TFET according to the present invention 2 (c) is a view showing a structure of a triple gate TFET having a structure of a gate overlapped with the source 101 and drain 102 regions according to the present invention.

In this case, a plurality of gates including an extension gate and a main gate formed on each of the source region and the channel region according to FIG. 2B and the source 101 region and the drain 102 according to FIG. The material constituting the plurality of gates 111, 112, and 113 including the plurality of extension gates 112 and 113 configured at the top of each region and the main gate 111 configured at the top of the channel region may include the plurality of gates. The gates 111, 112, and 113 may be configured differently from each other.

That is, the first extension gate 112, the second extension gate 113, and the main gate 111 of the triple gate TFET according to the present invention may be formed of different materials.

In this case, the first extension gate 112 and the second extension gate 113 may be made of a material different from that of the main gate 111, and the first extension gate 112 and the second extension gate 113 may cross each other. The liver may be composed of the same substance.

In other words, in the triple gate TFET according to the present invention, the material used for the doping of the first extension gate 112 and the second extension gate 113 is the material of the main gate 111 (or the main gate 111). Material used for the doping).

In addition, source doping N _s = 1 × 1020 cm-3 (p-type), drain doping N _d = 1 × 1020 cm-3 (n-type), channel doping N _ch = 1 × 1017 cm-3 (n- type), the gate oxide thickness t _ox = 2 nm, the silicon channel layer thickness t _si = 10 nm, the drain and source region length L _d = L _s = 40 nm, and the channel length L _ch = 50 nm.

In addition, the oxide material constituting the gate oxide film 104 may be composed of HfO 2 to maximize tunneling efficiency by maximizing an electric field effect.

Figure 3 shows the tunneling distribution of each of the single gate TFET, double gate TFET, triple gate TEET at the drain-source voltage V _ds = 0.7 V, V _gs = 0.7 V.

First, since the single gate TFET according to FIG. 3 (a) has no gate overlapped with the source region, almost no line tunneling exists and a high point tunneling distribution can be confirmed at the gate oxide-channel junction.

On the other hand, the double gate TFET shown in FIG. 3 (b) and the triple gate TFET shown in FIG. 3 (c) have a line in an area where the extension gates 112 and 113 overlap each of the source 101 region and the drain 102 region. There is tunneling, and there is no point tunneling in the junction region where the gate oxide film 104 and the channel 103 are bonded due to the influence of the electric field in the source 101 region, and the weak point tunneling distribution in the bulk region can be confirmed.

4 to 6 are diagrams illustrating energy bands and silicon bulk energy bands on a silicon surface of each of a single gate TFET, a double gate TFET, and a triple gate TFET.

First, referring to FIG. 4, FIG. 4 (a) shows an energy band of a silicon surface connected to a gate oxide of a single gate TFET, and tunneling between the source and the channel when the gate-source voltage is V _GS = 0.7V. 1) and tunneling (# 2) is observed between the channel and the drain when V _GS = -0.7V, which is point tunneling from the source to the drain direction.

In addition, the point tunneling has lower efficiency of SS (subthreshold swing) and driving current than line tunneling in the direction of gate oxide in silicon bulk, and since the tunneling (# 2) is a reverse current, leakage This causes an increase in leakage current (ambipolar current).

As shown in Fig. 4 (b), the point tunneling of the silicon bulk region is also observed. Comparing Fig. 4 (a) and Fig. 4 (b), as the influence of the electric field in the silicon bulk becomes smaller than the silicon surface, the tunneling length becomes longer and the tunneling rate becomes smaller. .

In addition, the line tunneling phenomenon is not observed in the single gate TFET. Tunneling # 3 represents the tunneling from the source to the channel, and because of the long tunneling length, there is no significant effect, but it is a cause of the fine current at V _GS = 0V. This current increases as the length of the channel decreases, which increases off-current as one of the short channel effects.

In addition, referring to FIG. 5 which shows the energy band of the double gate TFET as compared to the energy band of the single gate TFET of FIG. 4, FIG. As shown, the double gate TFET includes a main gate formed on the channel as shown, and includes an extension gate extending on the top of the source region.

The double gate TFET is configured such that a work function is differently controlled between the extension gate and the main gate by using different materials between the extension gate formed on the source and the main gate formed on the channel, thereby minimizing the hump phenomenon. It is configured to.

The extension gate formed on the source may be adjusted so that the flat band voltage V _FB is sufficiently low in the source region using a material lower than the work function of the main gate formed on the channel.

As a result, line tunneling (# 11) appears first in the direction of the gate oxide layer from the source, and there is no hump since point tunneling (# 12) appears in the portion that is bent and the portion that is not bent under the gate influence in the source.

However, point tunneling (# 14) appearing in the channel and drain increases leakage current. Tunneling # 13 is different from the V _FB of the gate material on the silicon surface in the case of a double-gate TFET as compared with the single-gate TFET of as showing a tunneling moving to drain from the same source with a single gate TFET, Fig. 4 (a) Because of the adjustment, point tunneling between the source and the channel does not appear.

However, since there is no influence of V _FB in the silicon bulk region of FIG. 5 (b), point tunneling (# 21) appears between the channel at the source. As shown in FIG. 5 (b), there is also a leakage current which is point tunneling (# 22) between the channel and the drain, but the tunneling rate distribution is much lower than that of the single gate TFET.

FIG. 6 is an energy band of a triple gate TFET having a gate structure overlapping the source and drain according to the present invention, and in addition to the structure of the double gate TFET as shown, an extension gate 113 on top (or top) of the drain 102. ) Is an additional structure.

The second extension gate 113, which is the gate of the top (or top) of the drain 102, can reduce leakage current appearing between the drain 103 and the channel 103 of the double gate TFET and the single gate TFET.

In the triple gate TFET of FIG. 6A, unlike the single gate TFET and the double gate TFET, the energy band of the silicon surface has no point tunneling between the channel 103 and the drain 102, and thus no leakage current exists. .

In this case, the triple gate TFET is disposed on the first and second extension gates 112 and 113 and the channel 103 formed on the source (or source region) 101 and the drain (or drain region) 102, respectively. By using different materials between the formed main gates 111, a work function may be configured to be differently controlled between the extension gates 112 and 113 and the main gates 111, thereby minimizing the hump phenomenon. It is composed.

In particular, the first extension gate 112 formed on the source 101 has a flat band voltage in the region of the source 101 using a material lower than the work function of the main gate 111 formed on the channel 103. voltage V _FB can be adjusted to be sufficiently low.

Accordingly, the triple gate TFET can eliminate the hump phenomenon like the double gate TFET.

That is, in the triple gate TFET according to the present invention, when the work function is lowered according to the change of the work function of the first extension gate 112 overlapping the source 101 region, the threshold voltage is also lowered, so line tunneling (# 11) is activated. And the line tunneling # 11 occurs before (preceding) the point tunneling # 12 so that the hump phenomenon can be easily prevented.

In this case, the change of the work function of the second extension gate 113 overlapping the upper portion of the drain 102 region may reduce leakage current generated in the single gate TFET and the double gate TFET as described above.

That is, the triple gate TFET according to the present invention has a structure of the gate portion 110 overlapping the drain 102 as well as the source 101, so that a leakage current may exist in the silicon bulk region of FIG. 6 (b). Because of the small size of the electric field in the bulk region, the total leakage current, including the bulk (silicon bulk) region and the surface (silicon surface) region, is reduced compared to the structure of the single gate TFET and the double gate TFET.

As shown in Fig. 6 (a), the tunneling of the triple gate TFET is performed inside the source 101 after the line tunneling (# 11) has occurred to the source 101 and the gate oxide film 104 as in Fig. 5 (a). Humping does not occur because it occurs in the order of point tunneling (# 12).

In addition, since the energy of the channel 103 and the drain 102 rises together due to the influence of the gate (second extension gate 113) formed on the drain 102, the triple gate TFET does not exhibit reverse current. .

Accordingly, the triple gate TFET may reduce the reverse current by adjusting the work function of the second extension gate 113 formed on the drain 102 and the material of the second extension gate 113. It is configured to be different from the material of the main gate 111 can be adjusted the work function of the second extension gate 113.

Meanwhile, each of the first extension gate 112, the second extension gate 113, and the main gate 111 constituting the gate part 110 operates as a gate (or is configured), and the first The work function of at least one of the plurality of gates 111, 112, and 113 formed of the extension gate 112, the second extension gate 113, and the main gate 111 is a work function of the remaining gates (or gates). Doping degree or doping material constituting the at least one gate of which the work function is different among the plurality of gates so as to be different from the doping degree or doping material constituting the remaining gate (or gates). Can be (adjusted).

By doing so, the degree of doping or the doping material for forming the first extension gate 112 may be different from that of the main gate 111 to prevent (remove) the hum phenomenon as described above. The reverse current may be reduced by configuring a degree of doping or a doping material for forming the second extension gate 113 to be different from a degree or a doping material of the main gate 111.

In this case, the triple gate TFET may be configured to have a different work function between the first extension gate 112 and the second extension gate 113, and as described above, the first and second extension gates ( 112 and 113) The first and second extension gates 112 and 113 may be controlled to be different from each other by differently adjusting the degree of doping or the doping material.

As described above, a tunneling field effect transistor having a gate structure overlapping a source and a drain according to the present invention, unlike a TFET of a single gate structure, an extension gate extending over the source and drain and overlapping a part of the source and drain, respectively. With the structure of the extension gate, line tunneling is activated while reducing the reverse current, thereby eliminating the hump phenomenon and ensuring high performance.

In this case, the tunneling field effect transistor having a gate structure overlapping the source and the drain according to the present invention, the gate structure composed of a plurality of gates consisting of extension gates and a main gate, and the work function between the plurality of gates are differently controlled. This prevents reverse currents and humps, ensuring low-power TEFT performance while ensuring higher efficiency than conventional TEFTs.

In addition, the tunneling field effect transistor having a gate structure overlapping the source and drain according to the present invention can increase the performance by reducing the leakage current compared to the conventional tunneling field effect transistor.

7 to 9 are diagrams illustrating the tunneling rates of each of the single gate TFET, the double gate TFET, and the triple gate TFET.

As shown in Fig. 7 (a), there is only point tunneling at V _GS = 0.7V of the single gate TFET and appears in both the silicon bulk region and the silicon surface region.

As shown in Fig. 7 (b), point tunneling appears from the source of the silicon surface to the channel at V _GS = 0V of the single gate TFET and silicon bulk when V _GS = -0.7V as shown in Fig. 7 (c). Point tunneling from channel to source appears on both and surfaces.

As shown in Fig. 8 (a), both line tunneling and point tunneling are observed in the double gate TFET.

However, unlike the single gate TFET, the double gate TFET occurs in the point tunneling of the silicon surface in the region where the gate at the top of the source and the non-existent region are encountered in the source, not between the source and the channel.

As shown in Figs. 8 (b) and 8 (c), the dual gate TFET tunnels almost identically to the single gate TFET.

In contrast, as shown in FIGS. 9 (a) and 9 (b), the triple gate TFET has almost the same tunneling rate as the double gate TFET, but as shown in FIG. 9 (c), the triple gate TFET is a single gate TFET. In addition, the point tunneling on the silicon surface seen in the double gate TFET is eliminated, reducing the leakage current.

FIG. 10 is a diagram illustrating current-voltage characteristic curves of each of a single gate TFET, a double gate TFET, and a triple gate TFET.

As shown, in the case of the double gate and triple gate TFETs in which the gate is added to the source region, the driving current increases by about 10 ⁴ times compared to the single gate TFET, and I ₆₀ (drain current when SS = ₆₀ mV / dec) Is increased by about 1 × 10 ⁹ times, and SSmin, the minimum SS value, is reduced by about 10 times, and the blocking current is reduced by about 100 times.

In addition, it can be seen that the triple gate TFET reduces leakage current by about 100 times than the single gate TFET and the double gate TFET.

The tunneling field effect transistor (triple TFET) having a gate structure overlapping the source region and the gate region according to an embodiment of the present invention provides high performance by enabling line tunneling while reducing reverse current by the electric field of the drain region. can do.

In addition, the triple gate TFET according to the present invention shows high performance when the gate oxide is replaced with a material having a high dielectric constant, and the threshold voltage is changed according to the work function of the source region gate. Lowers.

In addition, the triple gate TFET according to the present invention operates to eliminate the hump phenomena due to point tunneling and line tunneling, thereby exhibiting about 104 times higher driving current and 10 times higher SS than a single gate TFET. The leakage current can be reduced by about 100 times.

Through this, the triple gate TFET according to the present invention can increase the driving current, blocking current, leakage current, SS efficiency by separately adjusting the gate material.

The above description may be modified and modified by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

101: source 102: drain
103: channel 104: gate oxide film
110: gate portion 111: main gate
112: first extension gate 113: second extension gate

Claims (7)

In a tunneling field effect transistor,
sauce;
drain;
A channel between the source and the drain; And
A plurality of gates including a first extension gate formed to overlap a portion of an upper region of the source, a second extension gate formed to overlap a portion of an upper portion of the region of the drain, and a main gate formed to form an upper region of the channel; Including a gate portion,
A gate oxide layer formed of HfO ₂ to insulate the gate portion from the source, drain, and channel;
The first extension gate formed to overlap the source is configured to have a work function lower than the work function of the main gate formed at the upper portion of the channel so that line tunneling occurs before point tunneling, thereby preventing a hump phenomenon. ,
The second extension gate formed overlapping the drain reduces the leakage current between the channel and the drain, and the energy of the channel and the drain rises together to reduce the reverse current so that the work function of the second extension gate is reduced. Unlike a work function, a tunneling field effect transistor having a gate structure overlapping a source and a drain.
delete delete delete delete delete The method according to claim 1,
The first and second extension gates may be formed independently of the main gate, or may be extended to the main gate and configured as a single gate together with the main gate. Field effect transistor.

Images