KR102093894B1 - L-type tunnel field-effect transistor with improved operating performance - Google Patents

Abstract

The present invention relates to an L-shaped tunnel field-effect transistor (LTFET) with improved operating performance and, more specifically, to an L-shaped tunnel field-effect transistor with improved operating performance for on and off by supporting to allow a current to quickly flow between a source unit and a drain unit at a threshold voltage or lower by dividing a gate unit making up an L-shaped tunnel field-effect transistor into a plurality of different gates and having different work functions between the plurality of gates. The present invention alleviates a problem where a switching operation between on and off is not quickly performed at a threshold voltage or lower due to a weak current flow of a channel positioned between a source and a gate as an electric field is concentrated on an offset region positioned on a lower portion of the source at the threshold voltage or lower by a corner effect on a corner of a source regions of a conventional LTFET to provide an LTFET consisting of a gate with a plurality of different work functions to operate the LTFET to form a surface potential first on a channel of an offset region positioned between a source and the gate at a threshold voltage or lower, thereby greatly increasing an inclination at the threshold voltage or lower to support to quickly perform a switching operation between on and off of the LTFET to greatly improve operating performance.

Description

L-type tunnel field-effect transistor with improved operating performance

The present invention relates to an L-type tunnel field effect transistor with improved operation performance, and more specifically, to divide a gate portion constituting an L-type tunnel field effect transistor into a plurality of different gates, and to have different work functions between the plurality of gates. The present invention relates to an L-type tunnel field effect transistor having improved operation performance for ON and OFF by supporting a rapid flow of current between a source and a drain under a threshold voltage.

Tunnel field-effect transistors (TFETs) are actively being studied as potential replacements for traditional complementary metal-oxide-semiconductor (CMOS) technologies. The TFET provides a sub-threshold slope (SS), but the on-current (I _ON ) performance is limited. To overcome this limitation, various types of line tunneling TFETs have been recently introduced, including L-type TFETs (hereinafter referred to as LTFETs), U-types (UTFETs) and Z-type TFETs (ZTFETs), but LTFETs show the most efficient performance.

However, these LTFETs have a problem of deteriorating the SS performance due to a two-dimensional (2D) corner effect occurring at the corners of the source, which causes the LTFETs that require rapid current flow between the source and drain to have poor operating performance. Occurs.

In order to remove SS deterioration due to the corner effect caused by the edge of the source that is formed in the LTFET, a solution is to be performed using a fully depleted rounded edge with a gradual doping profile. Has a minor problem.

Korean Registered Patent No. 10-0622675

The present invention divides the gate part constituting the L-type tunnel field effect transistor into a plurality of gates and configures the work functions to be different between the plurality of gates to support rapid current flow between the source part and the drain part. An object of the present invention is to provide an L-type tunnel field effect transistor with improved performance of ON and OFF by improving the performance of the sub-voltage gradient (SS).

The L-type tunnel field effect transistor with improved operation performance according to an embodiment of the present invention includes a source part, a drain part, and a gate part including a first gate and a second gate, wherein the first gate includes the first gate. The first threshold voltage of the first offset region formed between the source portion and the first gate when a voltage below a threshold voltage is applied to the gate portion is configured to be stacked on the second gate. In order to be formed lower than a second threshold voltage of the second offset region formed between the second gates, the first gate and the second gate may be configured to have different work functions.

As an example related to the present invention, the gate portion may be configured to have different heights between the first gate and the second gate.

As an example related to the present invention, the source portion may be configured to have the same height as the height of the first gate.

As an example related to the present invention, the gate portion may include an oxide for insulating the first and second gates from the source and drain portions.

As an example related to the present invention, the drain portion may be doped to a doping level at which a bipolar current flowing from the source portion to the drain portion is suppressed when a voltage equal to or higher than a threshold voltage is applied to the gate portion.

As an example related to the present invention, the work function of the first gate may be configured to be smaller than the work function of the second gate.

In the present invention, due to the corner effect occurring at the corner of the source region of the conventional LTFET, the electric field is concentrated in the offset region located below the source under the threshold voltage, so the current flow in the channel located between the source and the gate is weak, resulting in a threshold voltage. Hereinafter, an improvement in a problem in which a switching operation between ON and OFF cannot be performed quickly is provided, and an LTFET composed of a gate having a plurality of different work functions is provided to provide a channel in an offset region located between a source and a gate below a threshold voltage. The LTFET can be operated so that the surface potential is formed first, and through this, the slope below the threshold voltage is greatly increased, so that the switching operation between ON and OFF of the LTFET is quickly performed, thereby providing an LTFET with greatly improved operation performance. It works.

1 is a schematic diagram of a conventional L-type tunnel field effect transistor.
2 is a graph of transmission characteristics of a conventional L-type tunnel field effect transistor.
3 is an exemplary view showing a contour plot of the tunneling rate and the tunneling rate of a conventional L-type tunnel field effect transistor.
4 is a diagram illustrating a tunneling rate at different source-gate bias voltages of a conventional L-type tunnel field effect transistor.
5A and 5B are configuration diagrams of an L-type tunnel field effect transistor with improved operation function according to an embodiment of the present invention.
6 is a graph showing I _ds -V _gs characteristics of an L-type tunnel field effect transistor with improved operation functions for different first work functions (W _{rk_gate1} ) according to an embodiment of the present invention.
7 is a contour graph of G _tun of an L-type tunnel field effect transistor with improved operation function according to an embodiment of the present invention.
8 is a graph showing I _ds -V _gs characteristics of an L-type tunnel field effect transistor with improved operation function according to height by gate according to an embodiment of the present invention.
FIG. 9 shows the I _ds -V _gs characteristics of the L-type tunnel field effect transistor with improved operation function with different T _j according to an embodiment of the present invention, and the SS and I _ON / I _OFF ratios extracted from the current-voltage characteristics. Graph shown.
10 is a graph showing I _ds -V _gs characteristics of an L-type tunnel field effect transistor with improved operation function for source height change according to an embodiment of the present invention.
11 is a graph of bipolar current change under various conditions of an L-type tunnel field effect transistor with improved operation function according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

Prior to the description, the structure and problems of the existing L-type tunnel field effect transistor (hereinafter, the conventional LTFET) will be described, and in contrast, an improved structure of the L-type tunnel field effect transistor with improved operation performance according to an embodiment of the present invention To explain.

1 is a schematic diagram of a conventional LTFET, as ^{shown, p + (10 20 cm -3} ) doped source (source) region is n ^- sandwiched between (10 ¹² cm ^-3) channels in the first channel It overlaps the gate region. The sandwich channel region may be defined as a first offset region (R _nonoffset ).

In addition, as shown in FIG. 1, there is an offset, which is a second channel formed between the source and the gate and is defined at the bottom (or bottom) of the source, which is defined as the second offset region (R _offset) . You can.

Unless otherwise specified, in the present invention, the existing LTFET is described according to the following parameters, but is not limited thereto.

As an example of the above parameters, source height (H _s ) = 40 nm, oxide thickness (t _ox ) = 2 nm, width of the first offset region (T _j ) = 5 nm, channel length (L _ch ) = 50 nm, second offset The height of the region (R _offset ) (H _offset ) = 10nm, the first offset region (R _nonoffset ) Height (H _nonoffset ) = H _s , gate height (H _g1 ) = H _s + (H _offset -t _ox ) = _{48 nm} , dielectric permittivity (ε _ox ) = 25, metal gate work function (W _{rk_LTFET} ) = 4.72 eV and Drain doping (N _d ) = 10 ²⁰ cm ^-3 will be described as an example.

A computer-aided design tool (TCAD) simulator is used for the performance experiment of the existing LTFET and the DG-LTFET according to an embodiment of the present invention.

Models used for simulation of the existing LTFET of the simulator are dynamic non-local band-to-band tunneling (BTBT) models (hereinafter BTBT models), Fermi statistics and constant mobility models. The BTBT model calculates BTBT in both lateral and one-dimensional (hereinafter 1D) directions. The decision direction is assumed to be <100> on all devices. A constant electron effective tunneling mass of 0.19 m _o was used in all simulations. Unless otherwise specified in the present invention, all simulations were performed at drain source bias (V _ds ) = 0.1 V.

2 is a graph related to transmission characteristics (I _ds -V _gs ) of an existing LTFET, as shown in FIG. 2 (a), a first threshold voltage (V _{th_Rnonoffset} ), which is a threshold voltage of the first offset region, is The second threshold voltage (V _{th_Roffset} ), which is 0.24 V and the threshold voltage of the second offset region, is 0.17 V.

Accordingly, the potential in the second offset region R _offset along the cut line indicated inset at V _gs = 0 V in FIG. _2B is higher than the potential in the first offset region R _nonoffset .

For subsequent analysis, the LTFET's drain-source current (I _ds ) versus gate-source bias (V _gs ) characteristics are shown in Figure 2 (a). Claim 1, the offset region between the gate and the source of direct overlap (R _nonoffset) and the electrical length of the first offset region (R _nonoffset) is the 1D direction.

However, in the second offset region R _offset , the electric field from the gate converges around the sharp edge (the portion indicated by X) of the source region in FIG. 1. This increases the potential of the second offset region (R _offset ) higher compared to the first offset region (R _nonoffset ) for a given bias (until saturation due to electron inversion occurs).

Fig. 2 (b) shows the surface potential of the oxide phase that constitutes the gate at V _gs = 0 V. The electric field can be seen that the potential of the second offset region _(offset R) higher than the potential of the first offset region (R _nonoffset) because converges to (portions indicated by X in Fig. 1) around a sharp corner source.

A first offset region a second threshold voltage (V _{th_Roffset)} for BTBT of the second offset portion (R _offset) a second offset region (R _offset), because the potential is high in comparison to the (R _nonoffset) is the first offset region (R _nonoffset ) is lower than the first threshold voltage for _BTBT (V _{th_Rnonoffset} ).

3 (a) and 3 (b) are contour plots of the tunneling rate (G _tun ) and G _tun at V _gs = 0.21 V, the bias required to generate I _ds = 10 ^-13 A of a conventional LTFET. Respectively.

As shown in FIG. 3, it can be seen that _BTBT occurs only in the second offset region R _offset and the first offset region R _nonoffset is not formed and completely turned off.

4 (a) shows G _tun at different V _gs values. Figure 4 a first threshold voltage (V _{th_Roffset)} with a first threshold voltage (V _{th_Rnonoffset)} from (a) it can be seen that V _gs = 0.17V and = 0.24V V _gs vicinity respectively.

4 (b) is a G _tun contour graph at V _gs = V _{th_Rnonoffset} = 0.24 V.

In FIG. 4 (a), G _tun of the first offset region R _nonoffset is always higher immediately after turning on by applying a voltage above the first threshold voltage to the gate, and BTBT region compared to the second offset region R _offset You can see that it is much larger in this y direction. Therefore, when the first offset region R _nonoffset is turned on, the second offset region R _offset is overwhelmed.

At this time, the meaning that the first offset region or the second offset region described in the present invention is turned on may mean that an electric potential is formed in the first offset region or the second offset region.

A first offset region (R _nonoffset) in G _tun is higher because the second offset region (R _offset) BTBT path is the other hand towards the source or the surface on the side of the second offset portion (R _offset) the first offset region ( R _nonoffset ) because BTBT path is 1D. When the 2D (hereinafter, 2D) BTBT path is naturally longer than the 1D path, G _tun is lowered in the second offset region (R _offset ).

As such, when a source-gate bias voltage below the first threshold voltage (V _gs <0.24 V) is applied to the gate, only the second offset region (R _offset ) with the path and lower G _tun contributes to the BTBT current, It can be seen that the more efficient first offset region R _nonoffset does not contribute.

That is, the existing LTFET has poor performance in the subthreshold region.

In summary, the existing LTFET is a first offset region formed between a source and a gate when a voltage below a threshold voltage is applied to the gate due to a two-dimensional (2D) corner effect occurring at a specific edge of the source ( the second threshold voltage (V _{th_Roffset)} for BTBT of the first second offset region (R _offset) to be formed than in the lower portion of the source threshold voltage (V _{th_Rnonoffset)} for BTBT of R _nonoffset) is formed in the lower, 2 As shown in, the sub-threshold slope is reduced, and the current flowing from the source to the drain does not flow quickly until the V _gs voltage above the threshold voltage is applied to the gate. There is a problem that the switching operation between is quite slow.

Accordingly, the first offset region R _nonoffset is turned on (at bias) with a bias lower than the second offset region R _offset (so that an electric potential is formed or current flows) to satisfy the condition of V _{th_Rnonoffset} <V _{th_Roffset} . If it can be forced, the first offset region (R _nonoffset ) is turned on in the region below the threshold voltage, and is turned on in the condition of R _nonoffset > G _tun in the second offset region (R _offset ) shown in FIG. 4 (a). Therefore, a significant improvement in the slope (hereinafter, SS) below the threshold voltage can be expected, thereby improving the switching operation between ON and OFF of the LTFET.

By improving the above-described problems of the existing LTFET, the L-type tunnel field effect transistor having improved operation performance according to an embodiment of the present invention has a first offset voltage V _{th_Rnonoffset} of the first offset region R _nonoffset . It is configured to be formed under a condition lower than the second threshold voltage V _{th_Roffset} of the region R _offset , and the first offset takes precedence over the surface of the gate in close contact with the second offset region while the source-gate bias voltage is below the threshold voltage. It is configured to flow current between the source and the gate through the surface of the gate in close contact with the region, increasing (slope) the magnitude (slope) of the slope (SS) below the threshold voltage, and increasing or decreasing the slope (SS) between the ON and OFF of the LTFET even below the threshold voltage. It can be supported so that the rapid switching operation of, it will be described in detail with reference to the drawings below.

5A is a configuration diagram of an L-type tunnel field effect transistor (hereinafter, DG-LTFET) according to an embodiment of the present invention, as shown, the DG-LTFET includes a source portion (or source region) 10 and a drain It may be configured to include a sub (or drain region) 30 and a gate portion (or gate region) 20.

In addition, the gate unit 20 may include a first gate (Gate1) 21 and a second gate (Gate2) 22. That is, the gate portion 20 may be composed of a plurality of different gates (21, 22).

In this case, the source part 10 may be configured to have a height H _s equal to the height H _g1 of the first gate 21.

In addition, the gate portion 20 is composed of a state in which the first gate 21 is stacked on the upper (or upper surface) of the second gate 22, and the source of a threshold voltage or less is applied to the gate portion 20. _{-When the} gate bias voltage V _gs is applied, the first threshold voltage V _{th_Rnonoffset of} the first offset region R _nonoffset 41 formed between the source unit 10 and the first gate 21 is the The first gate 21 and the first gate 21 to be formed lower than the second threshold voltage V _{th_Roffset of} the second offset region R _offset 42 formed between the source unit 10 and the second gate 22 The second gate 22 may be configured to have different work functions.

In addition, the gate portion 20 may be configured to have different heights between the first gate 21 and the second gate 22, and thus, the first gate 21 and the second corresponding to the first gate 21. The first threshold voltage of the first offset region 41 may be configured to be lower than the second threshold voltage of the second offset region 42 corresponding to the second gate 22.

In addition, the gate part 20 may include an oxide to insulate the first and second gates 21 and 22 from the source part 10 and the drain part 30.

The gate portion of the DG-LTFET has a dual gate (DG) structure, and the two gates, the first gate (gate1) 21 and the second gate (gate2) 22, have different work functions and heights. You can.

The first threshold voltage (V _{th_Rnonoffset)} a second schematic view DG-LTFET to achieve a threshold voltage smaller than the condition (V _{th_Roffset)} (V _{th_Rnonoffset <th_Roffset} V) (diagram) is shown in Figure 5a.

The gate portion 20 of the DG-LTFET has a first gate (21) and a second gate (gate2) (22) having different work functions (W _{rk_gate1} , W _{rk_gate2} ) and heights (H _g1 , H _g2 ), respectively. ).

That is, the first gate 21 and the second gate 22 may be made of different materials having different work functions.

At this time, the DG-LTFET is the first gate height (H _g1 ) = the height of the first offset region (H _nonoffset ) = the height of the source portion (H _s ) = 40nm, the second gate height (H _g2 ) = H _nonoffset -H _It will be described as an example consisting of _g1 + (H _offset (height of the second offset region)-t _ox (oxide thickness)) = 8nm and the width (T _j) = 5nm of the first offset region.

Also, it is preferable that the first work function W _{rk_gate1} of the first gate 21 is always lower (smaller) than the second work function W _{rk_gate2} of the second gate 22.

In addition, the second work function (W _{rk_gate2)} is described, for example, to be fixed to the W _{rk_gate2} = 4.72eV.

The DG-LTFET process flow may be based on an existing LTFET process flow, as shown in FIG. 5A.

The DG-LTFET process flow follows the existing LTFET process flow until the metal organic chemical vapor deposition of the second gate 22 (similar to the gate deposition of the LTFET).

Thereafter, two additional steps may be added, the DG-LTFET being masked to protect the gate oxide and channel region, and the second gate 22 may be selectively etched according to a desired height. You can.

Further, the metal of the first gate 21 may be deposited in a recess created by etching the second gate 22.

And the second first work function (W _{rk_gate1)} of gate 22 low work function first gate (21) than (W _{rk_gate2)} in accordance with the configuration as described above, the flatness of the second offset portion (R _offset) compared to the voltage (V _fb), thereby increasing the flat voltage (V _fb) of the first offset region (R _nonoffset).

5B shows V _fb (red symbol) of the DG-LTFET with W _{rk_gate1} = 4.5eV and W _{rk_gate2} = W _{rk_LTFET} . Also, V _fb (blue symbol) of the existing LTFET is displayed for comparison.

As illustrated, it can be seen that the potential of the first offset region R _nonoffset is increased in the DG-LTFET rather than the second offset region R _offset .

Since there is a 2D effect around the corner in the conventional LTFET, the potential does not change abruptly as the first gate of the DG-LTFET changes from the second gate. That is, in the conventional LTFET, the electric field converges around the source corner at the bottom of the gate corresponding to the bottom of the second gate.

However, in the DG-LTFET according to the present invention, the equilibrium of the potential is set between the first and second gates near the center of the second offset region R _offset , and the DG-LTFET potential is W _{rk_gate2} = W _{rk_LTFET and} then the LTFET potential. Overlap. When the first work function is less than the second work function (W _{rk_gate1} <W _{rk_gate2} ), the potential of the first offset region is increased, and through this, the increased potential of the first offset region R _nonoffset is the first threshold voltage ( V _{th_Rnonoffset)} .

If the first work function is properly adjusted to be smaller than the second work function, a condition (V _{th_Rnonoffset} <V _{th_Roffset} = 0.17 V) in which the first threshold voltage is formed smaller than the second threshold voltage can be achieved.

At this time, since the second work function W _{rk_gate2} = W _{rk_LTFET} = 4.72 eV, the second threshold voltage V _{th_Roffset} of the DG-LTFET is the same as V _{th_Roffset} of the existing LTFET.

6 (a) shows I _ds -V _gs characteristics of the DG-LTFET having a constant second work function W _{rk_gate2} = W _{rk_LTFET} = 4.72 eV and having different first work functions W _{rk_gate1} .

6 (b) and 6 (c) show the slope (SS) of the DG-LTFET below the threshold voltage extracted from the I _ds -V _gs characteristic of the DG-LTFET obtained in FIG. The ratio (I _ON / I _OFF ) is shown respectively.

In addition, the I _ds -V _gs characteristic (black square) of the existing LTFET is shown for reference. I _ON is extracted at V _gs = 0.7 V, and I _OFF can be defined as I _ds = 10 ^-17 A.

When the first work function is W _{rk_gate1} = 4.675eV (red circle), the first threshold voltage V _{th_Rnonoffset} decreases to 0.189V. Compared to the conventional LTFET, the first offset region R _nonoffset is turned on at a lower gate voltage in the subthreshold region together with the second offset region R _offset .

BTBT is a second offset region (R _offset) the first offset region (R _nonoffset) (Fig. 4 (a)) because it is more efficient, the current drain portion in the threshold voltage or less (subthreshold) regions more rapid increase in as compared to . Therefore, kink occurs in the I _ds -V _gs curve at the turning point (V _gs ~ 0.189 V) at which the first offset region R _nonoffset is turned on.

When the first work function is W _{rk_gate1} = 4.65 eV (green triangle), the first threshold voltage V _{th_Rnonoffset} is reduced to V _gs = 0.167 V and the first threshold voltage is less than the second threshold voltage (V _{th_Rnonoffset)} <V _{th_Roffset} ) is achieved, wherein the DG-LTFET exhibits an amazing SS of less than 10 mV / dec as shown in FIG. 6.

When the first work function is W _{rk_gate1} = 4.625 eV (blue star), the first threshold voltage V _{th_Rnonoffset} decreases more than 0.1448V (<V _{th_Roffset} ). As shown in W _{rk_gate1} = 4.625eV (blue star) and W _{rk_gate1} = 4.5eV (orange diamond), kink disappears when the first threshold voltage is less than the second threshold voltage (V _{th_Rnonoffset} <V _{th_Roffset} ), and the SS disappears. There is no change to the threshold and there is only a threshold voltage shift.

As described above, when the gate part is composed of a plurality of gates and the work functions of the first gate and the second gate are different, about 16% of I _ON / I _OFF of the DG-LTFET (W _{rk_gate1} = 4.625 eV) than the existing LTFET Improvement is observed.

Figure 7 (a) is a G _tun contour graph of DG-LTFET with W _{rk_gate1} = 4.65 eV at V _gs (= 0.172 V) bias required to achieve a drain current of 10 ^-13 A.

7 (b) shows the contour graph extracted in FIG. 7 (a).

For reference, FIG. 7 (b) also shows G _tun at V _gs (V _gs bias = 0.21 V as shown in FIG. 3 (b)) required to generate a drain current of 10 ^-13 A in a conventional LTFET.

As can be seen in Figure 7 (b), the existing LTFET contributes to the generation of the source-drain current I _ds in the second offset region R _offset where V _gs is below the threshold voltage, but the DG-LTFET according to the present invention Is highly dependent on the current in the first offset region (R _nonoffset ) with the current contribution in the second offset region (R _offset ) to produce the same amount of I _ds as the existing LTFET, where V _gs is below the threshold voltage.

As is described in 4 (a), first because it is more efficient G _tun of the offset region (R _nonoffset), G _tun as V _gs bias is increased, the geometry in a much larger area of the first offset region (R _nonoffset) Increasing exponentially, below the threshold voltage, the DG-LTFET exhibits a much steeper SS than the conventional LTFET.

On the other hand, the existing LTFET relies only on the inefficient BTBT of the second offset region R _offset until V _{th_Rnonoffset} = 0.24V.

To optimize device performance, the effects of changes in key parameters including H _g1 , H _g2 , H _s / T _j and N _d were investigated.

To investigate the effect of H _g1 and H _g2 values, fixed W _{rk_gate1} = 4.5eV and W _{rk_gate2} = W _{rk_LTFET} , H _s = H _nonoffset = 40nm, H _offset = 10 nm and T _j = 5 nm and different H _g1 And H _g2 = H _nonoffset -H _g1 + (H _offset -t _ox ), the I _ds -V _gs characteristics of the DG-LTFET are shown in FIG. 8.

8, it can be seen that I _ds is independent of H _g1 and H _g2 .

To investigate the effect of T _j on device performance, fixed W _{rk_gate1} = 4.5eV, W _{rk_gate2} = W _{rk_LTFET} , H _g1 = H _nonoffset = 40nm, H _offset = 10nm and H _g2 = H _nonoffset -H _g1 + ( I _ds -V _gs characteristics of DG-LTFET with H _offset -t _ox ) = 8 nm and different T _j (Figure 9 (a)) and SS extracted from this current-voltage characteristic (Figure 9 (b)) and I _{The ON} / I _OFF ratio (FIG. 9 (c)) is shown through FIG.

As T _j increases, the result shows that the ratio of I _ON / I _OFF decreases. This is because the BTBT path length increases as T _j increases. DG-LTFET devices with T _j below 5 nm are expected to degrade device performance by the well-known quantum confinement effect, so T _j = 5 nm devices show optimum performance.

The effects of various H _s are investigated. Fixed H _{rk_gate1} = 4.5eV, W _{rk_gate2} = W _{rk_LTFET} , H _g1 = H _s = H _nonoffset , H _g2 = H _nonoffset -H _g1 + (H _offset -t _ox ) = 8 nm and T _j = 5 nm The I _ds -V _gs characteristic of the DG-LTFET for _s is shown in FIG. 10.

By maintaining H _g1 = H _s , H _offset = 10 nm and H _g2 = 8 nm, the electric field vector distribution in the DG-LTFET remains the same as H _s changes and the BTBT region is simply scaled to H _s .

The increase and decrease of the BTBT region by H _s increases and decreases the I _ON / I _OFF ratio without changing the SS, as is clearly shown in FIGS. 10 (a) and 10 (b).

Finally, the bipolar current of the DG-LTFET is discussed. The bipolar drain current of the TFET depends on the drain-channel junction. In DG-LTFET, the drain-channel junction is controlled by W _{rk_gate2} = W _{rk_LTFET} by the second gate.

In the same work function, the electrostatics of the drain-channel junction of the DG-LTFET is the same as that of the conventional LTFET.

11 (a) shows that the second work function W _{rk_gate2} = W _{rk_LTFET} and when the first work function W _{rk_gate1} changes, the polarity currents of the DG-LTFET and the conventional LTFET are the same.

Changes in W _{rk_gate1} in DG-LTFET drain-channel does not affect the joint. The same factors apply to other design parameter variations of DG-LTFETs including H _s , H _g1 , H _g2 , T _j .

In other words, the DG-LTFET exhibits a bipolar current equivalent to that of a conventional LTFET unless the static electricity of the drain-channel junction is affected.

Figure 11 (b) shows different N _d for DG-LTFETs with W _{rk_gate1} = 4.5eV, W _{rk_gate2} = W _{rk_LTFET} , H _g1 = H _nonoffset = 40nm, H _g2 = H _offset -t _ox = 8nm and T _j = 5nm. When the value is considered, it shows I _ds -V _gs characteristic. The doping level for the drain portion of 10 ¹⁸ cm ^-3 is shown to suppress the bipolar current without affecting I _ON .

Because the first threshold voltage is greater than the second threshold voltage (V _{th_Rnonoffset} > V _{th_Roffset} ), a more efficient 1D BTBT with a higher G _tun as the first offset region (R _nonoffset ) in the source section has a higher bias in the region below the threshold voltage Occurs as

Conventional LTFETs do not fully utilize the channel during a subthreshold region because the first threshold voltage is greater than the second threshold voltage (V _{th_Rnonoffset} > V _{th_Roffset} ).

As described above, the DG-LTFET according to an embodiment of the invention uses a low double material than the gate stack structure of a top gate work function (W _{rk_gate1)} of the bottom gate work function (W _{rk_gate2).}

This increases the potential of the first offset region (R _nonoffset) and, thereby reduce the first threshold voltage (V _{th_Rnonoffset)} of the first offset region (R _nonoffset).

The DG-LTFET lowers the first threshold voltage V _{th_Rnonoffset} <V _{th_Roffset} ) of the first offset region R _nonoffset by inverting the threshold condition of the existing LTFET. The first offset region (R _nonoffset ) having a high G _tun is turned on before the second offset region (R _offset ) in the region where V _gs of the DG-LTFET is below a threshold voltage and represents SS less than 10 mV / dec.

For the first work function on the DG-LTFET (W _{rk_gate1)} is to achieve a 10mv / dec SS now be sufficiently smaller than the W _{rk_gate2.}

I _ds and SS were found to be independent of H _g1 and H _g2 . The DG-LTFET was further evaluated for different device dimensions including T _j and H _s while maintaining the same electric field vector distribution. I _ds decreases with increasing T _j and increases with H _s . The N _d value of 10 ¹⁸ cm ^-3 was found to significantly reduce the bipolar I _ds .

As described above, according to the present invention, an electric field is concentrated in an offset region located below a source under a threshold voltage due to a corner effect occurring at a corner of a source region of a conventional LTFET, and current flow in a channel located between the source and the gate. This is weak and improves the problem that switching operation between ON and OFF cannot be performed quickly below the threshold voltage, and provides an LTFET composed of gates having a plurality of different work functions to provide a position between the source and the gate below the threshold voltage. The LTFET can be operated so that the surface potential is first formed in the channel of the offset region, which greatly increases the slope below the threshold voltage, thereby enabling the switching operation between the ON and OFF of the LTFET to be performed quickly, greatly improving the operation performance. LTFET can be provided.

The above-described contents may be modified and modified without departing from the essential characteristics of the present invention to those skilled in the art to which the present invention pertains. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

10: source section 20: gate section
21: first gate 22: second gate
30: drain portion 41: first offset region
42: second offset region

Claims (6)

In the L-type tunnel field effect transistor,
Source part;
Drain portion; And
A gate portion including a first gate and a second gate
It includes,
The gate portion is configured such that the first gate is stacked on top of the second gate, and the first offset region is formed between the source portion and the first gate when a voltage equal to or less than a threshold voltage is applied to the gate portion. The first threshold voltage is configured to have a different work function between the first gate and the second gate to be formed lower than the second threshold voltage of the second offset region formed between the source portion and the second gate. L-type tunnel field effect transistor with improved operating performance, characterized in that.
The method according to claim 1,
The gate portion is configured to have different heights between the first gate and the second gate, the L-type tunnel field effect transistor with improved operating performance.
The method according to claim 1,
The source portion is configured to have the same height as the height of the first gate L-type tunnel field effect transistor with improved operating performance.
The method according to claim 1,
The gate portion includes an oxide for insulating the first and second gates from the source and drain portions, and the L-type tunnel field effect transistor with improved operating performance.
The method according to claim 1,
The L-type tunnel field effect transistor with improved operating performance is characterized in that the drain portion is doped to a doping level at which a bipolar current flowing from the source portion to the drain portion is suppressed when a voltage equal to or higher than a threshold voltage is applied to the gate portion.
The method according to claim 1,
The L-type tunnel field effect transistor with improved operating performance, characterized in that the work function of the first gate is smaller than the work function of the second gate.

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