KR20110017756A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to modulate gate shift clocks by using one control signal. CONSTITUTION: A liquid crystal display panel includes data lines, gate liens, a plurality of TFTs and liquid crystal cells. The liquid crystal cells are connected to the TFTs. A data driving circuit supplies positive and negative data voltages to the data lines. A gate driving circuit successively supplies a gate pulse to the gate lines. A timing controller generates a single control signal. A gate shift clock modulation circuit modulates gate shift clocks.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

Various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and electroluminescent devices (ELs). have.

BACKGROUND ART Liquid crystal display devices have tended to be gradually widened due to their light weight, thinness, and low power consumption. The liquid crystal display device is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment, indoor and outdoor advertising display devices, and the like. The liquid crystal display displays an image by controlling an electric field applied to the liquid crystal cells to modulate the light incident from the backlight unit.

In an active matrix type liquid crystal display device, the voltage charged in the liquid crystal cell is influenced by a kickback voltage (or feed-through voltage, ΔVp) generated by the parasitic capacitance of the TFT (Thin Film Transistor). The kickback voltage DELTA Vp is expressed by Equation 1 below.

Here, 'Cgd' is a parasitic capacitance formed between the gate terminal of the TFT connected to the gate line and the drain terminal of the TFT connected to the pixel electrode of the liquid crystal cell, and 'ΔVg' is the gate high of the gate pulse supplied to the gate line. It is the voltage difference between the voltage and the gate low voltage. Due to the kickback voltage, the voltage applied to the pixel electrode of the liquid crystal cell is changed to cause flicker in the display image.

Gate pulse modulation (GPM) can reduce kickback voltage by reducing the voltage difference (ΔVg) of the gate pulse (or scan pulse). This gate modulation technique controls the modulation timing of the shift clocks using a plurality of control signals. However, in order to implement the gate modulation technique, the timing controller needs to add output pins to output a plurality of control signals.

According to the driving method of the liquid crystal display, the amount of data voltage charging of the liquid crystal cells may vary, and thus, display quality may be degraded. Therefore, a method for compensating for the variation in the amount of charge of the liquid crystal cell is required.

Accordingly, an object of the present invention is to provide a liquid crystal display device which modulates gate shift clocks with one control signal and compensates the amount of charge of a liquid crystal cell.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes data lines to which a data voltage is supplied, gate lines to which a gate pulse synchronized with the data voltage is sequentially applied, the data lines and the data line. A liquid crystal display panel comprising a plurality of TFTs connected to intersections of gate lines, and liquid crystal cells connected to the TFTs; A data driver circuit for supplying a positive / negative data voltage to the data lines; A gate driving circuit sequentially supplying a gate pulse to the gate lines using a gate start pulse and modulated gate shift clocks; A timing controller for generating a single control signal for modulating said gate start pulses, gate shift clocks, and said gate start pulses; And a gate shift clock modulation circuit for modulating the gate shift clocks in response to the single control signal.

The timing controller generates first and second control signals having a predetermined time difference. The timing controller has an exclusive OR gate that outputs the single control signal as a result of an exclusive NOR of the first and second control scenes.

The low logic section of the first control signal overlaps a falling edge of odd gate shift clocks among the gate shift clocks. The low logic section of the second control signal overlaps the falling edge of even gate shift clocks among the gate shift clocks.

At least one of the phase difference, the duty ratio, and the pulse width is different from the first and second control signals.

The present invention can reduce the number of pins of the timing controller and the power integrated circuit (IC) by modulating the gate shift pulses using a single control signal, and furthermore, by generating a two-phase pulse as a single control signal, The amount of filling variation can be compensated for.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 10.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel having a pixel array 20, a plurality of source drive ICs 11, a gate driving circuit 13, and a timing. The controller 21 and the power IC 22 are provided with a printed circuit board 14 ("PCB"). A backlight unit for uniformly irradiating light onto the liquid crystal display panel may be disposed below the liquid crystal display panel.

The liquid crystal display panel includes an upper glass substrate and a lower glass substrate 15 facing each other with a liquid crystal layer interposed therebetween. The pixel array 20 of the liquid crystal display panel displays video data including liquid crystal cells arranged in a matrix by a cross structure of data lines and gate lines. The pixel array 20 includes TFTs formed at intersections of data lines and gate lines, and pixel electrodes connected to the TFTs. The pixel array 20 may be implemented in various ways. For example, the pixel array 20 may be implemented as the pixel array of FIG. 7 in which neighboring liquid crystal cells share one data line, thereby reducing the number of data lines and source drive ICs. Each of the liquid crystal cells of the pixel array 20 is driven by a voltage difference between a pixel electrode charging a data voltage through a TFT and a common electrode to which a common voltage is applied to display an image of video data by adjusting the amount of light transmitted. . A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal display panel. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and in-plane switching (IPS) mode and fringe field switching (FFS) mode. In the case of the same horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode.

The liquid crystal mode of the liquid crystal display panel applicable to the present invention may be implemented in any liquid crystal mode as well as in the TN mode, VA mode, IPS mode, FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The output channels of each of the source drive ICs 11 are connected 1: 1 to the data lines of the pixel array 20. The source drive ICs 11 are data driving circuits for supplying the positive / negative data voltages to the data lines of the pixel array 20 under the control of the timing controller 21. The source drive ICs 11 sample and latch digital video data input from the timing controller to convert the serial data transmission scheme into digital video data of the parallel data transmission scheme. The source drive ICs 11 receive a positive / negative gamma compensation voltage. The source drive ICs 11 convert the digital video data into the positive / negative analog video data voltage according to the polarity control signal input from the timing controller using the positive / negative gamma compensation voltage. The source drive ICs 11 output the positive / negative data voltages to the data lines of the pixel array 20 in response to the source output enable signal input from the timing controller. The source drive ICs 11 may be bonded onto the lower glass substrate of the liquid crystal display panel by a chip on glass (COG) process, and may also be a tape carrier package (TCP) 12 by a tape automated bonding (TAB) process. It may be bonded to the lower glass substrate of the liquid crystal display panel in the form.

The gate driving circuit 13 receives the gate start pulse Vst and the gate shift clocks GCLK1 ′ to GCLK4 ′ input from the power IC 22 to sequentially process the gate pulses to the gate lines of the pixel array 20. To supply. The gate driving circuit 13 is mounted on TCP and bonded to the lower glass substrate of the liquid crystal display panel by a TAB process, or directly formed on the lower glass substrate simultaneously with the pixel array 20 by a GIP (Gate In Panel) process. Can be. The gate driving circuit 13 may be disposed on both sides of the pixel array 20 or on one side of the pixel array 20. The gate start pulse Vst controls the timing of the first gate pulse. The gate shift clocks GCLK1 'to GCLK4' are clock signals for shifting the gate start pulse GSP. The gate shift clocks GCLK1 'to GCLK' are lowered by the power IC 22 at the gate high voltage Vgh near the falling edge. Gate shift clocks GCLK1 'to GCLK4' are input to a source terminal of a pull-up transistor connected to the shift register output terminal of the gate driving circuit 13. Therefore, the gate pulses supplied to the gate lines are modulated in the same form as the gate shift clocks GCLK1 'to GCLK4', thereby lowering the gate high voltage Vgh near its falling edge. By the modulation of the gate pulse, the voltage difference between the gate high voltage Vgh and the gate low voltage Vgh of the gate pulse is decreased in Equation 1, thereby reducing the kickback voltage of the liquid crystal cell.

The PCB 14 on which the timing controller 21 and the power IC 22 are mounted is connected to the source drive ICs 11 through a flexible circuit board. The timing controller 21 receives digital video data input from an external system board through an interface, such as a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface, through a mini LVDS interface. Supplies). The timing controller 21 may include timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a dot clock CLK input through an LVDS interface or a TMDS interface. Get input. The timing controller 21 uses the timing signals Vsync, Hsync, DE, and CLK to adjust the data timing control signal for controlling the operation timing of the source drive ICs 11 and the operation timing of the gate driving circuit 13. Generate a gate timing control signal for control. The timing controller 21 controls the gate timing control signal so that the digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array 20 of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer) Hz. And the frequency of the data timing control signal can be multiplied by a frame frequency reference of 60 x i (i is a positive integer of 2 or more) Hz.

The data timing control signal output from the timing controller 21 includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), Polarity control signal POL and the like. The source sampling clock SSC is a clock signal that controls the data sampling operation of the source drive ICs 11 based on the rising or falling edge. The source start pulse SSP controls the data sampling start time of the source drive ICs 11. If data and data timing control signals are transmitted between the timing controller 21 and the source drive ICs 11 through the mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs 11. The source output enable signal SOE controls the output timing of the source drive ICs 11.

The gate timing control signal output from the timing controller 21 includes a gate start pulse Vst, gate shift clocks GCLK1 to GCLK4, a gate output enable signal GOE, and a GPM control signal FLK. Include. The first to fourth gate shift clocks GCLK1 to GCLK4 are four-phase clocks sequentially shifted with a predetermined time difference. The conventional timing controller generates two GPM control signals in order to modulate the four phase gate shift clock, but the timing controller 21 of the present invention modulates each of the four phase gate shift clocks with one GPM control signal.

The power IC 22 receives the gate start pulse Vst, the gate shift clocks GCLK1 to GCLK4 and the GPM control signal FLK from the timing controller 21. The level shifter of the power IC 22 is suitable for driving the TFTs of the pixel array 20 using the voltages of the gate shift clocks GCLK1 to GCLK4 input from the timing controller 21 at a low voltage of TTL (Transistor Transistor Logic) or LVDS level. Level shifting to a gate high voltage Vgh of 15 V or more and modulating each of the gate shift clocks GCLK1 to GCLK4 in response to the GPM control signal FLK. Thus, the level shifter of the power IC 22 includes a gate shift clock modulation circuit. The first to fourth gate shift clocks GCLK1 'to GCLK4' modulated by the power IC 22 are shifted to the shift register of the gate driving circuit 13 as four-phase clocks sequentially shifted by a predetermined time difference. Is entered.

3 shows a GPM control signal generation circuit in the timing controller 21.

Referring to FIG. 3, the timing controller 21 generates first and second GPM control signals FLK1 and FLK2. This timing controller 21 has an exclusive negative logic gate (EX-NOR) 31. The exclusive negative OR gate 31 performs an OR operation on the first and second GPM control signals FLK1 and FLK2 and outputs the result. Therefore, the GPM control signal FLK output from the timing controller 21 is generated in low logic only when the logic values of the first and second GPM control signals FLK1 and FLK2 are different from each other.

4 shows the level shifter of the power IC 22 in detail.

Referring to FIG. 4, the level shifter of the power IC 22 includes the FLK sampling logic section 41. In Fig. 4, Q1 to Q4 are transistors, and R1 and R2 are resistors.

The FLK sampling logic section 41 raises the voltage of the first gate shift clock GCLK1 to the gate high voltage Vgh level, and 4i (i is a positive integer) + first low logic section of the GPM control signal FLK. (Or GPM time) turns on first transistor Q1. The first transistor Q1 lowers the gate high voltage Vgh under the control of the FLK sampling logic unit 41 to output the modulated first gate shift clock GCLK1 ′. The FLK sampling logic unit 41 raises the voltage of the second gate shift clock GCLK2 to the gate high voltage Vgh level and the second transistor Q2 during the 4i + 2th low logic section of the GPM control signal FLK. Turn on. The second transistor Q2 lowers the gate high voltage Vgh under the control of the FLK sampling logic unit 41 to output the modulated second gate shift clock GCLK2 '. The FLK sampling logic unit 41 raises the voltage of the second gate shift clock GCLK2 to the gate high voltage Vgh level and performs the third transistor Q3 during the 4i + 3th low logic section of the GPM control signal FLK. Turn on). The third transistor Q3 lowers the gate high voltage Vgh under the control of the FLK sampling logic unit 41 and outputs a modulated third gate shift clock GCLK3 '. The FLK sampling logic unit 41 raises the voltage of the fourth gate shift clock GCLK4 to the gate high voltage Vgh level and the fourth transistor Q4 during the 4i + 4th low logic periods of the GPM control signal FLK. Turn on. The fourth transistor Q4 lowers the gate high voltage Vgh under the control of the FLK sampling logic unit 41 and outputs a modulated fourth gate shift clock GCLK4 '.

5 is a waveform diagram illustrating gate shift clocks GCLK1 to GCLK4 and GPM control signals FLK1, FLK2, and FLK according to a first embodiment of the present invention. 6 is a waveform diagram showing modulated gate shift clocks GCLK1 'to GCLK4'.

The first and second GPM control signals FLK1 and FLK2 generated in the timing controller 21 have a predetermined time difference. The low logic section of the first GPM control signal FLK1 overlaps the high logic section (or pulse width period) of the second GPM control signal FLK2 and further includes the first and third gate shift clocks GCLK1 and GCLK3. Overlap with the polling edge of. The low logic section of the second GPM control signal FLK2 overlaps the high logic section of the first GPM control signal FLK1 and overlaps the falling edges of the first and third gate shift clocks GCLK1 and GCLK3. . The odd low logic section of the first GPM control signal FLK1 determines the modulation time GPMt of the first gate shift clocks GCLK1. The even-lowest low logic period of the first GPM control signal FLK1 determines the modulation time GPMt of the third gate shift clocks GCLK3. The odd low logic section of the second GPM control signal FLK2 determines the modulation time GPMt of the second gate shift clocks GCLK2. The even-lowest low logical section of the first GPM control signal FLK1 determines the modulation time GPMt of the fourth gate shift clocks GCLK4.

The phase difference, pulse width, duty ratio, etc. of the first and second GPM control signals FLK1 and FLK2 may be appropriately adjusted according to the driving method of the liquid crystal display panel and the structure of the pixel array 20. For example, the first and second GPM control signals FLK1 and FLK2 may be generated with the same duty ratio as shown in FIG. 5, and may be generated with different duty ratios as shown in FIG. 9.

Although the same polarity and the same data voltage are applied to the liquid crystal cells adjacent to the left and right in the pixel array 20 as shown in FIG. 7, the amount of charge may vary. The present invention provides a modulation time of odd gate pulses applied to odd gate lines of the pixel array 20 as shown in FIG. 7 by varying the duty ratios of the first and second GPM control signals FLK1 and FLK2. By differently controlling the modulation time of the even gate pulses to be applied to each other can be equally compensated for the amount of charge of the adjacent liquid crystal cells.

FIG. 7 is a circuit diagram illustrating a part of the pixel array 20 to which the data line sharing scheme is applied. FIG. 8 is a waveform diagram illustrating a data voltage supplied to data lines and a gate pulse supplied to gate lines of the pixel array 20 illustrated in FIG. 7.

7 and 8, gate pulses synchronized with data voltages whose polarities are inverted in one horizontal period period are sequentially supplied to the gate lines G1 to G6. The gate pulses swing between the gate high voltage (Vgh) and the gate low voltage, and are generated with a pulse width (1/2 H) of 1/2 horizontal period. The gate high voltage Vgh of the gate pulses is modulated based on the GPM control signal FLK.

The first TFT T1 disposed along the first vertical line (the leftmost vertical line) and the second TFT T2 disposed along the second vertical line store the data voltages from the first data line DL1. Time division supply to the first and second pixel electrodes P1 and P2. The first TFT T1 is turned on according to the modulated gate pulses from the odd gate lines GL1, GL3, and GL5 to convert the positive / negative data voltage from the first data line DL1 to the first data line. The first pixel electrode P1 is disposed on the left side of the DL1. To this end, the drain electrode of the first TFT T1 is connected to the first data line DL1, and the source electrode thereof is connected to the first pixel electrode P1 disposed on the left side of the first data line DL1. . The gate electrode of the first TFT T1 is connected to the odd gate lines GL1, GL3, GL5. The second TFT T2 is turned on in response to the gate pulses from the even gate lines GL2, GL4, and GL6 to convert the positive / negative data voltage from the first data line DL1 to the first data line DL1. Is supplied to the second pixel electrode P2 disposed on the right side. To this end, the drain electrode of the second TFT T2 is connected to the first data line DL1, and the source electrode thereof is connected to the second pixel electrode P2 disposed on the right side of the first data line DL1. . The gate electrode of the second TFT T2 is connected to the even gate lines GL2, GL4, GL6. Among the data voltages of the same polarity sequentially supplied through the first data line DL1, after the first data voltage is charged in the first liquid crystal cell, the second data voltage is charged in the second liquid crystal cell.

The third TFT T3 disposed along the third vertical line, and the fourth TFT T4 disposed along the fourth vertical line, transmit the data voltages from the second data line DL2 to the third and fourth pixel electrodes. Time division supply to (P3, P4). The third TFT T3 is turned on in response to the gate pulses from the even gate lines GL2, GL4, and GL6 to convert the positive / negative data voltage from the second data line DL2 to the second data line DL2. Is supplied to the third pixel electrode P3 disposed on the left side. To this end, the drain electrode of the third TFT T3 is connected to the second data line DL2, and the source electrode thereof is connected to the third pixel electrode P3 disposed on the left side of the second data line DL2. . The gate electrode of the third TFT T3 is connected to the even gate lines GL2, GL4, GL6. The fourth TFT T24 is turned on according to the gate pulses from the odd gate lines GL1, GL3, and GL5 to convert the positive / negative data voltage from the second data line DL2 to the second data line DL2. Is supplied to the fourth pixel electrode P4 disposed on the right side. To this end, the drain electrode of the fourth TFT T4 is connected to the second data line DL2, and the source electrode thereof is connected to the fourth pixel electrode P4 disposed on the right side of the second data line DL2. . The gate electrode of the fourth TFT T4 is connected to the odd gate lines GL1, GL3, GL5. Among the data voltages of the same polarity sequentially supplied through the second data line DL2, after the first data voltage is charged in the fourth liquid crystal cell, the second data voltage is charged in the third liquid crystal cell.

The fifth TFT T5 disposed along the fifth vertical line, and the sixth TFT T6 disposed along the sixth vertical line, transmit data voltages from the third data line DL3 to the fifth and sixth pixel electrodes. Time division supply to (P5, P6). The fifth TFT T5 is turned on in response to the gate pulses from the even gate lines GL2, GL4, and GL6 to convert the positive / negative data voltage from the third data line DL3 to the third data line DL3. Supply to the fifth pixel electrode P5 disposed on the left side of the? To this end, the drain electrode of the fifth TFT T5 is connected to the third data line DL3, and the source electrode thereof is connected to the fifth pixel electrode P5 disposed on the left side of the third data line DL3. . The gate electrode of the fifth TFT T5 is connected to even gate lines GL2, GL4, GL6. The sixth TFT T6 is turned on according to the gate pulses from the odd gate lines GL1, GL3, and GL5 to convert the positive / negative data voltage from the third data line DL3 to the third data line DL3. Is supplied to the sixth pixel electrode P6 disposed on the right side. To this end, the drain electrode of the sixth TFT T6 is connected to the third data line DL3, and the source electrode thereof is connected to the sixth pixel electrode P6 disposed on the right side of the third data line DL3. . The gate electrode of the sixth TFT T6 is connected to the odd gate lines GL1, GL3, GL5. Among the data voltages of the same polarity sequentially supplied through the third data line DL3, after the first data voltage is charged in the sixth liquid crystal cell, the second data voltage is charged in the fifth liquid crystal cell.

The seventh TFT T7 disposed along the seventh vertical line and the eighth TFT T8 disposed along the eighth vertical line may receive data voltages from the fourth data line DL4 on the seventh and eighth pixel electrodes. Time division supply to (P7, P8). The seventh TFT T7 is turned on according to the gate pulses from the odd gate lines GL1, GL3, and GL5 to receive the positive / negative data voltage supplied through the fourth data line DL4. The seventh pixel electrode P7 is disposed on the left side of the DL4. To this end, the drain electrode of the seventh TFT T7 is connected to the fourth data line DL4, and the source electrode thereof is connected to the seventh pixel electrode P7 disposed on the left side of the fourth data line DL4. . The gate electrode of the seventh TFT T7 is connected to the odd gate lines GL1, GL3, GL5. The eighth TFT T8 is turned on according to the gate pulses from the even gate lines GL2, GL4, and GL6 to receive the positive / negative data voltage supplied through the fourth data line DL4 to the fourth data line. The eighth pixel electrode P8 is disposed on the right side of the DL4. To this end, the drain electrode of the eighth TFT T8 is connected to the fourth data line DL4, and the source electrode thereof is connected to the eighth pixel electrode P8 disposed on the right side of the fourth data line DL4. . The gate electrode of the eighth TFT T8 is connected to the even gate lines GL2, GL4, GL6. Among the data voltages of the same polarity sequentially supplied through the fourth data line DL4, after the first data voltage is charged in the seventh liquid crystal cell, the second data voltage is the eighth of the fourth data line DL4. The liquid crystal cell is charged.

If the data voltages of the same polarity are continuously supplied to the data lines DL1 to DL6, and the pulse widths of the gate pulses are the same and the modulation times of the gate pulses are the same, the second, second pixel array 20 as shown in FIG. The data filling amount of the third, fifth and eighth liquid crystal cells is larger than the data filling amount of the first, fourth and sixth liquid crystal cells due to the precharging effect. As shown in FIG. 9, the pulse width and duty ratio of the second GPM control signal FLK2 are smaller than the first GPM control signal FLK1, so that the gate pulses applied to the even gate lines GL2, GL4, and GL6 are shown in FIG. The modulation time GPMt2 is made longer than the modulation time GPMt1 of the gate pulse applied to the odd gate lines GL1, GL3, GL5. As a result, according to the present invention, the data filling amount of the second liquid crystal cell is lowered by the data filling amount of the first liquid crystal cell, thereby controlling the data filling amount of the first and second liquid crystal cells in the same manner.

9 is a waveform diagram illustrating gate shift clocks GCLK1 to GCLK4 and GPM control signals FLK1, FLK2, and FLK according to a second embodiment of the present invention. 10 is a waveform diagram showing modulated gate shift clocks GCLK1 'to GCLK4'.

9 and 10, the first and second GPM control signals FLK1 and FLK2 generated in the timing controller 21 have a predetermined time difference. The low logic section of the first GPM control signal FLK1 overlaps the high logic section (or pulse width period) of the second GPM control signal FLK2 and further includes the first and third gate shift clocks GCLK1 and GCLK3. Overlap with the polling edge of. The low logic section of the second GPM control signal FLK2 overlaps the high logic section of the first GPM control signal FLK1 and overlaps the falling edges of the first and third gate shift clocks GCLK1 and GCLK3. . The odd low logic section of the first GPM control signal FLK1 determines the modulation time GPMt1 of the first gate shift clocks GCLK1. The even-lowest low logical section of the first GPM control signal FLK1 determines the modulation time GPMt1 of the third gate shift clocks GCLK3. The odd low logic period of the second GPM control signal FLK2 determines the modulation time GPMt2 of the second gate shift clocks GCLK2. The even-lowest low logic period of the second GPM control signal FLK2 determines the modulation time GPMt2 of the fourth gate shift clocks GCLK4.

In the pixel array as shown in FIG. 7, the duty ratio of the second GPM control signal FLK2 is smaller than that of the first GPM control signal FLK1 in order to compensate for the non-uniformity of charge amount of the liquid crystal cells adjacent to the left and right. Due to this difference in duty ratio, the low logical section of the second GPM control signal FLK2 is longer than that of the first GPM control signal FLK1. Therefore, the modulation time GPMt2 of the gate pulses applied to the even gate lines G2, G4, and G6 is longer than the modulation time GPMt2 of the gate pulses applied to the odd gate lines G1, G3, G5. .

The timing controller 21 calculates an exclusive negative logical sum EX-NOR of the first and second GPM control signals FLK1 and FLK2 and outputs the result as the final GPM control signal FLK. As a result of the exclusive negative AND operation of the first and second GPM control signals FLK1 and FLK2, the even-lowest low logical section of the GPM control signal FLK is longer than the odd-numbered low logical section. The GPM control signal FLK is output through the single output pin of the timing controller 21.

The inventors of the present application demonstrated the effects of the present invention through experiments. In this experiment, the liquid crystal display having the pixel array as shown in FIG. 7 was used as a sample, and the amount of charge of the liquid crystal cell was uniformly compensated by the first and second GPM control signals FLK1 and FLK2 as shown in FIGS. 9 and 10. Table 1 below shows the signals used in the experiment.

Low voltage High voltage Period High width Vst -5V 25 V 18 ms 14us GCLK1 '-GCLK4' 0 V 25 V 32us 12us FLK1 0 V 3.3 V 20us 4us FLK2 0 V 3.3 V 20us 3us

In Table 1, Vst and GCLK1 'to GCLK4' swing between -5V and 25V at the output of power IC 22. FLK1 and FLK2 swing between 0V and 3.3V at the output of the timing controller 21. The pulse width of FLK2 is set smaller than the pulse width of FLK1, and the duty ratio is smaller than the duty ratio of FLK1. In the signals of Table 1, a pulse period and a high width may vary according to a control setting value. The control setting value may vary depending on the frame frequency of the input image, the pixel array structure, and the resolution of the liquid crystal display panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, the embodiment of the present invention can be applied to a liquid crystal display device requiring a gate pulse regardless of any liquid crystal mode or driving method, as well as other flat panel display devices such as a field emission display (FED). , To compensate for the amount of data charge in electroluminescence devices such as plasma display panels (PDPs), organic light emitting diodes (OLEDs), and electrophoresis displays It may be applied to the modulation of the gate pulse (or scan pulse). Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram illustrating a timing controller, a power IC, and a gate driving circuit.

3 is a circuit diagram illustrating a GPM control signal generator of a timing controller.

4 is a circuit diagram showing a level shifter of a power IC.

5 is a waveform diagram illustrating gate shift clocks and a GPM control signal according to a first embodiment of the present invention.

6 is a waveform diagram illustrating modulated gate shift clocks.

7 is a circuit diagram illustrating an example of a pixel array in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating data and gate pulses applied to the pixel array illustrated in FIG. 7.

9 is a waveform diagram illustrating gate shift clocks and a GPM control signal according to a second embodiment of the present invention.

10 is a waveform diagram illustrating modulated gate shift clocks.

<Description of Symbols for Main Parts of Drawings>

13 gate driving circuit 21 timing controller

22: Power IC 31: Exclusive Negative Gate (EX-NOR)

Claims (9)

Data lines to which a data voltage is supplied, gate lines to which gate pulses synchronized with the data voltage are sequentially applied, a plurality of TFTs connected to intersections of the data lines and the gate lines, and to the TFTs A liquid crystal display panel including the liquid crystal cells; A data driver circuit for supplying a positive / negative data voltage to the data lines; A gate driving circuit sequentially supplying a gate pulse to the gate lines using a gate start pulse and modulated gate shift clocks; A timing controller for generating a single control signal for modulating said gate start pulses, gate shift clocks, and said gate start pulses; And And a gate shift clock modulation circuit for modulating the gate shift clocks in response to the single control signal. The method of claim 1, The timing controller, Generating first and second control signals having a predetermined time difference, And an exclusive OR gate for outputting the single control signal as a result of an exclusive NOR of the first and second control scenes. The method of claim 2, The low logic section of the first control signal overlaps the falling edge of odd gate shift clocks among the gate shift clocks. And a low logic section of the second control signal overlaps a falling edge of even gate shift clocks among the gate shift clocks. The method of claim 3, wherein And at least one of a phase difference and a duty ratio of the first and second control signals are different from each other. The method of claim 4, wherein The liquid crystal cells, A first liquid crystal cell disposed on a left side of a first data line to charge a first data voltage supplied through the first data line; A second liquid crystal cell disposed on the right side of the first data line to charge a second data voltage supplied through the first data line; A fourth liquid crystal cell disposed on a right side of a second data line to charge a first data voltage supplied through the second data line; A third liquid crystal cell disposed on the left side of the second data line to charge a second data voltage supplied through the second data line; A sixth liquid crystal cell disposed on a right side of a third data line to charge a first data voltage supplied through the third data line; A fifth liquid crystal cell disposed on the left side of the third data line to charge a second data voltage supplied through the third data line; A seventh liquid crystal cell disposed on a left side of a fourth data line to charge a first data voltage supplied through the fourth data line; And And an eighth liquid crystal cell disposed on the right side of the fourth data line to charge a second data voltage supplied through the fourth data line. The method of claim 5, The TFTs, A first TFT turned on according to a first gate pulse from a first gate line to supply the first data voltage supplied through the first data line to a pixel electrode of the first liquid crystal cell; A second TFT turned on according to a second gate pulse from a second gate line to supply the second data voltage supplied through the first data line to a pixel electrode of the second liquid crystal cell; A third TFT turned on according to the second gate pulse to supply the second data voltage supplied through the second data line to the pixel electrode of the third liquid crystal cell; A fourth TFT which is turned on according to the first gate pulse and supplies the first data voltage supplied through the second data line to the pixel electrode of the fourth liquid crystal cell; A fifth TFT that is turned on according to the second gate pulse to supply the second data voltage supplied through the third data line to the pixel electrode of the fifth liquid crystal cell; A sixth TFT turned on according to the first gate pulse to supply the first data voltage supplied through the third data line to the pixel electrode of the sixth liquid crystal cell; A seventh TFT turned on according to the first gate pulse to supply the first data voltage supplied through the fourth data line to the pixel electrode of the seventh liquid crystal cell; And An eighth TFT which is turned on according to the second gate pulse and supplies the second data voltage supplied through the fourth data line to the pixel electrode of the eighth liquid crystal cell; The gate high voltage of the first gate pulse is lowered for a first time defined by the odd low logic section of the single control signal, and the gate high voltage of the second gate pulse is the even low logic of the single control signal. And lowering for a second time defined by the interval. The method of claim 6, And the second time is longer than the first time. The method of claim 7, wherein And the duty ratio of the second control signal is smaller than the duty ratio of the first control signal. The method of claim 7, wherein And the pulse width of the second control signal is smaller than the pulse width of the first control signal.

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