KR20110012796A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20110012796A
KR20110012796A KR1020090070664A KR20090070664A KR20110012796A KR 20110012796 A KR20110012796 A KR 20110012796A KR 1020090070664 A KR1020090070664 A KR 1020090070664A KR 20090070664 A KR20090070664 A KR 20090070664A KR 20110012796 A KR20110012796 A KR 20110012796A
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KR
South Korea
Prior art keywords
pattern
mask
layer
groove
semiconductor device
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KR1020090070664A
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Korean (ko)
Inventor
이종수
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090070664A priority Critical patent/KR20110012796A/en
Publication of KR20110012796A publication Critical patent/KR20110012796A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve the operational property of the semiconductor device by preventing a photosensitive film pattern from being collapsed in a fine pattern forming process. CONSTITUTION: A mask film(304) is formed on the upper side of a target layer(302). Grooves corresponding to patterns are formed on the mask film. A hard mask layer(306) is formed on the mask film with the grooves. A photosensitive film is formed on the hard mask layer. A photosensitive pattern is formed on the upper side of the grooves. The mask film is etched based on the photosensitive pattern. The target layer which is exposed by the mask film is etched to form the patterns.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for increasing process margins in forming patterns having different line widths and spacings in cell regions and peripheral regions on semiconductor substrates.

The semiconductor memory device includes a cell area including a plurality of unit cells and a peripheral area including components for controlling data transfer or power supply. The cell region includes a plurality of unit cells composed of capacitors and transistors, and double capacitors are used for temporarily storing data, and transistors respond to control signals (word lines) by using properties of semiconductors whose electrical conductivity varies depending on the environment. To transfer data between the bit line and the capacitor. The peripheral area includes input / output pads for transferring data, data input / output lines, and internal voltage circuits for supplying various voltages in the semiconductor memory device.

Manufacturing equipment for manufacturing semiconductor memory devices is commonly referred to as semiconductor equipment, which can be broadly divided into equipment entering the preprocessing line, equipment entering the postprocessing line, and service equipment. Often, the former process refers to the process of making a circuit on a wafer, and the latter process refers to the process of cutting circuits made on a substrate one by one, connecting and packaging wires to be connected to the outside.

In the process of making circuits on the wafer, it is necessary to record the pattern of the circuit to be manufactured on the wafer, which is often called lithography technology. Lithography techniques include a series of processes that apply photoresist on a wafer and then expose, develop, etch and remove the photoresist. The key to lithography is to pattern the photoresist through an exposure process that injects light after forming the photoresist on the wafer. For example, light scanned by a photoresist on a wafer passes through a reticle having circuit pattern information. The photoresist corresponding to the portion covered by the reticle remains on the wafer, and light passes through the reticle. The photoresist of the areas thus removed is removed. Here, the reticle is made by expanding a mask in which the circuit pattern to be printed is formed in the same size, typically 4 to 5 times.

The lithographic technique described above is widely used in the manufacture of semiconductor memory devices. For example, to determine the position of a component in a semiconductor memory device, including a process of separating active and inactive regions on a silicon wafer, a process of forming a gate pattern, and a process of forming contact plugs and contacts, and the like. Lithography techniques are useful. Recently, as the degree of integration of semiconductor memory devices is increased, finer circuit patterns are required to be printed on silicon wafers. Therefore, a lot of research is being conducted on lithography technology to print fine patterns on silicon wafers, i.e., semiconductor substrates.

1A to 1D are cross-sectional views illustrating a method of forming a pattern in a general semiconductor memory device. Semiconductor memory devices can be divided into cell regions and peripheral regions. In general, a fine pattern is formed in a cell region like a unit cell. In the peripheral region, since the degree of integration is lower than that of a cell region, a pattern has a line width or a distance between patterns. A wide, non-fine pattern is formed. Hereinafter, a process of forming a pattern on a semiconductor substrate will be described by dividing it into a cell region and a peripheral region.

Referring to FIG. 1A, an insulating film 104 and a hard mask layer 106 are sequentially deposited on the etched layer 102 in both the cell region and the peripheral region.

Referring to FIG. 1B, a photosensitive film 108 is deposited on the hard mask layer 106.

Referring to FIG. 1C, the photosensitive film 108 is exposed using a mask defining a pattern to be formed on a semiconductor substrate to form the photosensitive film pattern 110. Although the distance between the photoresist pattern 110 is narrow in the cell region where the fine pattern is formed, the distance between the photoresist pattern 110 is wide in the peripheral region.

Referring to FIG. 1D, the exposed hard mask layer 106 is patterned using the photoresist pattern 110 as an etch mask. Although not shown, etching the exposed insulating layer 104 while the hard mask layer 104 is patterned, and etching the exposed etching target layer 102 while the insulating layer 104 is etched, forms a pattern in the cell region and the peripheral region. can do.

FIG. 2 is a photograph showing a problem of the pattern forming method described with reference to FIGS. 1A to 1D.

As shown, a line photosensitive film pattern having a narrow line width is finely formed in the cell region, but the line photosensitive film pattern having a narrow line width is collapsed in the peripheral region. This phenomenon occurs because the exposure process conditions are poorer in the peripheral area than in the cell area. For example, the margin of the focus distance (Depth Of Focus, DOF) is an example.

The cell region is located at the center of the lens of the exposure equipment during the exposure process, so that the error of the focal length generated during the process is large and thus within the process margin. As a result, defects can be reduced even if the pattern is minutely formed in the cell region. However, unlike the cell area, the peripheral area has a larger focal length error than that of the cell area, thereby increasing the possibility of a defect. In addition, since the peripheral area has a large distance between the photoresist patterns and the property of the photoresist pattern is not firm, the photoresist pattern may be easily collapsed. In order to overcome this problem, a method of additionally forming an auxiliary pattern so as not to collapse the photoresist pattern defining the pattern to be formed in the peripheral area has been proposed, but it is unpredictable where the collapse of the photoresist pattern is not expected and it is necessary to form too many auxiliary patterns. Problems arise and are difficult to apply to manufacturing processes to produce actual products.

In order to solve the above-described conventional problems, the present invention is formed in advance in the position where the photoresist pattern is to be formed to prevent the photoresist pattern from collapsing during the formation of the fine pattern so that the lower portion of the photoresist pattern is supported Thereby, the manufacturing method of a semiconductor element for improving the manufacturing yield of a semiconductor element is provided.

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a groove corresponding to a position of a pattern on a mask film formed on an etched layer; Forming a photoresist pattern on the groove; Etching the mask layer based on the photoresist pattern; And etching the etched layer exposed by the etched mask film to form the pattern.

Preferably, forming a groove corresponding to the position of the pattern on the mask layer formed on the etched layer comprises: depositing a mask layer on the etched layer; Depositing a first photosensitive film on the mask film; Patterning the first photoresist layer to expose the position of the pattern; And partially etching the exposed upper portion of the mask layer by using the patterned first photoresist layer as an etch mask.

Preferably, the depth of the groove is characterized in that about 10 to 15% of the height of the photosensitive film pattern.

Preferably, the depth of the groove is formed to less than 100Å, the photosensitive film pattern is characterized in that formed to about 800 ~ 900 ~.

Preferably, the manufacturing method of the semiconductor device further comprises the step of depositing a hard mask layer on the mask film including the groove.

Preferably, the hard mask layer is characterized in that the groove formed in the cell region is embedded and flattened, and the size of the groove formed in the peripheral region is reduced.

Preferably, the photosensitive film pattern is formed of any one of a positive (positive) and a negative (negative) photosensitive film.

Preferably, the exposure process includes at least one of a resolution enhancement of lithography assisted by chemical shrinkage (RELACS), wet (Immersion), sapphire and reflow processes.

Preferably, the light source used in the exposure process is characterized in that any one of i-line, KrF, ArF and EuV.

Preferably, the reticle used in the exposure process may be any one of a binary mask and a half tone mask.

Preferably, the groove is formed only in the peripheral area by using a cell open / close mask.

According to the present invention, after forming a groove on the etching mask insulating layer formed on the etched layer in the process of forming a fine gate pattern in the semiconductor device, the photoresist pattern is formed on the groove, thereby preventing the photoresist pattern from falling down. There is an advantage that can prevent defects that occur during pattern formation in the peripheral area.

In addition, the present invention does not need to form a separate auxiliary pattern for preventing the pattern from collapsing in the peripheral region, and may selectively form a step such as a groove only in the peripheral region except for the cell region, thereby providing a semiconductor device manufacturing process. The manufacturing yield can be increased while reducing the burden.

The present invention forms a groove in the upper portion of the mask film in order to overcome the defects caused by reduced process margin during manufacturing of the semiconductor device, and then forms a photoresist pattern on the upper portion of the groove. Because of the poor processing conditions in the peripheral region compared with the cell region, the mask pattern defining the narrow line width pattern is likely to collapse. To overcome this, the lower part of the mask pattern can be supported by the side wall of the groove. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of forming a pattern in a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device can be roughly divided into a cell region and a peripheral region. Hereinafter, a process of forming a pattern on a semiconductor substrate will be described by dividing it into a cell region and a peripheral region.

Referring to FIG. 3A, an insulator is deposited on the etched layer 302 to form a mask layer 304 in both the cell region and the peripheral region, and then the first photoresist layer 328 is deposited on the mask layer 304.

Referring to FIG. 3B, the first photoresist pattern is formed by patterning the first photoresist layer 328 by performing an exposure process using a step forming mask that exposes positions of patterns to be formed in the etched layer 302 of the cell region and the peripheral region. 330 is formed. Compared with the related art, the first photoresist pattern 330 has a property opposite to that of the photoresist pattern 110 illustrated in FIG. 1C. That is, the photoresist pattern 110 of FIG. 1C covers the lower layer corresponding to the position of the pattern to be formed and exposes the patterns, but the first photoresist pattern 330 exposes the position where the pattern is to be formed.

Referring to FIG. 3C, the groove 332 is formed by partially etching the upper portion of the mask layer 304 exposed below using the first photoresist pattern 330 as an etch mask, and the remaining first photoresist pattern 330 is formed. Remove. In this case, the depth of the groove 332 is about 100 mm, and the size of the groove 332 formed in the peripheral area is larger than that of the cell area.

Referring to FIG. 3D, the hard mask layer 306 is deposited on the mask film 304 having the groove 332 formed thereon. At this time, the hard mask layer 306 includes an amorphous carbon film (amorphous carbon). The thickness at which the hard mask layer 306 is deposited is such that the grooves 322 in the peripheral region are not buried. That is, although the hard mask layer 306 reduces the size of the grooves 322 formed in the peripheral region, the top of the hard mask layer 306 still has a step. On the other hand, since the groove 332 formed in the cell region is formed narrower than the peripheral region, the step may disappear and the upper portion of the hard mask layer 306 may be flat. In the case of the cell region, since the process conditions are excellent, unlike the peripheral region, even if the groove 332 of the cell region is buried and a step is not secured, the probability of a defect occurring during pattern formation is not high.

Referring to FIG. 3E, the second photoresist layer 308 is deposited on the hard mask layer 306 of the cell region and the peripheral region. At this time, the second photosensitive film 308 is deposited to a thickness of about 800 ~ 900Å.

Referring to FIG. 3F, a second photoresist layer pattern 310 is formed by patterning the second photoresist layer 308 by performing an exposure process using a mask defining positions of patterns to be formed in the cell region and the peripheral region. Therefore, the second photoresist pattern 310 is formed on the groove 322. That is, the lower portion of the second photosensitive film pattern 310 formed in the peripheral area is supported through the step of the groove 322 and does not easily fall unlike the conventional art.

The depth of the groove 332 formed in FIG. 3C was about 100 μs, and when the depth of the groove 332 is formed at about 10 to 15% of the height of the second photoresist pattern 310, the lower portion of the second photoresist pattern 310 is formed. Enough to support However, in the case where the second photoresist layer pattern 310 is formed higher, defects may be prevented as the depth of the groove 332 becomes deeper, and in this case, the mask layer 304 deposited on the etched layer 302. ) Should also be thicker.

In the above-described embodiment of the present invention, a positive photoresist film or a negative photoresist film may be used for the first and second photoresist films 328 and 308 deposited for the pattern formation on the semiconductor substrate according to the embodiment. Can be. In addition, according to an embodiment, the exposure process of the present invention includes one or more of a resolution enhancement of lithography assisted by chemical shrinkage (RELACS), wet (Immersion), sapphire and reflow processes. Further, depending on the size and process conditions of the pattern to be formed on the semiconductor substrate, i-line, KrF, ArF or EuV may be used in the exposure process. In addition, the reticle used in the exposure process may use a binary mask or a halftone mask.

A method of manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of forming a groove corresponding to the position of the pattern on the mask film formed on the etched layer, forming a photoresist pattern on the top of the groove, based on the photoresist pattern Etching the mask film, and etching the etched layer exposed by the etched mask film to form a pattern. That is, after forming a groove for forming a step in the upper portion of the mask film used as an etching mask for etching the etched layer, a photosensitive film pattern is formed on the top of the groove to prevent the photosensitive film pattern from being collapsed by being supported by the groove. do. Furthermore, according to an embodiment, the method of manufacturing a semiconductor device may further include depositing a hard mask layer on a mask film.

In addition, in the embodiments described with reference to FIGS. 3A to 3F, the process is performed in the same manner as in the cell region and the peripheral region. However, when the cell open / close mask is used in another embodiment of the present invention, the cell region and the peripheral region are separated from each other. You may form a pattern. In this case, the cell region is covered, and then a groove is formed only in the upper portion of the mask film formed in the peripheral region, and then a photoresist pattern is formed, because the cell region does not need to form a groove because of a small process error.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1D are cross-sectional views illustrating a method of forming a pattern in a general semiconductor memory device.

Figure 2 is a photograph showing a problem of the pattern forming method described in Figures 1a to 1d.

3A to 3F are cross-sectional views illustrating a method of forming a pattern in a semiconductor memory device according to an embodiment of the present invention.

Claims (11)

Forming a groove corresponding to the position of the pattern on the mask film formed on the etched layer; Forming a photoresist pattern on the groove; Etching the mask layer based on the photoresist pattern; And Etching the etched layer exposed by the etched mask layer to form the pattern Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming a groove corresponding to the position of the pattern on the mask layer formed on the etched layer is Depositing a mask film on the etched layer; Depositing a first photosensitive film on the mask film; Patterning the first photoresist layer to expose the position of the pattern; And And partially etching the exposed upper portion of the mask layer by using the patterned first photoresist layer as an etching mask. The method of claim 1, The depth of the groove is a method of manufacturing a semiconductor device, characterized in that about 10 to 15% of the height of the photosensitive film pattern. The method of claim 3, The depth of the groove is formed to less than 100Å, the method of manufacturing a semiconductor device, characterized in that the photosensitive film pattern is formed to about 800 ~ 900Å. The method of claim 1, And depositing a hard mask layer on the mask layer including the grooves. The method of claim 5, The hard mask layer is a method of manufacturing a semiconductor device, characterized in that the grooves formed in the cell region is buried and flattened and the size of the grooves formed in the peripheral region is reduced. The method of claim 1, The photosensitive film pattern is a semiconductor device manufacturing method, characterized in that formed of any one of a positive (positive) and negative (negative). The method of claim 1, The exposure process includes at least one of a resolution enhancement of lithography assisted by chemical shrinkage (RELACS), wet (Immersion), sapphire (Sapphire) and a reflow process. The method of claim 1, The light source used in the exposure process is any one of i-line, KrF, ArF and EuV manufacturing method of a semiconductor device. The method of claim 1, The reticle used in the exposure process is any one of a binary mask and a half tone mask. The method of claim 1, And forming a groove only in a peripheral area by using a cell open / close mask.
KR1020090070664A 2009-07-31 2009-07-31 Method for fabricating semiconductor device KR20110012796A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11270885B2 (en) 2019-06-26 2022-03-08 Samsung Electronics Co., Ltd. Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11270885B2 (en) 2019-06-26 2022-03-08 Samsung Electronics Co., Ltd. Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device
US11728167B2 (en) 2019-06-26 2023-08-15 Samsung Electronics Co., Ltd. Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device

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