KR20090044556A - Method for manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein an amorphous carbon layer is formed on an alignment key or an overlay vernier having a step, and an HTO is formed thereon, whereby defects are caused by a subsequent process. It is a technology that can prevent the phenomenon.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the prior art.

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the prior art.

Figure 3 is a photograph showing the problem according to the prior art.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, which is caused by poor step coverage when an amorphous carbon layer, which is used as a hard mask layer, is formed on an alignment key or an overlay vernier with a step. It relates to a technology that can compensate for the defects.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a hard mask layer 20 of a tungsten or polysilicon layer is formed on a semiconductor substrate 10, and a photoresist pattern 30 is formed.

Referring to FIG. 1B, the hard mask layer 20 may be etched using the photoresist pattern 30 as a mask to form a hard mask layer pattern (not shown), and the semiconductor substrate may be formed using the hard mask layer pattern (not shown) as a mask. 10) is etched to form a step.

Here, as the design rule of the semiconductor device becomes smaller, the resist thickness decreases to improve the pattern collapse and the resolution. As a result, the thickness of the hard mask layer may not be increased, and as shown in FIG. 1B, the lower portion of the semiconductor substrate may be left without being completely etched due to the lack of etching selectivity between the hard mask layer and the semiconductor substrate.

In order to overcome the above problems, an amorphous carbon layer (a-Carbon) and a silicon oxynitride layer (SiON) are used as the hard mask layer.

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art, and illustrate a bit line forming process as an example.

Referring to FIG. 2A, a bit line material layer 50, an amorphous carbon layer 60, and a silicon oxynitride layer 70 are formed on the semiconductor substrate 40 to overcome the problems described with reference to FIGS. 1A and 1B. After that, a resist pattern 80 is formed. Here, the amorphous carbon layer 60 has a main component of polymer, which is the same as the resist.

At this time, the trench trench (not shown) of the overlay vernier formed in the free area on the semiconductor substrate 40 is formed to have a step of 250 nm or more, so that the amorphous carbon layer having poor step coverage in the trench sidewall, which is a part having a step, is formed. 60 is abnormally formed. In addition, since the silicon oxynitride film 70 is formed on the amorphous carbon layer 60, it is abnormally formed.

Referring to FIG. 2B, a bit line is formed by sequentially etching the silicon oxynitride layer 70, the amorphous carbon layer 60, and the bit line material layer 50 using the resist pattern 80 as a mask.

Then, the resist pattern 80 is removed and cleaned using oxygen plasma.

At this time, the silicon oxynitride film 70 and the amorphous carbon layer 60 of the abnormally formed portion are damaged as shown in ⓐ portion of FIG. 3.

3 is a photograph of an overlay vernier after a resist pattern removal and cleaning process using an oxygen plasma, and it can be seen that the silicon oxynitride film (70 in FIG. 2B) and the amorphous carbon layer (60 in FIG. 2B) are damaged in the area ⓐ. have. In severe cases, the amorphous carbon layer 60 may be lifted.

In the above-described method for manufacturing a semiconductor device according to the related art, in order to increase the accuracy of the alignment key or the overlay vernier, the step of the key is maintained at 1200 to 3000 mW, which is maintained even in the subsequent process.

In addition, an amorphous carbon layer and a silicon oxynitride layer are formed as a hard mask layer on a step, and the step coverage characteristics of the amorphous carbon layer and the silicon oxynitride layer are weak so that an amorphous carbon layer is abnormally formed and the silicon oxynitride layer covers the portion. Since it is impossible to do so, there is a problem that the amorphous carbon layer is damaged or lifted during the removal and cleaning of the resist pattern.

An object of the present invention is to provide a method of manufacturing a semiconductor device that improves the characteristics of the semiconductor device by compensating for damage of the amorphous carbon layer used as the hard mask layer of the conductive wiring.

Method for manufacturing a semiconductor device according to the present invention

Forming a conductive layer for conductive wiring on the semiconductor substrate on which the parent vernier of the overlay vernier is formed;

Forming a hard mask layer on the conductive layer for the conductive wiring by a lamination structure of an amorphous carbon layer, HTO and a silicon oxynitride film;

Forming a resist pattern in a vernier region on the parent vernier region;

Etching the hard mask layer using the resist pattern as a mask to form a vernier, and subjecting the resist pattern to oxygen plasma;

The conductive wiring conductive layer is a conductive layer of a word line (gate), a bit line or a metal wiring,

The overlay vernier is in the form of a box in box or a box in bar,

The HTO is formed at a temperature of 300-900 ℃,

The first HTO is characterized in that it is formed to a thickness of 50-200 nm.

In addition, the method of manufacturing a semiconductor device according to the present invention,

Forming a gate material layer on the semiconductor substrate;

Patterning the gate material layer to form a gate and simultaneously etching a gate material layer of an overlay vernier region to form a trench;

Forming an interlayer insulating film on the entire surface and forming a bit line contact hole connected to the semiconductor substrate through the interlayer insulating film and forming a mother vernier of an overlay vernier exposing the trench;

Forming a bit line conductive layer filling the bit line contact hole on an entire surface thereof;

Forming an amorphous carbon layer on the bit line conductive layer;

Sequentially forming HTO and silicon oxynitride on the amorphous carbon layer;

Forming a resist pattern in a vernier region on the parent vernier region;

Etching the hard mask layer using the resist pattern as a mask to form a vernier, and subjecting the resist pattern to oxygen plasma;

The HTO is formed to a thickness of 50 to 200 nm at a temperature of 700-900 ℃,

The overlay vernier is characterized in that it is in the form of a box in box or a box in bar.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail. However, the present invention is not limited to the embodiments described herein, but may be embodied in other forms, and the embodiments described herein fully disclose the technical idea of the present invention in a thorough and complete manner, and fully convey the spirit of the present invention to those skilled in the art. As provided, the same reference numerals throughout the specification indicate the same components.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention and illustrate a method of forming an overlay vernier. It can also be applied to the alignment key forming process.

Referring to FIG. 4A, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 100. In this case, the device isolation layer is formed of an oxide film having a trench formed in the device isolation region and filling the trench.

A stacked structure of the gate material layer 110, that is, the gate oxide layer (not shown), the gate conductive layer (not shown), the gate metal layer (not shown), and the hard mask layer (not shown) are formed on the entire surface.

Next, a resist is applied on the gate material layer 110, and a resist pattern (not shown) is formed by an exposure and development process using a gate mask (not shown).

Next, the gate material layer 110 is etched using the resist pattern as a mask to form a gate formed of the gate material layer 110.

In this case, the etching process of the gate material layer 110 forms a trench 130 that exposes the semiconductor substrate 100 by simultaneously etching the gate material layer 110 of the overlay vernier region.

Next, an interlayer insulating film 120 is formed over the entire surface.

The interlayer insulating layer 120 is etched to form a bit line contact hole (not shown) that exposes an active region on the semiconductor substrate 100.

In this case, the bit line contact hole forming process may form the mother vernier of the overlay vernier by etching the interlayer insulating layer 120 of the overlay vernier region to expose the bottom of the trench 130. Here, the trench 130 is formed in a rectangular planar structure.

Next, a bit line conductive layer 140 is formed on the entire surface of the bit line contact hole.

In this case, the bit line conductive layer 140 is formed of one of a polysilicon layer, a metal layer, and a stacked structure thereof.

Next, an amorphous carbon layer 150 is formed on the bit line conductive layer 140.

At this time, since the step coverage of the amorphous carbon layer 150 is not good, a defect 160 which is an abnormally formed portion at the corner of the bottom of the trench 130 is formed.

Referring to FIG. 4B, HTO 170 is formed over the entire surface including the defect 160.

At this time, the HTO 170 is formed by a thickness of 50-200 nm at a temperature of 300-900 ℃. Here, the HTO 170 fills a portion of the defect 160 to prevent the oxygen plasma from penetrating through the defect 160.

Next, a silicon oxynitride film 180 is formed on the HTO 170.

At this time, the HTO 170 serves to alleviate the poor step coverage of the amorphous carbon layer 150 and the silicon oxynitride film 180.

Then, a resist (not shown) is applied over the entire surface, and a resist pattern is formed by an exposure and development process using a bit line mask (not shown).

A bit line (not shown) is patterned in the cell region using the resist pattern as a mask, and an island-shaped ruler vernier (not shown) is formed in the center of the overlay vernier region.

At this time, the vernier is formed in a rectangular planar structure. The vernier is formed by the lamination structure of the bit line conductive layer 140, the amorphous carbon layer 150, the HTO 170 and the silicon oxynitride film 180, which are the same lamination structure as the bit line of the cell region.

Accordingly, an overlay vernier composed of a vernier in a stacked structure of the bit line conductive layer 140, the amorphous carbon layer 150, the HTO 170, and the silicon oxynitride layer 180 is formed inside the mother vernier formed of the trench 130. Is formed.

Here, the overlay vernier is formed in a box in box structure.

In addition, the magnetic vernier may be replaced with an island-type resist pattern formed on the silicon oxynitride layer 180.

Another embodiment of the present invention is to form a box in bar (box in bar) structure.

Another embodiment of the present invention is applied to a process of forming an overlay vernier or an alignment key in a process of forming another conductive wiring, for example, a word line (gate) or a metal wiring.

In the method of manufacturing a semiconductor device according to the present invention, HTO is formed between a laminated structure of an amorphous carbon layer and a silicon oxynitride layer used as a hard mask layer during the formation of a conductive wiring to compensate for defects due to poor step coverage ratio. Enables to provide flawless overlay verniers.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

Forming a conductive layer for conductive wiring on the semiconductor substrate on which the parent vernier of the overlay vernier is formed; Forming a hard mask layer on the conductive layer for the conductive wiring by a lamination structure of an amorphous carbon layer, HTO and a silicon oxynitride film; Forming a resist pattern in a vernier region on the parent vernier region; And etching the hard mask layer using the resist pattern as a mask to form a vernier vernier and subjecting the resist pattern to an oxygen plasma process. The method of claim 1, The conductive layer conductive layer is a semiconductor device manufacturing method, characterized in that the conductive layer of the word line (gate), bit line or metal wiring. The method of claim 1, The overlay vernier is a method of manufacturing a semiconductor device, characterized in that the form of a box in (box in box) or a box in bar (box in bar). The method of claim 1, The HTO is formed at a temperature of 300-900 ℃ manufacturing method of a semiconductor device. The method of claim 1, The HTO is formed in a thickness of 50-200 nm manufacturing method of a semiconductor device. Forming a gate material layer on the semiconductor substrate; Patterning the gate material layer to form a gate and simultaneously etching a gate material layer of an overlay vernier region to form a trench; Forming an interlayer insulating film on the entire surface and forming a bit line contact hole connected to the semiconductor substrate through the interlayer insulating film and forming a mother vernier of an overlay vernier exposing the trench; Forming a bit line conductive layer filling the bit line contact hole on an entire surface thereof; Forming an amorphous carbon layer on the bit line conductive layer; Sequentially forming HTO and silicon oxynitride on the amorphous carbon layer; Forming a resist pattern on the vernier region of the mother vernier region; And etching the hard mask layer using the resist pattern as a mask to form a vernier vernier and subjecting the resist pattern to an oxygen plasma process. The method of claim 6, The HTO is formed in a thickness of 50 to 200 nm at a temperature of 300 to 900 ℃ manufacturing method of a semiconductor device. The method of claim 6, The overlay vernier is a method of manufacturing a semiconductor device, characterized in that the form of a box in (box in box) or a box in bar (box in bar).

Images