KR20110008476A - Printed circuit board for semiconductor package and semiconductor package having the same - Google Patents

Printed circuit board for semiconductor package and semiconductor package having the same Download PDF

Info

Publication number
KR20110008476A
KR20110008476A KR1020090065840A KR20090065840A KR20110008476A KR 20110008476 A KR20110008476 A KR 20110008476A KR 1020090065840 A KR1020090065840 A KR 1020090065840A KR 20090065840 A KR20090065840 A KR 20090065840A KR 20110008476 A KR20110008476 A KR 20110008476A
Authority
KR
South Korea
Prior art keywords
circuit board
printed circuit
semiconductor package
core layer
solder resist
Prior art date
Application number
KR1020090065840A
Other languages
Korean (ko)
Inventor
김일규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090065840A priority Critical patent/KR20110008476A/en
Publication of KR20110008476A publication Critical patent/KR20110008476A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

PURPOSE: A printed circuit board for semiconductor package and a semiconductor package having the same are provided to prevent the crack of a semiconductor by preventing interfacial delamination. CONSTITUTION: A core layer(102) has both sides which are opposite to each other. A first interconnection(112) is formed in the one-side of a core layer and ahs a bond finger. A second wiring(114) is formed in the other side of the core layer and has a ball land. A solder resist is formed to expose the bond finger in one side and ball land in the other side of the core layer to outside. The solder resist is formed by laminating the pattern of at least two solder resist pattern film are crossed with each other.

Description

Printed circuit board for semiconductor package and semiconductor package having the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a printed circuit board for a semiconductor package and a semiconductor package having the same, which can prevent defects in post-processing due to warpage.

As the degree of integration of integrated circuit chips increases, more circuits can be placed on chips of the same size, so that integrated circuit chips can send and receive more I / O signals, so semiconductor packages also place more I / O pins within a limited area. There was a need to do it. One way to meet these needs is to develop and use a Ball Grid Array (BGA) package.

The BGA package is manufactured using a printed circuit board capable of high density and high precision in which a larger number of components, that is, a semiconductor chip, can be mounted when mounting a component, and research on this is further increasing. . Therefore, recent package development is required to provide not only the microfabrication technology of the components to be mounted, that is, the semiconductor chip, but also a printed circuit board that enables high-density component mounting.

The printed circuit board is manufactured by forming a wiring made of a conductive material such as copper on a core layer made of a hard insulating material, and refers to a substrate immediately before mounting an electronic component.

Specifically, the printed circuit board may include a core layer made of an insulating material, and first and second portions formed on one side and the other side of the core layer and made of a conductive material such as copper, respectively, and including bond fingers and ball lands. And a solder resist formed to expose bond fingers and ball lands on one side and the other side of the core layer including the wirings.

However, although not shown and described in detail, in the prior art, the thermal expansion coefficients (CTEs) of the core layers, the copper wirings, and the solder resists, which are the constituent materials of the printed circuit board, are different from each other. After fabrication, the interfacial delamination between the constituent materials is caused by the difference in coefficient of thermal expansion during the reliability test process of repeating the high temperature process and the low temperature process.

In addition, since the solder resist has a significantly higher thermal expansion coefficient than the core layer and the copper wiring, when the solder resist is etched after coating in a method such as screen printing or spray coating, the thickness is uneven. This occurs, which causes cracks in the semiconductor chip.

In addition, conventional BGA packages have warpage throughout the substrate as the semiconductor chip adheres and is sealed with an encapsulant on a solder resist having a significantly higher coefficient of thermal expansion than other materials, resulting in poor quality. .

The present invention provides a printed circuit board for a semiconductor package and a semiconductor package having the same, which can prevent the occurrence of interfacial peeling caused by the difference in thermal expansion coefficient between the constituent materials.

The present invention also provides a printed circuit board for a semiconductor package and a semiconductor package having the same, which can prevent cracking of a semiconductor chip by preventing interfacial delamination caused by differences in thermal expansion coefficients between constituent materials.

In addition, the present invention provides a printed circuit board for a semiconductor package and a semiconductor package having the same, which can prevent warpage of a substrate and prevent quality degradation.

In one aspect, a printed circuit board for a semiconductor package according to the present invention, the core layer having one surface and the other surface opposite thereto; A first wiring formed on one surface of the core layer and having a bond finger; A second wiring formed on the other surface of the core layer and having a ball land; And a solder resist formed to expose the bond finger and the ball land on one surface of the core layer including the first wiring and the other surface of the core layer including the second wiring, respectively, wherein the solder resists are parallel to each other. At least two solder resist films including a plurality of stripe-type first patterns and stripe-type second patterns disposed between the first patterns are stacked so that the extending directions of the patterns cross each other. do.

The first pattern is made of a solder resist film.

The second pattern is made of a material having a lower coefficient of thermal expansion than the first pattern, preferably, a fiber material.

In another aspect, a semiconductor package according to the present invention includes a core layer having one surface and the other surface opposite thereto, a first wiring formed on one surface of the core layer and having a bond finger, and formed on the other surface of the core layer. A second wiring having lands and one surface of the core layer including the first wiring and the other surface of the core layer including the second wiring, respectively, formed to expose the bond finger and the ball land and arranged in parallel with each other. A print comprising at least two solder resist films including a plurality of stripe type first patterns and stripe type second patterns disposed between the first patterns, the solder resists being stacked so that the extending directions of the patterns cross each other. Circuit board; And a semiconductor chip attached to the printed circuit board and electrically connected to the printed circuit board.

The first pattern is made of a solder resist film.

The second pattern is made of a material having a lower coefficient of thermal expansion than the first pattern, preferably, a fiber material.

The semiconductor package according to the present invention further includes an encapsulant for sealing an upper surface of the printed circuit board including the semiconductor chip.

In addition, the semiconductor package according to the present invention further includes an external connection terminal attached to the ball land of the printed circuit board.

According to an exemplary embodiment of the present invention, at least two or more solder resist films including a plurality of stripe type first patterns arranged in parallel with each other and a stripe type second pattern disposed between the first patterns may be arranged in an extension direction of the patterns. The solder resist is formed by stacking to cross each other, and the solder resist is applied to realize a printed circuit board.

Accordingly, in the solder resist of the present invention, a fiber material having a relatively low coefficient of thermal expansion is disposed between the solder resist patterns, and also because the solder resist films are laminated so that the extending directions of the patterns cross each other, As the expansion of the solder resist due to the overlap is continuous, it is possible to prevent the expansion of the solder resist in one direction, so that thermal expansion of the solder resist can be alleviated. As a result, the quality of the printed circuit board itself as well as the quality of the semiconductor package Can be improved.

In addition, the present invention is because the solder resist is formed by using a uniform surface of the solder resist film, it is possible to prevent the thickness non-uniformity caused during conventional solder resist coating and etching, as well as cracks in the semiconductor chip accordingly It can prevent occurrence.

In addition, the present invention can prevent warpage of the entire printed circuit board by alleviating thermal expansion due to the high thermal expansion coefficient of the solder resist, and as a result, it is possible to further improve the quality of the semiconductor package.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a printed circuit board for a semiconductor package according to the present invention, and FIGS. 2 to 4 are plan views illustrating solder resists in a printed circuit board for a semiconductor package according to the present invention.

As shown, the printed circuit board 100 for semiconductor packages according to the present invention may include a first wiring 112 and a first wiring 112 formed on each of the core layer 102 and one surface of the core layer 102 and the other surface opposite thereto. Solder resists 120 formed on one surface of the core layer 102 including the second wiring 114 and the first wiring 112 and the other surface of the core layer 102 including the second wiring 14, respectively. It includes.

The core layer 102 constitutes a body of the printed circuit board 100, and is formed of an insulating material such as FR4 (Flame Retardant Type 4) or resin.

The first wiring 112 is formed on one surface of the core layer 102 and has a bond finger 116. The second wiring 114 is formed on the other surface opposite to one surface of the core layer 102 and has a ball land 118.

The solder resist 120 is formed on one surface of the core layer 102 including the first wiring 112 and on the other surface of the core layer 102 including the second wiring 114, respectively. Is formed to expose the bond finger 116 and the ball land 118 of the second wiring 114.

In addition, the solder resist 120, unlike the conventional one made of a bulk type, as shown in FIGS. 2 and 3, the stripe type first patterns 122a arranged in parallel with each other. And the solder resist films 120a and 120b including the stripe type second pattern 122b disposed between the first patterns 122a and the first and second patterns 122a and 122b. It consists of the laminated structure A laminated | stacked so that the extending direction may mutually cross. In this case, the solder resist films 120a and 120b are laminated at least two or more sheets so as to obtain a desired thickness of the solder resist 120. Similarly, the solder resist films 120a and 120b may be stacked in the first and second layers. The extension directions of the second patterns 122a and 122b are continuously crossed.

The stripe-type first patterns 122a may be formed by thinly cutting a solder resist sheet having a uniform surface. The stripe-type second pattern 122b is preferably made of a material having a coefficient of thermal expansion relatively lower than that of the solder resist material. For example, the stripe-type second pattern 122b is formed of a fiber material. The second pattern 122b is adhered between the first patterns 122b arranged in parallel with each other in a stripe type, and serves as a stress mitigator in one solder resist film 120a or 120b.

As such, the solder resist films 120a and 120b including the first patterns 122a and the second patterns 122b may be stacked such that the extending directions of the respective patterns 122a and 122b cross each other. In addition, each of the solder resist films 120a and 120b includes a second pattern 122b made of a fiber material as a stress relieving agent, and as shown in FIG. 4, expansion of the solder resist due to temperature change overlaps. As a result, the phenomenon in which the expansion of the solder resist is increased in one direction is prevented. As a result, thermal expansion of the solder resist 120 according to the present invention is remarkably alleviated.

Therefore, the printed circuit board according to the present invention has a structure in which the solder resist is formed as described above, that is, the solder resist films including the stress relieving agent are laminated with the extension directions of the patterns crossing each other. Due to the difference in the coefficient of thermal expansion between the components it can effectively prevent the interface peeling.

In addition, the printed circuit board according to the present invention can mitigate thermal expansion due to the high thermal expansion coefficient of the solder resist, thereby preventing warpage of the substrate.

In addition, since the printed circuit board according to the present invention constitutes a solder resist using a solder resist film having a uniform surface, it is possible to prevent thickness non-uniformity generated during the application and etching of the solder resist, and thus, in a semiconductor chip Cracks can be prevented.

Therefore, when manufacturing a semiconductor package by applying the printed circuit board according to the present invention as described above, it is possible to improve the quality of the manufactured semiconductor package.

Although not shown, the printed circuit board for a semiconductor package according to the present invention described above includes a conductive pattern, an insulating layer, and a via pattern between each of the first wiring and one surface of the core layer and between the second wiring and the other surface of the core layer. This can be formed.

Here, the insulating layer is interposed between the first wiring and the conductive pattern and between the second wiring and the conductive pattern to serve to electrically insulate the components, and the via pattern is formed in the insulating layer to form the first layer. The wiring and the conductive pattern and the second wiring and the conductive pattern are electrically connected to each other.

5 is a cross-sectional view illustrating a semiconductor package configured by applying the above-described printed circuit board according to the present invention.

As illustrated, the semiconductor package 500 of the present invention includes a printed circuit board 510, a semiconductor chip 530 attached on an upper surface of the printed circuit board 510, and the printed circuit board 510. A metal wire 540 which electrically connects the bond finger 516 of the semiconductor chip and the bonding pad 532 of the semiconductor chip 530, and a printed circuit board 510 including the semiconductor chip 530 and the metal wire 540. The encapsulant 550 for sealing the upper surface of the (), and the external connection terminal 560 attached to the ball land 518 on the lower surface of the printed circuit board 510.

Here, the printed circuit board 510 may be understood as having the same configuration as that of the printed circuit board according to the present invention described above. That is, the printed circuit board 510 of the semiconductor package 500 according to the present invention includes a core layer 502 and first wirings 512 and second formed on one surface and the other surface of the core layer 502, respectively. The wiring 514 and one surface of the core layer 502 including the first wiring 512 and the other surface of the core layer 502 including the second wiring 514 are respectively formed on the wiring 514. A solder resist 520 is formed to expose the bond finger 516 and the ball land 518 of the second wiring 514.

As described above, the solder resist 520 may include the first solder resist films including the stripe type first patterns arranged in parallel with each other and the stripe type second pattern disposed between the first patterns. And at least two or more sheets are laminated so that the extending directions of the second patterns cross each other.

The semiconductor chip 530 includes a bonding pad 532 disposed on an upper surface of the semiconductor chip 530, and is attached to the upper surface of the printed circuit board 510 in a face-up type through an adhesive 534. do.

The encapsulant 550 is made of, for example, an epoxy molding compound (EMC), and serves to protect the semiconductor chip 530 from external influences. The external connection terminal 560 is preferably made of solder balls. In addition to the solder balls, other types can also be used.

In the semiconductor package according to the present invention, since thermal expansion of the solder resist in the printed circuit board is structurally reduced, interfacial separation between components in the printed circuit board is suppressed, and cracks in the semiconductor chip are also prevented. Because of the improved quality.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a cross-sectional view showing a printed circuit board for a semiconductor package according to the present invention.

2 to 4 are plan views illustrating a solder resist in a printed circuit board for a semiconductor package according to the present invention.

5 is a cross-sectional view illustrating a semiconductor package according to the present invention.

Claims (10)

A core layer having one surface and the other surface opposite thereto; A first wiring formed on one surface of the core layer and having a bond finger; A second wiring formed on the other surface of the core layer and having a ball land; And A solder resist formed to expose the bond finger and the ball land on one surface of the core layer including the first wiring and the other surface of the core layer including the second wiring; Including; The solder resist may include at least two solder resist films including a plurality of stripe type first patterns arranged in parallel to each other and a stripe type second pattern disposed between the first patterns so that extension directions of the patterns cross each other. Printed circuit board for a semiconductor package, characterized in that laminated. The method of claim 1, The first pattern is a printed circuit board for a semiconductor package, characterized in that consisting of a solder resist film. The method of claim 1, The second pattern is a printed circuit board for a semiconductor package, characterized in that made of a material having a lower coefficient of thermal expansion than the first pattern. The method of claim 3, wherein The second pattern is a printed circuit board for a semiconductor package, characterized in that the fiber (Fiber) material. A core layer having one surface and the other surface opposite thereto, a first wiring formed on one surface of the core layer and having a bond finger, a second wiring formed on the other surface of the core layer and having ball lands, and the first wiring A plurality of stripe type first patterns and the first pattern formed on the other surface of the core layer including the second layer and the other surface of the core layer including the second wiring, respectively, and arranged in parallel with each other to expose the bond fingers and the ball lands. A printed circuit board including at least two solder resist films including a stripe type second pattern disposed between the plurality of solder resist films stacked in such a manner that the extending directions of the patterns cross each other; And A semiconductor chip attached to the printed circuit board and electrically connected to the printed circuit board; A semiconductor package comprising a. The method of claim 5, The first pattern is a semiconductor package, characterized in that consisting of a solder resist film. The method of claim 5, The second pattern is a semiconductor package, characterized in that made of a material having a lower coefficient of thermal expansion than the first pattern. The method of claim 7, wherein The second pattern is a semiconductor package, characterized in that made of a fiber (Fiber) material. The method of claim 5, And an encapsulant for sealing an upper surface of the printed circuit board including the semiconductor chip. The method of claim 5, The semiconductor package further comprises an external connection terminal attached to the ball land of the printed circuit board.
KR1020090065840A 2009-07-20 2009-07-20 Printed circuit board for semiconductor package and semiconductor package having the same KR20110008476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090065840A KR20110008476A (en) 2009-07-20 2009-07-20 Printed circuit board for semiconductor package and semiconductor package having the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090065840A KR20110008476A (en) 2009-07-20 2009-07-20 Printed circuit board for semiconductor package and semiconductor package having the same

Publications (1)

Publication Number Publication Date
KR20110008476A true KR20110008476A (en) 2011-01-27

Family

ID=43614469

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090065840A KR20110008476A (en) 2009-07-20 2009-07-20 Printed circuit board for semiconductor package and semiconductor package having the same

Country Status (1)

Country Link
KR (1) KR20110008476A (en)

Similar Documents

Publication Publication Date Title
KR101067109B1 (en) A printed circuit board comprising embeded electronic component within and a method for manufacturing
TWI421996B (en) Electrostatic discharge protection structures
US7754538B2 (en) Packaging substrate structure with electronic components embedded therein and method for manufacturing the same
KR100851072B1 (en) Electronic package and manufacturing method thereof
US8466565B2 (en) Substrate and semiconductor device
TWI512926B (en) Package on package structure and method for manufacturing same
JP2008085089A (en) Resin wiring board and semiconductor device
JP2007165888A (en) Printed-circuit substrate in which electron devices are built, and its manufacturing method
KR101481571B1 (en) Semiconductor Package apparatus and its manufacturing method
US20080145975A1 (en) Method for fabricating circuit board structure with embedded semiconductor chip
JP2005150748A (en) Semiconductor chip package having decoupling capacitor and method for manufacturing same
KR20100009941A (en) Semiconductor package having stepped molding compound with conductive via, method for formation of the same and stacked semiconductor package using the same
WO2007114106A1 (en) Semiconductor device, layered type semiconductor device using the same, base substrate, and semiconductor device manufacturing method
CN111524863A (en) Semiconductor device and method for manufacturing the same
US8022513B2 (en) Packaging substrate structure with electronic components embedded in a cavity of a metal block and method for fabricating the same
KR20140143902A (en) Semiconductor package and method of manufacturing the semiconductor package
US20130075144A1 (en) Package substrate with mesh pattern and method for manufacturing the same
US7626126B2 (en) Multilayer semiconductor device
KR100608610B1 (en) PCB, manufacturing method thereof and semiconductor package using the same
CN109427725B (en) Interposer substrate and method of manufacturing the same
JP4324732B2 (en) Manufacturing method of semiconductor device
KR20110008476A (en) Printed circuit board for semiconductor package and semiconductor package having the same
KR101099579B1 (en) Stack Chip Package
KR20100043592A (en) Multi-layers printed circuit board comprising stack-via posts
JP2007109933A (en) Printed wiring board and mounting method of semiconductor using it

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination