KR20110002284A - Semiconductor memory device and its driving method - Google Patents
Semiconductor memory device and its driving method Download PDFInfo
- Publication number
- KR20110002284A KR20110002284A KR1020090059794A KR20090059794A KR20110002284A KR 20110002284 A KR20110002284 A KR 20110002284A KR 1020090059794 A KR1020090059794 A KR 1020090059794A KR 20090059794 A KR20090059794 A KR 20090059794A KR 20110002284 A KR20110002284 A KR 20110002284A
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- negative
- word line
- internal
- line voltage
- Prior art date
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
Abstract
Description
The present invention relates to a semiconductor design technique, and to a technique for generating an internal voltage.
In general, semiconductor devices and semiconductor memory devices are provided with an external power source to generate internal voltages of various voltage levels, and operate internal circuits using the internal voltages.
1 is a block diagram of a semiconductor memory device of the prior art.
Referring to FIG. 1, a semiconductor memory device includes a
The
On the other hand, since the negative word line voltage VINT2 is consumed much to deactivate the memory cell transistor during the precharge operation period, the negative word line voltage VINT2 may increase momentarily during the initial period of the precharge operation. . When the negative word line voltage VINT2 rises, the leakage current of the memory cell transistor increases, thereby deteriorating the refresh characteristics and the data sensing characteristics of the semiconductor memory device.
SUMMARY OF THE INVENTION The present invention has been proposed to solve the above conventional problems, and an object thereof is to provide a semiconductor memory device capable of generating a stable internal voltage.
According to an aspect of the present invention for achieving the above technical problem, by receiving an internal negative voltage as a driving power supply to generate a negative word line voltage having a higher target voltage level than the internal negative voltage to provide a negative word line voltage stage A negative word line voltage generator for generating the negative word line voltage; And an over-driving unit for providing the internal negative voltage to the negative word line voltage terminal during an initial period of a precharge operation.
Further, according to another aspect of the invention, the step of providing a negative voltage of a voltage level lower than the negative word line voltage to the negative word line voltage stage during the initial period of the precharge operation; And providing the negative word line voltage to the negative word line voltage terminal after the initial period of the precharge operation.
In the semiconductor memory device to which the present invention is applied, since the negative word line voltage is stably supplied, the leakage current of the memory cell transistor can be minimized. Therefore, the refresh characteristics of the semiconductor memory device and the data sensing characteristic during active operation can be improved.
In addition, since no additional voltage driver is required to stabilize the negative word line voltage, current consumption and layout area can be minimized.
DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.
In general, logic signals and binary data values of a circuit are classified into high level (high level) or low level (low level) corresponding to voltage level, and may be expressed as '1' and '0', respectively. . In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, P-channel metal oxide semiconductor (PMOS) and N-channel metal oxide semiconductor (NMOS), which are terms used in the present embodiment, are known to be a kind of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).
2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
Referring to FIG. 2, the semiconductor memory device receives a negative negative voltage VINT1 as a driving power source to generate a negative wordline voltage VINT2 having a target voltage level higher than that of the internal negative voltage VINT1 to generate a negative word line voltage terminal ( A negative word
For reference, as in the present exemplary embodiment, the semiconductor memory device may further include a
The detailed configuration and main operations of the semiconductor memory device configured as described above are as follows.
The
In addition, the negative word
In addition, the
Meanwhile, the negative word line voltage VINT2 supplied through the negative word line voltage terminal VBBW is consumed during the precharge operation period. In the semiconductor memory device according to the present embodiment, the negative word line voltage VINT2 is particularly high. The potential of the negative word line voltage terminal VBBW is provided to the negative word line voltage terminal VBBW by providing an internal negative voltage VINT1 of a voltage level lower than the negative word line voltage VINT2 during the initial period of the precharge operation consumed. Unstable internal operation due to rise can be prevented.
As described above, the semiconductor memory device may include providing an internal negative voltage VINT1 having a lower voltage level than the negative word line voltage VINT2 to the negative word line voltage terminal VBBW during an initial period of a precharge operation. After the initial period of the precharge operation, the negative word line voltage terminal VBBW is driven through providing a negative word line voltage VINT2.
In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
For example, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be illustrated. In addition, the configuration of an active high or an active low for indicating an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.
1 is a block diagram of a semiconductor memory device of the prior art.
2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
* Explanation of symbols for the main parts of the drawings
21: negative voltage generator
23: over-driving part
In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090059794A KR20110002284A (en) | 2009-07-01 | 2009-07-01 | Semiconductor memory device and its driving method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090059794A KR20110002284A (en) | 2009-07-01 | 2009-07-01 | Semiconductor memory device and its driving method |
Publications (1)
Publication Number | Publication Date |
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KR20110002284A true KR20110002284A (en) | 2011-01-07 |
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Family Applications (1)
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KR1020090059794A KR20110002284A (en) | 2009-07-01 | 2009-07-01 | Semiconductor memory device and its driving method |
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KR (1) | KR20110002284A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9019781B2 (en) | 2011-08-05 | 2015-04-28 | SK Hynix Inc. | Internal voltage generation circuit |
-
2009
- 2009-07-01 KR KR1020090059794A patent/KR20110002284A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9019781B2 (en) | 2011-08-05 | 2015-04-28 | SK Hynix Inc. | Internal voltage generation circuit |
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