KR20110002284A - Semiconductor memory device and its driving method - Google Patents

Semiconductor memory device and its driving method Download PDF

Info

Publication number
KR20110002284A
KR20110002284A KR1020090059794A KR20090059794A KR20110002284A KR 20110002284 A KR20110002284 A KR 20110002284A KR 1020090059794 A KR1020090059794 A KR 1020090059794A KR 20090059794 A KR20090059794 A KR 20090059794A KR 20110002284 A KR20110002284 A KR 20110002284A
Authority
KR
South Korea
Prior art keywords
voltage
negative
word line
internal
line voltage
Prior art date
Application number
KR1020090059794A
Other languages
Korean (ko)
Inventor
김철회
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090059794A priority Critical patent/KR20110002284A/en
Publication of KR20110002284A publication Critical patent/KR20110002284A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A semiconductor memory device and a driving method thereof are provided to improve a refresh property and a data detection property by minimizing the leakage current of a memory cell transistor. CONSTITUTION: A negative word line voltage generating part(22) generates a negative word line voltage which has a higher target voltage level than an internal negative voltage and transfers it to a negative word line voltage terminal. An over driving part(23) supplies the internal negative voltage to the negative word line voltage terminal during the initial period of a pre-charge operation. A negative voltage generating part(21) generates the internal negative voltage.

Description

Semiconductor memory device and its driving method {SEMICONDUCTOR MEMORY DEVICE AND ITS DRIVING METHOD}

The present invention relates to a semiconductor design technique, and to a technique for generating an internal voltage.

In general, semiconductor devices and semiconductor memory devices are provided with an external power source to generate internal voltages of various voltage levels, and operate internal circuits using the internal voltages.

1 is a block diagram of a semiconductor memory device of the prior art.

Referring to FIG. 1, a semiconductor memory device includes a negative voltage generator 11 and a negative word line voltage generator 12.

The negative voltage generator 11 performs charge pumping to generate an internal negative voltage VINT1 using the ground voltage VSS, and provide the generated negative voltage VINT1 to the internal voltage terminal VBB. In addition, the negative word line voltage generator 12 receives the internal negative voltage VINT1 as a power source to generate a negative word line voltage VINT2 having a voltage level higher than the internal negative voltage VINT1 to generate a negative word line voltage. Provided to VBBW.

On the other hand, since the negative word line voltage VINT2 is consumed much to deactivate the memory cell transistor during the precharge operation period, the negative word line voltage VINT2 may increase momentarily during the initial period of the precharge operation. . When the negative word line voltage VINT2 rises, the leakage current of the memory cell transistor increases, thereby deteriorating the refresh characteristics and the data sensing characteristics of the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above conventional problems, and an object thereof is to provide a semiconductor memory device capable of generating a stable internal voltage.

According to an aspect of the present invention for achieving the above technical problem, by receiving an internal negative voltage as a driving power supply to generate a negative word line voltage having a higher target voltage level than the internal negative voltage to provide a negative word line voltage stage A negative word line voltage generator for generating the negative word line voltage; And an over-driving unit for providing the internal negative voltage to the negative word line voltage terminal during an initial period of a precharge operation.

Further, according to another aspect of the invention, the step of providing a negative voltage of a voltage level lower than the negative word line voltage to the negative word line voltage stage during the initial period of the precharge operation; And providing the negative word line voltage to the negative word line voltage terminal after the initial period of the precharge operation.

In the semiconductor memory device to which the present invention is applied, since the negative word line voltage is stably supplied, the leakage current of the memory cell transistor can be minimized. Therefore, the refresh characteristics of the semiconductor memory device and the data sensing characteristic during active operation can be improved.

In addition, since no additional voltage driver is required to stabilize the negative word line voltage, current consumption and layout area can be minimized.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

In general, logic signals and binary data values of a circuit are classified into high level (high level) or low level (low level) corresponding to voltage level, and may be expressed as '1' and '0', respectively. . In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, P-channel metal oxide semiconductor (PMOS) and N-channel metal oxide semiconductor (NMOS), which are terms used in the present embodiment, are known to be a kind of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device receives a negative negative voltage VINT1 as a driving power source to generate a negative wordline voltage VINT2 having a target voltage level higher than that of the internal negative voltage VINT1 to generate a negative word line voltage terminal ( A negative word line voltage generator 22 for providing to the VBBW and an over-driving unit 23 for providing the internal negative voltage VINT1 to the negative word line voltage terminal VBBW during the initial period of the precharge operation. Equipped.

For reference, as in the present exemplary embodiment, the semiconductor memory device may further include a negative voltage generator 21 for generating the internal negative voltage VINT1. The negative voltage generator 21 performs charge pumping to generate an internal negative voltage VINT1 as the ground voltage VSS. In general, the internal negative voltage VINT1 is used as the substrate bias voltage of the transistor or the memory cell transistor.

The detailed configuration and main operations of the semiconductor memory device configured as described above are as follows.

The negative voltage generator 21 may include a periodic pulse generator 212 for generating a periodic pulse signal OSC in response to the voltage detection signal V_DET, and charge pumping in response to the periodic pulse signal OSC. Charge detection unit 213 for generating the internal negative voltage VINT1 by the ground voltage VSS, and whether the internal negative voltage VINT1 has reached the desired voltage level to detect the voltage detection signal ( And an internal voltage level detector 211 for outputting V_DET). Therefore, the periodic pulse generator 212 outputs a periodic pulse signal OSC that pulses at a specific period, and the charge pumping unit 213 generates an internal negative voltage VINT1 using the periodic pulse signal OSC. On the other hand, when the internal negative voltage VINT1 rises, the internal voltage level detection unit 211 detects it and controls to generate the periodic pulse signal OSC, so that the internal negative voltage VINT1 maintains a constant voltage level.

In addition, the negative word line voltage generator 22 is configured as a voltage regulator for receiving the internal negative voltage VINT1 and outputting the negative word line voltage VINT2. That is, a voltage regulator method is used to generate a negative word line voltage VINT2 using the internal negative voltage VINT1.

In addition, the overdriving unit 23 controls the control pulse generator 231 for generating the control pulse signal CTRL_PULSE that pulses during the initial period of the precharge operation, and the internal negative voltage in response to the control pulse signal CTRL_PULSE. And a switching unit MN1 for transferring VINT1) to the negative word line voltage terminal VBBW. Herein, the control pulse generator 231 inverts the delay unit 2 for delaying the precharge signal PRE for a predetermined time, and a signal inverting the signals output from the precharge signal PRE and the delay unit 2. And a logic unit (NAND, INV2) for outputting the control pulse signal (CTRL_PULSE). Since the switching unit MN1 is constituted by the NMOS transistor MN1, the NMOS transistor MN1 is turned ON while the control pulse signal CTRL_PULSE is pulsed at a high level by the delay time of the delay unit 2. The negative voltage VINT1 is transferred to the negative word line voltage terminal VBBW.

Meanwhile, the negative word line voltage VINT2 supplied through the negative word line voltage terminal VBBW is consumed during the precharge operation period. In the semiconductor memory device according to the present embodiment, the negative word line voltage VINT2 is particularly high. The potential of the negative word line voltage terminal VBBW is provided to the negative word line voltage terminal VBBW by providing an internal negative voltage VINT1 of a voltage level lower than the negative word line voltage VINT2 during the initial period of the precharge operation consumed. Unstable internal operation due to rise can be prevented.

As described above, the semiconductor memory device may include providing an internal negative voltage VINT1 having a lower voltage level than the negative word line voltage VINT2 to the negative word line voltage terminal VBBW during an initial period of a precharge operation. After the initial period of the precharge operation, the negative word line voltage terminal VBBW is driven through providing a negative word line voltage VINT2.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be illustrated. In addition, the configuration of an active high or an active low for indicating an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a block diagram of a semiconductor memory device of the prior art.

2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: negative voltage generator

23: over-driving part

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (9)

A negative word line voltage generator configured to receive an internal negative voltage as a driving power source and generate a negative word line voltage having a target voltage level higher than that of the internal negative voltage and provide the negative word line voltage to a negative word line voltage terminal; And An over-driving unit for providing the internal negative voltage to the negative word line voltage terminal during an initial period of a precharge operation. A semiconductor memory device having a. The method of claim 1, And a negative voltage generator configured to generate the internal negative voltage. The method of claim 2, The negative voltage generator, And performing internal charge pumping to generate the internal negative voltage using the ground voltage. The method of claim 2, The negative voltage generator, A periodic pulse generator for generating a periodic pulse signal in response to the voltage detection signal; A charge pumping unit configured to generate the internal negative voltage with a ground voltage by performing charge pumping in response to the periodic pulse signal; And And an internal voltage level detector for detecting whether the internal negative voltage reaches a target voltage level and outputting the voltage detection signal. The method of claim 1, The negative word line voltage generator, And a voltage regulator configured to receive the internal negative voltage and output the negative word line voltage. The method of claim 1, The over driving part, A control pulse generator for generating a control pulse signal pulsed during an initial period of the precharge operation; And And a switching unit for transferring the internal negative voltage to the negative word line voltage terminal in response to the control pulse signal. The method of claim 6, The control pulse generator, A delay unit for delaying the precharge signal for a predetermined time; And And a logic unit for outputting the control pulse signal by ANDing the signal obtained by inverting the precharge signal and the signal output from the delay unit. The method of claim 1, And the internal negative voltage is used as a substrate bias voltage of a transistor. Providing a negative voltage at a voltage level lower than the negative word line voltage at the negative word line voltage stage during the initial period of the precharge operation; And Providing the negative word line voltage to the negative word line voltage terminal after the initial period of the precharge operation. Method of driving a semiconductor memory device comprising a.
KR1020090059794A 2009-07-01 2009-07-01 Semiconductor memory device and its driving method KR20110002284A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090059794A KR20110002284A (en) 2009-07-01 2009-07-01 Semiconductor memory device and its driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090059794A KR20110002284A (en) 2009-07-01 2009-07-01 Semiconductor memory device and its driving method

Publications (1)

Publication Number Publication Date
KR20110002284A true KR20110002284A (en) 2011-01-07

Family

ID=43610563

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090059794A KR20110002284A (en) 2009-07-01 2009-07-01 Semiconductor memory device and its driving method

Country Status (1)

Country Link
KR (1) KR20110002284A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9019781B2 (en) 2011-08-05 2015-04-28 SK Hynix Inc. Internal voltage generation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9019781B2 (en) 2011-08-05 2015-04-28 SK Hynix Inc. Internal voltage generation circuit

Similar Documents

Publication Publication Date Title
KR100543659B1 (en) Active driver for generating internal voltage
US20070236278A1 (en) Internal voltage generator for semiconductor integrated circuit capable of compensating for change in voltage level
US7733162B2 (en) Plumping voltage generating circuit
KR100562654B1 (en) Bleq driving circuit and semiconductor memory device using it
KR101092997B1 (en) Device for generating internal negative voltage
KR100631953B1 (en) Memory device
KR100954110B1 (en) Power up signal generator and integrated circuit using the same
US8362827B2 (en) Semiconductor device including transistors that exercise control to reduce standby current
US6903595B2 (en) High voltage transfer circuit
KR100886628B1 (en) Internal voltage generation circuit in semiconductor device
JP3869690B2 (en) Internal voltage level control circuit, semiconductor memory device, and control method thereof
KR101035408B1 (en) Semiconductor device
KR20110002284A (en) Semiconductor memory device and its driving method
US7276959B2 (en) Pumping circuit of semiconductor device
KR100761371B1 (en) Active driver
KR100641913B1 (en) Refersh controlling circuit of semiconductor memory device
KR100799103B1 (en) Semiconductor device
US9019781B2 (en) Internal voltage generation circuit
KR20110047892A (en) Integrated circuit and its driving method
KR100903388B1 (en) Internal voltage control circuit and thereof control method
US7990206B2 (en) Device for supplying temperature dependent negative voltage
KR100889324B1 (en) VCORE release driver
KR20090027378A (en) Internal voltage generating circuit
KR100720221B1 (en) Voltage generator
KR100919811B1 (en) Internal Voltage Generating Circuit

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination