KR20110001717A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
KR20110001717A
KR20110001717A KR1020090059378A KR20090059378A KR20110001717A KR 20110001717 A KR20110001717 A KR 20110001717A KR 1020090059378 A KR1020090059378 A KR 1020090059378A KR 20090059378 A KR20090059378 A KR 20090059378A KR 20110001717 A KR20110001717 A KR 20110001717A
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KR
South Korea
Prior art keywords
region
ion implantation
forming
same
cell
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KR1020090059378A
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Korean (ko)
Inventor
김인구
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주식회사 하이닉스반도체
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Priority to KR1020090059378A priority Critical patent/KR20110001717A/en
Publication of KR20110001717A publication Critical patent/KR20110001717A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor device forming method is provided to reduce the time and cost required for implementing the ion injection process as the additional process per area by implementing the ion injection processes in cell area and peri area at the same time. CONSTITUTION: A semiconductor substrate(10) includes a cell area and a peri area. A photosensitive pattern exposes a part of the peri area and the cell area on the semiconductor substrate. The ion injection energy is 250keV to 350keV. A second ion injection area is formed on the first ion injection area using the photosensitive pattern as the mask.

Description

Method for forming semiconductor device

The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device including an ion implantation step.

In general, in the case of a high voltage product, the input / output circuit of the product is a high voltage device and the internal logic circuit is a low voltage device. In most cases, high voltage and low voltage devices must set breakdown voltage and threshold voltage of the device as important characteristics of their own devices. Since ion implantation for adjusting the threshold voltage must be performed separately at the site where each device is to be formed, an independent photo mask is necessary. In particular, in the case of a semiconductor device comprising a plurality of transistors required for the operation of various circuits, more specifically a cell transistor connected to a storage electrode for storing data, and a ferry transistor provided in a peripheral circuit for reading and writing data. Multiple mask processes and multiple mask processes are required for implantation.

On the other hand, the triple-well structure is a well (WELL) of the MOSFET (Metal Oxide Semiconductor FET; hereinafter referred to as "MOS") included in the cell region and the peripheral circuit of the main circuit, the well included in the cell region, for example It is a structure to distinguish wells of the same type included in and peripheral circuits. In general, a semiconductor device having a triple-well structure includes NMOS (ferry-NMOS) and PMOS (ferry-PMOS), and in this NMOS or PMOS, another MOS (cell-MOS) for a cell is included. have.

In the triple-well semiconductor device, an ion implantation that adjusts the threshold voltages of the cell-NMOS and the ferry-NMOS is performed after an N-channel threshold voltage mask process to adjust an operating voltage (Vt; Threshold Voltage). To adjust the concentration of each threshold voltage. After the P-channel threshold voltage mask process, in order to adjust the threshold voltages of the Peri-PMOS and the cell-NMOS, two or more steps of the photoresist and ion implantation process are performed. In the semiconductor device by such a process, the threshold voltages of Peri-PMOS, Peri-NMOS, and Cell-NMOS have an organic relationship with each other.

This triple-well semiconductor device can vary the well concentration of the P-well of the cell region and the P-well of the peripheral circuit except this cell, and thus, the independent MOSFETs having different substrates and different operating characteristics for device fabrication can be fabricated. There is a characteristic.

However, the conventional triple-well structured semiconductor device described above has many problems in device fabrication. That is, in order to independently form the electrical characteristics of each MOSFET, there is a problem in that a separate threshold voltage concentration control process is required to obtain a well region and an operating voltage corresponding to each MOSFET characteristic. In addition, the manufacturing process of the conventional triple-well semiconductor device has a problem that the process for the concentration control of Peri-PMOS, Peri-NMOS, cell-NMOS affects each other. For this reason, the ion implantation for controlling the concentration of the Peri-PMOS affects the cell-NMOS threshold voltage concentration. Therefore, the operating voltage of each MOSFET cannot be adjusted independently. In order to solve this problem, a separate photoresist film and a mask process need to be added.

The present invention is to solve the problem that the cost and time of the semiconductor device is increased by the mask process and ion implantation process to implement a variety of transistors such as Peri-PMOS, Peri-NMOS, cell-NMOS.

The method of forming a semiconductor device of the present invention comprises forming a first ion implantation region in the semiconductor substrate using a photoresist pattern that exposes a portion of a cell region and a ferry region on a semiconductor substrate, and forming the first ion implantation region in the semiconductor substrate using the photoresist pattern as a mask. Forming a second ion implantation region on the first ion implantation region, forming a third ion implantation region on the second ion implantation region using the photoresist pattern as a mask, and forming a polysilicon layer on the semiconductor substrate It characterized in that it comprises a step of heat treatment after.

In this case, the forming of the first ion implantation region is characterized in that the ion implantation in the cell region and the ferry region at the same element, the same ion implantation energy, the same implantation angle.

The ion implantation energy is 250 keV to 350 keV.

The forming of the second ion implantation region may include ion implantation into the cell region and the ferry region at the same element, at the same ion implantation energy, and at the same implantation angle.

The forming of the third ion implantation region may include ion implantation into the cell region and the ferry region at the same element, at the same ion implantation energy, and at the same implantation angle.

In the forming of the third ion implantation region, the third ion may have the same height as a portion where the channel of the cell region is formed, and coincide with the point where the boundary surface of the depletion layer by the junction of the ferry region is located. Forming an injection region characterized in that it comprises a.

The heat treatment after forming the polysilicon layer on the semiconductor substrate may include forming a source / drain in the cell region and the ferry region.

The present invention allows the ion implantation process of the semiconductor device to be simultaneously performed in the cell region and the ferry region, thereby providing an effect of reducing the time and cost required to perform the ion implantation process as a separate process for each region.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

In the present invention, in order to simultaneously perform an ion implantation process in the cell region and the ferry region, by omitting an ion implantation process for defining a source / drain and replacing the polysilicon layer with a subsequent heat treatment, each region is conventionally used. In order to control the concentration separately, the processes performed for each region may be performed at the same time.

1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

As shown in FIG. 1A, after the photoresist film is applied to the semiconductor substrate 10 including the cell region and the ferry region ii, an exposure and development process is performed to form the photoresist pattern 12. Next, the first ion implantation region 14 is formed in the semiconductor substrate 10 using the photoresist pattern 12 as a mask. In this case, the first ion implantation region 14 is preferably a p well in which a p-type dopant is ion implanted with a high energy ion implanter. In this case, the first ion implantation region 14 is preferably formed of p-well in order to make the operation of the transistor faster by using a property in which electron mobility is faster than hole mobility in silicon used as a semiconductor substrate. . However, the present invention is not limited thereto and may be changed to n wells. In addition, it is preferable that the process for forming the first ion implantation region 14 is made under the same conditions in the cell region and the ferry region ii. That is, it is preferable that the elements to be implanted, the energy to be implanted and the angle to which the ions are implanted are the same. At this time, the injected energy is preferably 250keV to 350keV. Although the first ion implantation regions 14 of the cell region and ferry region ii are conventionally formed by being performed simultaneously instead of being separately performed for separate concentration control for each region, the characteristics of the semiconductor device It doesn't matter so much, so it doesn't matter.

Next, it is preferable to form the second ion implantation region 16 on the first ion implantation region 14 using the photosensitive film pattern 12 as a mask. In this case, the second ion implantation region 16 preferably serves to prevent a short circuit between the active regions (not shown). In this case, when the first ion implantation region 14 is ion-implanted with the p-type dopant, the second ion implantation region 16 is also ion-implanted with the p-type dopant, and the first ion implantation region 14 is ion-implanted with the n-type dopant. In this case, the first ion implantation region 16 is also preferably implanted with an n-type dopant. The process for forming the second ion implantation region is preferably made under the same conditions in the cell region and the ferry region (ii). That is, it is preferable that the same element, the same energy, and the angle at which the ions are implanted are the same. Likewise, in the same manner as the first ion implantation region 14, the second ion implantation region 16 of the cell region VII and the ferry region ii is conventionally performed separately for separate concentration control for each region. Even if the process is performed at the same time instead of the process, the characteristics of the semiconductor device are not significantly affected, so it is not a problem.

Then, it is preferable to form the third ion implantation region 18 on the second ion implantation region 16 using the photosensitive film pattern 12 as a mask. In this case, the third ion implantation region 18 preferably serves to adjust the threshold voltage. The process for forming the second ion implantation region is preferably made under the same conditions in the cell region and the ferry region (ii). That is, it is preferable that the same element, the same energy, and the angle at which the ions are implanted are the same. Here, the third ion implantation region 18 is formed to have the same height as the portion where the channel is formed in the cell region, and the point where the boundary surface of the depletion layer due to junction is located in the ferry region ii. It is desirable to match with.

If the third ion implantation region 18 is not formed to have the same height as the portion in which the channel is formed in the cell region, the leakage current may occur in the channel region or the time for storing data normally may be reduced. If the third ion implantation region 18 is not formed at the same depth as the depth at which the junction is formed in the ferry region ii, a short circuit between the source and the drain may occur and the transistor may not function. Problems will arise. Therefore, the third ion implantation region 18 is preferably formed at the position described above. In order to control the channel region of the third ion implantation region 18, it is preferable to form a recess gate or a fin structured gate. As described above, when the third ion implantation region 18 is positioned, even if the cell region and the ferry region are formed by being performed at the same time instead of a separate process, the characteristics of the semiconductor device are not significantly affected.

As shown in FIG. 1B, after the polysilicon 22 is formed on the semiconductor substrate 10, a heat treatment process is performed to form the source / drain 24. At this time, the polysilicon 22 is preferably doped with a Group 5 element to form an NMOS when the first ion implantation region is a p well. In addition, when the first ion implantation region is n well, it is preferable to be doped with a group 3 element to form a PMOS. Conventionally, the ion implantation process is performed separately in the cell region (i) and the ferry region (ii) to form a source / drain, but in the present invention, the cell region (i.e. And ferry area (ii) are performed simultaneously.

As described above, by simultaneously performing the ion implantation process in the cell region and ferry region, the number of masks required for the separate ion implantation process performed for each region can be reduced to reduce the cost and time required to form the semiconductor device.

1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Claims (7)

Forming a first ion implantation region in the semiconductor substrate using a photoresist pattern that exposes a portion of the cell region and the ferry region on the semiconductor substrate; Forming a second ion implantation region on the first ion implantation region using the photoresist pattern as a mask; Forming a third ion implantation region on the second ion implantation region using the photoresist pattern as a mask; And Forming a polysilicon layer on the semiconductor substrate, and then heat-treating the semiconductor device. The method according to claim 1, Forming the first ion implantation region is And implanting the same element, the same ion implantation energy, and the same implantation angle into the cell region and the ferry region. The method according to claim 2, The ion implantation energy is a method of forming a semiconductor device, characterized in that 250keV to 350keV. The method according to claim 1, Forming the second ion implantation region is And implanting the same element, the same ion implantation energy, and the same implantation angle into the cell region and the ferry region. The method according to claim 1, Forming the third ion implantation region is And implanting the same element, the same ion implantation energy, and the same implantation angle into the cell region and the ferry region. The method according to claim 1, Forming the third ion implantation region is And forming the third ion implantation region to have the same height as the portion where the channel of the cell region is formed and to coincide with the point where the boundary surface of the depletion layer by the junction of the ferry region is located. Method of forming a semiconductor device. The method according to claim 1, After forming the polysilicon layer on the semiconductor substrate and heat treatment Forming a source / drain in the cell region and the ferry region.
KR1020090059378A 2009-06-30 2009-06-30 Method for forming semiconductor device KR20110001717A (en)

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KR1020090059378A KR20110001717A (en) 2009-06-30 2009-06-30 Method for forming semiconductor device

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KR1020090059378A KR20110001717A (en) 2009-06-30 2009-06-30 Method for forming semiconductor device

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KR20110001717A true KR20110001717A (en) 2011-01-06

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