KR20110001572A - Nonvolatile memory device and operating method thereof - Google Patents

Nonvolatile memory device and operating method thereof Download PDF

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Publication number
KR20110001572A
KR20110001572A KR1020090059148A KR20090059148A KR20110001572A KR 20110001572 A KR20110001572 A KR 20110001572A KR 1020090059148 A KR1020090059148 A KR 1020090059148A KR 20090059148 A KR20090059148 A KR 20090059148A KR 20110001572 A KR20110001572 A KR 20110001572A
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South Korea
Prior art keywords
memory cell
voltage
dummy
word line
dummy memory
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KR1020090059148A
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Korean (ko)
Inventor
전유남
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090059148A priority Critical patent/KR20110001572A/en
Publication of KR20110001572A publication Critical patent/KR20110001572A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

PURPOSE: A nonvolatile memory device and an operating method thereof are provided to improve a threshold voltage distribution property by narrowly controlling the threshold voltage distribution of memory cells connected to a thirty second word line. CONSTITUTION: A source selection transistor, a first dummy memory cell, a plurality of memory cells, a second dummy memory cell and a drain selection transistor are serially connected between a common source line and a bit line. The program of the memory cell connected to the second dummy memory cell is executed. A first lead voltage is applied to the first dummy memory cell. A second lead voltage higher than the first lead voltage is applied to a second dummy memory cell(S616). The pass/fail of the program operation is verified(S617).

Description

 Nonvolatile memory device and its operation method

The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device having a dummy word line and a method of operating the same.

1 is a diagram illustrating a memory cell array of a general NAND flash memory device.

Referring to FIG. 1, a memory cell array includes a plurality of memory cell blocks, and a memory cell block includes a plurality of strings. The string has a structure in which a selection transistor and a plurality of memory cells are connected in series. One string is connected in series between the drain select transistor DST connected to the bit line BL0, the source select transistor SST connected to the common source line CSL, and the select transistors DST and SST. It includes a plurality of memory cells (MC0 to MC31). Depending on the design of the circuit, 16, 32, or 64 memory cells may be connected in series between the select transistors DST and SST. Here, the case where 32 memory cells are connected in series will be described as an example. do. The drain select line DSL connects the gate electrodes of the drain select transistors DST, and the source select line SSL connects the gate electrode of the source select transistor SST, and the word lines WL0 to WL31. ) Connects the gate electrodes of the memory cells MC0 to MC31.

Data of 0 or 1 in the flash memory is determined according to threshold voltages of the memory cells sensed by the read operation or the verify operation. For example, a precharge voltage is applied to the bit line and a ground voltage is applied to the common source line CSL. A read voltage is applied to the selected word line, and a voltage above the power supply voltage is applied to the unselected word lines, for example, a pass voltage for turning on unselected memory cells. In addition, a drain voltage Vcc is applied to the drain select line DSL and the source select line SSL to turn on the drain select transistors DST and the source select transistors SST. Subsequently, the precharge voltage applied to the bit lines is sensed, and when the voltage of the bit line is lower than the precharge voltage, it is divided into an erase state ('1' state). ).

FIG. 2 is a diagram illustrating a wide distribution of threshold voltages of memory cells due to memory cells connected to a first word line and memory cells connected to a last word line among a plurality of memory cells in a general NAND flash memory device. .

Referring to FIG. 2, the threshold voltages of the memory cells connected to the last word line WL31 are lowest. This is because, unlike other word lines, relatively little interference occurs in the word line direction. In most NAND flash memories, a program operation is sequentially performed in a direction from a first word line WL0 adjacent to a source select line SSL to a 32nd word line WL31 adjacent to a drain select line DSL. For this reason, when the memory cell connected to the first word line WL0 to the 31st word line WL30 is programmed after the memory cell connected to the next word line, the floating gate of the memory cell connected to the next word line is programmed. The threshold voltage may change due to the floating gate potential change. However, since the program operation is last performed on the memory cells connected to the 32nd word line WL31, the influence of such interference phenomenon is small.

It can be seen that the threshold voltages of the memory cells connected to the first word line WL0 are distributed the highest, which means that the memory cells connected to the first word line WL0 are distorted than the memory cells connected to other word lines. Because it is vulnerable to. For example, since 0 V is applied to the gate of the source select transistor during a program operation, an electron-hole pair is formed by a gate induced drain leakage (GIDL) in a region adjacent to the channel and the gate, and the double electrons are formed. They quickly move to a high potential channel region and are injected into a floating gate of a programmed cell by a program voltage applied to the first word line WL0. If this disturb occurs in the programmed memory cell, this causes an increase in the threshold voltage. This phenomenon occurs in the thirty-second word line WL31, but since the 0 V is applied to the source select line SSL and the power supply voltage Vcc is applied to the drain select line DSL during the program operation, the thirty-second word line WL31 is applied. ) Is a minor occurrence.

An object of the present invention is to provide a nonvolatile memory device capable of improving a threshold voltage distribution characteristic due to an asymmetry of interference of a memory cell adjacent to a drain select transistor, and a method of operating the same.

In order to achieve the above technical problem the nonvolatile memory device according to the present invention,

A memory cell array including a plurality of strings having a source select transistor, a first dummy memory cell, a plurality of memory cells, a second dummy memory cell, and a drain select transistor connected in series between a common source line and a bit line; And

A voltage configured to generate a second read voltage applied to the second dummy memory cell higher than a first read voltage applied to the first dummy memory cell during a program verify operation of the memory cell connected to the second dummy memory cell; It includes a supply.

In this embodiment, the voltage supply unit may be configured to further generate a verify voltage to be applied to the selected memory cell during the program verify operation, and apply the first read voltage to the unselected memory cell.

The method may further include a row decoder configured to apply a voltage supplied from the voltage supply unit to a word line to which a corresponding memory cell is connected.

In this embodiment, the voltage supply unit applies a read voltage having the same level to the first dummy memory cell and the second dummy memory cell during a program verify operation of a memory cell not connected to the second dummy memory cell. can do.

Method of operation of a nonvolatile memory device according to the present invention,

A memory cell array is provided wherein a source select transistor, a first dummy memory cell, a plurality of memory cells, a second dummy memory cell, and a drain select transistor include a plurality of strings connected in series between a common source line and a bit line. ;

Performing a program operation of a memory cell connected to the second dummy memory cell; And

And applying a first read voltage to the first dummy memory cell and applying a second read voltage higher than the first read voltage to the second dummy memory cell to perform a program verify operation.

In the present exemplary embodiment, a verification voltage may be applied to a selected memory cell and a first read voltage may be applied to a non-selected memory cell for the program verify operation.

In this embodiment, during a program verify operation of a memory cell not connected to the second dummy memory cell, a read voltage having the same level may be applied to the first dummy memory cell and the second dummy memory cell.

In this embodiment, the first read voltage may be a voltage for turning on the unselected memory cells.

In this embodiment, the memory cells in the memory cell array may be multi-level cells or single-level cells.

According to the nonvolatile memory device according to the present invention, the threshold voltage distribution of the memory cells connected to the 32nd word line WL31 is widened due to the difference in the interference effect, thereby eliminating the threshold voltage distribution without a specific external device. It can help improve and increase yield.

In addition, when the verification operation is performed after programming the memory cell connected to the 32nd word line WL31, unlike applying the first read voltage Vread1 to the remaining word lines WL0 to WL30 and the first dummy word line. Since the second read voltage Vread2 higher than the first read voltage Vread1 is applied to the second dummy word line adjacent to the drain select transistor DST, more current flows than when the first read voltage Vread1 is applied. Thus, by compensating for determining the threshold voltage high, the result can be programmed to a threshold voltage higher than the desired threshold voltage level.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a diagram illustrating a memory cell array of a NAND flash memory device including dummy memory cells.

Referring to FIG. 3, unlike the memory cell array illustrated in FIG. 1, a dummy memory cell DMC0 is connected between the source select transistor SST and the memory cell MC0, and the drain select transistor DST is connected to the source select transistor SST and the memory cell MC0. The dummy memory cell DMC1 is connected between the memory cells MC31. The dummy word lines DWL0 and DWL1 are connected to gates of the dummy memory cells DMC0 and DMC1, respectively. The dummy memory cells DMC0 and DMC1 may have the same structure as the memory cells MC0 to MC31. However, unlike the memory cells, the dummy memory cells DMCO and DMC1 do not perform a program operation and a read operation. That is, dummy memory cells are not used as data storage elements.

4 is a diagram illustrating a change in threshold voltage distribution in a NAND flash memory device having dummy word lines inserted therein.

In order to solve the threshold voltage distribution problem due to the edge word line in NAND flash memory, when 32 word lines are used, as shown in FIG. 3, 32 word lines serving as flash memory are shown. In addition, a method of inserting a word line serving as a dummy has been introduced. That is, a disturb phenomenon occurs in a memory cell connected to the first word line WL0 and the 32nd word line WL31 by adding a dummy word line between the existing selection transistors DST and SST and the edge word line. We will try to solve the threshold voltage distribution problem.

However, as shown in FIG. 4, even when the dummy word line is inserted, the memory cell connected to the dummy word line, that is, the dummy memory cell does not program, and thus interference occurs in the memory cell connected to the thirty-second word line WL31. The problem of threshold voltage distribution due to asymmetry cannot be solved.

5 is a block diagram illustrating a nonvolatile memory device according to the present invention.

Referring to FIG. 5, a nonvolatile memory device includes a memory cell array 510, a voltage supply unit 520, a row decoder 530, a controller 540, and a page buffer 550.

The memory cell array 510 includes a source select transistor SST, a first dummy memory cell DMC0, a plurality of memory cells MC0-MC31, a second dummy memory cell DMC1, and a drain select transistor DST. Contains a string connected in series. Each bit line BL1 to BLn serving as a drain is connected to the drain select transistor DST, and the common source line CSL serving as a source is connected to the source select transistor SST. The first dummy memory cell DMC0 is connected in series with the source select transistor SST, and the second dummy memory cell DMC1 is connected in series with the drain select transistor DST. The number of memory cells connected in series between the first dummy memory cell DMC0 and the second dummy memory cell DMC1 is 16, 32, and 64 in consideration of the device and the density. In FIG. 5, 32 memory cells are configured as one string, and there are N such strings. Memory cells (eg, MC1) are controlled by one word line WL1.

The voltage supply unit 520 generates and supplies a program voltage Vpgm, a program verify voltage Vverify, a first read voltage Vread1, and a second read voltage Vread2 according to a program operation or a verify operation.

When the program operation of the 32nd memory cell MC31 is performed, the voltage supply unit 520 applies the program voltage Vpgm to the 32nd word line WL31. Thereafter, the verify voltage Vverify is applied to the 32nd word line WL31 for the program verify operation, and the first read voltage Vread1 is applied to the remaining word lines WL0 to WL30 and the first dummy word line DWL0. The second read voltage Vread2 is applied to the second dummy word line DWL1. In order to achieve the effect of the present invention, the second read voltage Vread2 is higher than the first read voltage Vread1.

In addition, when the program operation of the memory cells MC0-MC30 other than the 32nd memory cell MC31 is performed, the voltage supply unit 520 applies the first dummy word line DWL0 to the first dummy word line DWL0 during the program verify operation. The read voltage Vread1 and the second read voltage Vread2 applied to the second dummy word line DWL1 are generated and supplied at the same level.

The row decoder 530 transfers the voltages generated by the voltage supply unit 520 to the corresponding word line according to the address signal transmitted from the controller 540.

The page buffer 550 controls read, program, erase, and verify operations thereof in the nonvolatile memory device. The page buffer 550 temporarily stores data to be input into the memory cell or stores a program verification result.

In addition, the controller 540 receives the command signal CMD and the address signal ADD to control the voltage supply unit 520, the row decoder 530, and the page buffer 550.

Hereinafter, a method of operating the nonvolatile memory device of the present invention including the above configuration will be described.

6 is a flowchart illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, first, a program operation is performed to store data in memory cells connected to a corresponding word line WLn by applying a program voltage to an Nth target word line (eg, WLn) among 32 word lines. (S611).

Next, it is judged whether or not the Nth program target word line WLn is the 32nd word line WL31 corresponding to the last word line (S612). At this time, when the N-th program target word line WLn is not the 32nd word line WL31, a read voltage having the same level as that of the first dummy word line DWL0 is applied to the second dummy word line DWL1 (S613). The pass / fail of the program operation is verified (S614).

If the program fails in step S614, the process returns to step S611 immediately, and a program voltage of which the voltage is increased (using the ISPP method) is first applied to the Nth word line (for example, WLn), thereby applying the Nth word line (WLn). The data is programmed again into the memory cells. Thereafter, a read voltage having the same level as that of the first dummy word line DWL0 is applied to the second dummy word line DWL1 (S613) to verify the pass / fail of the program operation (S614). This operation is repeatedly performed while raising the program voltage until the program passes.

If it is a program pass in step S614, an address for selecting a word line is increased by one (S615), and the flow returns to step S611 to apply a program voltage to the next program word line (for example, WL n +1 ), thereby providing a word line (WL n +). Program data to the memory cells connected to 1 ).

Then, the flow advances to step S612 to determine whether or not the word line WL n +1 is the 32nd word line (for example, WL31) corresponding to the last. Steps S611 to S615 are repeated until the program target word line becomes the 32nd word line corresponding to the last word line. At this time, if the target word line is the last word, that is, the 32nd word line WL31, the second dummy read voltage Vread2 is higher than the read voltage Vread1 applied to the first dummy word line DWL0. The pass / fail of the program operation is verified by applying the word line DWL1 (S616) (S617).

At this time, if the program fails in step S617, the process returns to step S611 again, and the program voltage obtained by raising the voltage (using the ISPP method) to the last programmed word line (for example, WL31) is applied. The program operation of the memory cells connected to the word line WL31 corresponding to the same is performed again. Then, the read voltage Vread2 higher than the read voltage Vread1 applied to the first dummy word line DWL0 is applied to the second dummy word line DWL1 to verify the pass / fail of the program operation. This operation is repeatedly performed while raising the program voltage until the program passes.

If the program passes in step S617, all the operations are terminated.

7 is a diagram illustrating an applied voltage condition during a program / verify operation of a specific memory cell in a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 7, a case in which a program operation is performed on a memory cell connected to a second word line WL1 among a plurality of memory cells MC0 to MC31 will be described. As described above, the program voltage Vpgm is applied to the second word line WL1, and the pass voltage Vpass is applied to the remaining word lines WL0, WL2 to WL31. At this time, a pass voltage Vpass having the same level is applied to the first dummy word line and the second dummy word line.

After the program operation, the verify operation of the programmed memory cell MC1 is performed. The first read voltage Vread1 is applied to the remaining word lines except for the second word line WL1, and the verification voltage Vverify is applied to the second word line WL1 to determine the current measured through the bit line. If the amount is larger than the specific amount, the program voltage Vpgm is increased to perform the program operation again. On the contrary, if the amount of the current is smaller than the specific amount, the program operation is determined to be the desired level and the next word line is programmed.

For example, when a program operation is performed on the memory cell MC31 connected to the last word line WL31 among the memory cells MC0 to MC31, a program voltage is applied to the last word line WL31. When performing the verify operation, unlike the other word lines DWL0 and WL0-WL30, a second read voltage higher than the first read voltage Vread1 is applied to the second dummy word line DWL1 adjacent to the drain select transistor DST. Vread2) is applied.

 In this case, a larger amount of current flows than when the first read voltage Vread1 is applied to the second dummy word line DWL1, and thus, an effect of programming a threshold voltage higher than a desired threshold voltage level can be obtained.

Below, the principle which produces this effect is demonstrated.

When programming data to a memory cell, most of the data is programmed from a memory cell close to the source select transistor SST, that is, from a memory cell MC0 connected to the first word line WL0. Therefore, when the program operation is performed on the memory cell MC31 connected to the 32nd word line WL31, the remaining memory cells MC0-MC30 may be in a program state or an erase state. In extreme cases, all of the remaining memory cells MC0-MC30 may be programmed. At this time, since the programmed memory cells may act as a resistor due to a resistance component or the like, less current flows in the 32nd memory cell MC31. Therefore, in fact, even though the threshold voltage of the 32nd memory cell MC31 is low, it is determined that the threshold voltage is high because of seeing such a small current flowing, thereby causing a problem of less program.

In this case, when the second read voltage Vread2 higher than the first read voltage Vread1 is applied to the second dummy word line DWL1, more current is generated than when the first read voltage Vread1 is applied. Will flow. Therefore, the fact that the threshold voltage is low may be compensated for determining it to be high, thereby obtaining an effect of programming a threshold voltage higher than a desired threshold voltage level.

When the program verification of the thirty-second word line WL31 is performed, a method of reproducing the effect of the present invention by increasing the voltage of another word line may be considered. However, in this case, a read disturb problem may occur due to the increased first read voltage Vread1. However, since the second dummy word line DWL1 adjacent to the drain select transistor DST does not actually serve as a flash cell as in the present invention, a read disturb problem is caused by the increased second read voltage Vread2. Does not occur.

Here, since the voltage increase amount of the second read voltage Vread2 has to be changed to match the interference characteristics of each technology, accurate interference compensation must be determined by measurement.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a diagram illustrating a memory cell array of a general NAND flash memory device.

FIG. 2 illustrates that in the NAND flash memory device of FIG. 1, the distribution of threshold voltages of memory cells is widened due to memory cells connected to a first word line and memory cells connected to a last word line among a plurality of memory cells. Drawing.

3 is a diagram illustrating a memory cell array of a NAND flash memory device including dummy memory cells.

4 is a diagram illustrating a change in threshold voltage distribution in a NAND flash memory device having dummy word lines inserted therein.

5 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

6 is a flowchart illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

7 is a diagram illustrating an applied voltage condition during a program / verify operation of a specific memory cell in a nonvolatile memory device according to an embodiment of the present invention.

Claims (9)

A memory cell array including a plurality of strings having a source select transistor, a first dummy memory cell, a plurality of memory cells, a second dummy memory cell, and a drain select transistor connected in series between a common source line and a bit line; And A voltage configured to generate a second read voltage applied to the second dummy memory cell higher than a first read voltage applied to the first dummy memory cell during a program verify operation of the memory cell connected to the second dummy memory cell; Nonvolatile memory device including a supply. The method of claim 1, And the voltage supply unit is further configured to generate a verify voltage to be applied to a selected memory cell in the program verify operation, and apply the first read voltage to an unselected memory cell. The method of claim 1, And a row decoder configured to apply a voltage supplied from the voltage supply unit to a word line to which a corresponding memory cell is connected. The method of claim 1, The voltage supply unit applies a read voltage having the same level to the first dummy memory cell and the second dummy memory cell during a program verify operation of a memory cell not connected to the second dummy memory cell. A memory cell array is provided wherein a source select transistor, a first dummy memory cell, a plurality of memory cells, a second dummy memory cell, and a drain select transistor include a plurality of strings connected in series between a common source line and a bit line. ; Performing a program operation of a memory cell connected to the second dummy memory cell; And And applying a first read voltage to the first dummy memory cell and applying a second read voltage higher than the first read voltage to the second dummy memory cell to perform a program verify operation. Method of operation. The method of claim 5, And a verify voltage is applied to the selected memory cell and a first read voltage is applied to the unselected memory cell for the program verify operation. The method of claim 5, And applying a read voltage having the same level to the first dummy memory cell and the second dummy memory cell during a program verify operation of a memory cell not connected to the second dummy memory cell. The method of claim 6, And wherein the first read voltage is a voltage that turns on the unselected memory cells. The method of claim 5, And a memory cell in the memory cell array is a multi-level cell or a single-level cell.
KR1020090059148A 2009-06-30 2009-06-30 Nonvolatile memory device and operating method thereof KR20110001572A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8630119B2 (en) 2011-05-20 2014-01-14 Hynix Semiconductor Inc. Method for operating non-volatile memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8630119B2 (en) 2011-05-20 2014-01-14 Hynix Semiconductor Inc. Method for operating non-volatile memory device

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