KR101674070B1 - Method of program operation for non-volatile memory device - Google Patents

Abstract

The method includes performing a program operation of memory cells, performing a first verify operation of the memory cells to maintain the erase state among the memory cells, performing a second verify operation of remaining memory cells other than the cells to be erased, Wherein the first verify voltage used in the first verify operation is lower than the second verify voltage used in the second verify operation and is maintained at a constant level regardless of the change in the second verify voltage, And a program operation method of the device.

Description

[0001] The present invention relates to a method of operating a nonvolatile memory device,

The present invention relates to a program operation method of a nonvolatile memory device, and more particularly, to a program operation method of a nonvolatile memory device for preventing a reliability degradation of a verify operation due to a source bouncing phenomenon during a program verify operation.

The program operation of the nonvolatile memory element includes a program section and a verify section. In the program period, the threshold voltage of the selected memory cell is increased. In the verify period, it is determined whether the threshold voltage of the selected memory cell has increased by the reference voltage. The program operation of the nonvolatile memory device will be described in detail with reference to the following drawings.

1 is a view for explaining a programming operation of a nonvolatile memory element according to the related art. 2 is a timing chart for explaining a program verify operation of a nonvolatile memory device according to the prior art. 3 is a graph for explaining a threshold voltage according to the related art.

Referring to FIG. 1, the structure of a nonvolatile memory device will now be described.

The volatile memory device includes a memory cell array 14 in which data is stored and supplies a voltage to the word lines WL0 to WLn connected to the memory cell array 14 and the word lines WL0 to WLn And a page buffer 16 connected to the memory cell array 14 and the bit lines BL for adjusting the voltage applied to the bit lines BL.

The memory cell array 14 will be described in more detail. The memory cell array 14 includes a plurality of strings ST1 to ST4. Each of the strings has the same structure. Among them, the first string ST1 will be described as an example. The first string ST1 includes a drain select transistor DST, memory cells F0 to Fn, and a source select transistor SST connected in series. The drain of the drain select transistor DST is connected to the bit line BL and the source of the source select transistor SST is connected to the common source line CSL. The drain select transistors DST included in the different strings are connected to form a drain select line DSL. The memory cells F0 to Fn included in the different strings are connected to each other to form a plurality of word lines WL0 to WLn. In addition, the source select transistors (SST) included in the different strings are connected to form a source select line (SSL).

The programming operation of the nonvolatile memory device will now be described.

The program operation of the nonvolatile memory element includes a program section and a program verify section. In the program period, a ground voltage (for example, 0 V) is applied to the selected bit line connected to the selected memory cell, and the program voltage is applied to the selected word line to raise the threshold voltage of the selected memory cell. In the program verify period, after the program voltage is applied to the word line, the threshold voltage of the selected memory cell is verified to judge whether or not the selected memory cell is programmed.

The program verification section will be described in detail as follows.

The memory cells included in the first to fourth strings ST1 to ST4 are referred to as the first memory cell A and the second memory cell MC when the program operation is performed on the memory cells F1 connected to the first word line WL1, The memory cell B, the third memory cell C and the fourth memory cell D, respectively. At this time, after the program period, the first memory cell A is a cell whose threshold voltage is higher than the reference voltage, the second memory cell B is a cell which is to be in an erase state, and the third memory cell C is a cell whose threshold voltage is And the fourth memory cell D is a cell which will maintain the erase state.

The program verify operation may be performed by pre-charging all the bit lines BL, and then detecting a change in the voltage level of each bit line BL according to the threshold voltage of the selected memory cells. During the verify operation, the verify voltage is applied to the selected word line and the verify pass voltage is applied to the remaining word lines. For example, as described above, since the threshold voltage of the first memory cell A is higher than the reference voltage, a channel is not formed under the first memory cell A in the verify operation. Therefore, the precharge voltage level applied to the bit line BL of the first string ST1 is maintained as it is. Since the second memory cell B is a cell to maintain the erase state, a channel is formed because the threshold voltage is lower than the reference voltage. Accordingly, since a channel is formed under all the memory cells F0 to Fn of the second string ST2 to form a current path, the bit line BL and the common source line CSL are electrically connected to each other, The voltage of the bit line BL connected to the string ST2 decreases. The third memory cell C is a cell to be programmed, but a channel is formed because the threshold voltage is lower than the reference voltage, and thus the voltage level of the bit line BL decreases. Since the fourth memory cell D is a cell to be erased, a channel is formed, and thus the voltage level of the bit line BL decreases.

In particular, among cells to be programmed, in the case of cells such as the third memory cell C having a threshold voltage lower than the reference voltage, the page buffer 16 has the voltage level of the bit line BL decreased in the evaluation period (see FIG. 2) And judges it as a non-programmed cell. For example, during the program verify operation, the verify voltage Vf is applied to the selected word line (Sel.LL) during the evaluation period. The reference voltage Vv 'may be changed according to the level of the verify voltage Vf. In the evaluation period for evaluating the change in the voltage level of the bit line BL, not only the cells 34 in which the program operation has been completed, the cells in which no program is programmed (34 'in FIG. 3) Are evaluated together. Thus, the precharge voltage transmitted from the bit line BL through the active region of each string in which the channel is formed under the selected cell is simultaneously applied to the common source line CSL. As such, when the voltage is simultaneously transmitted from the plurality of strings to the common source line CSL, the resistance of the common source line CSL may increase sharply. In this case, the voltage of the bit line BL connected to un-programmed cells like the third memory cell C may not be sufficiently reduced. As a result, the page buffer 16 can judge the unprogrammed cell as a program completed cell.

In addition, the number of cells in which the program operation is completed in the corresponding string increases as the cells adjacent to the drain select transistor DST than the source select transistor SST. That is, as the cells closer to the drain select transistor DST than the source select transistor SST, the source bouncing phenomenon occurs more frequently during the program operation, and the reference voltage Vv 'level of the verify operation can be lowered . Thus, the program verify operation can be performed according to the lowered reference voltage Vv 'to judge the memory cells whose program is not completed (34' in FIG. 3) as the programmed cells (34 in FIG. 3).

In this case, in a subsequent read operation, since the cell is read and determined as a cell lower in level than the read reference voltage Vr, the reliability may be lowered.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which prioritises cells to be erased by applying a voltage lower than a verify voltage before applying a verify voltage applied to a selected word line, It is possible to prevent the voltage of the bit line from being simultaneously transmitted to the common source line in the evaluation period.

A program operation method of a nonvolatile memory device according to an example of the present invention performs a program operation of memory cells. And performs a first verify operation of the memory cells to maintain the erase state among the memory cells. Performing a second verify operation of remaining memory cells other than cells to be in an erase state. Wherein the first verify voltage used in the first verify operation is lower than the second verify voltage used in the second verify operation and is maintained at a constant level regardless of the change in the second verify voltage Program operation method.

The program operation is performed by applying the program voltage to the word lines connected to the memory cells.

The first verify operation includes precharging all the bit lines connected to the string including the memory cells and verifying only the memory cells to maintain the erase state and disabling the bit line connected to the string including the memory cells to maintain the erase state .

Discharging the bit line is performed by applying a first verify voltage of 0V or 500mV or less to the word line coupled to the memory cells to be held in the erase state.

The second verify operation verifies the memory cells on which the program operation has been performed to discharge the bit line connected to the string including the memory cell where the threshold voltage does not reach the target voltage, The bit line associated with the containing string is not discharged.

The second verify operation is performed by applying a voltage corresponding to the target voltage to the word line connected to the memory cells in which the program operation is performed.

A program operation method of a nonvolatile memory device according to another practical example of the present invention performs a program operation of selected memory cells. Precharges a bit line connected to a string including memory cells. Performing a first verify operation using the first verify voltage to perform a second verify operation using a second verify voltage higher than the first verify voltage after discharging the bit line connected to the string including the memory cell to maintain the erase state And performing a verify operation on the remaining memory cells.

The memory cell to be maintained in the erase state is applied with a voltage lower than the target voltage of the verify operation to the word line to distinguish it from the cells to be programmed.

A voltage of 0 V or 500 mV or less is applied to the word line with a voltage lower than the target voltage of the verify operation.

The program operation is performed by a single level cell (SLC) or a multi level cell (MLC) type program operation.

In the program verify operation, the cells to be erased are preferentially evaluated by applying a voltage lower than the verify voltage before applying the verify voltage applied to the selected word line, It is possible to prevent the voltage of the bit line from being simultaneously transmitted to the line.

1 is a view for explaining a programming operation of a nonvolatile memory element according to the related art.
2 is a timing chart for explaining a program verify operation of a nonvolatile memory device according to the prior art.
3 is a graph for explaining a threshold voltage according to the related art.
4 is a diagram for explaining a programming operation of the nonvolatile memory device according to the present invention.
5 is a timing chart for explaining a program operation method of a nonvolatile memory device according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limiting the scope of the invention to those skilled in the art It is provided to let you know completely.

4 is a diagram for explaining a programming operation of the nonvolatile memory device according to the present invention.

The structure of the nonvolatile memory device will now be described.

The nonvolatile memory device includes a memory cell array 104 in which data is stored and supplies a voltage to the word lines WL0 to WLn connected to the memory cell array 104 and the word lines WL0 to WLn And a page buffer 16 connected to the memory cell array 104 and the bit lines BL and adapted to adjust a voltage applied to the bit lines BL.

The memory cell array 104 will be described in more detail. The memory cell array 104 includes a plurality of strings ST1 to ST4. Each of the strings has the same structure. Among them, the first string ST1 will be described as an example. The first string ST1 includes a drain select transistor DST, memory cells F0 to Fn, and a source select transistor SST connected in series. The drain of the drain select transistor DST is connected to the bit line BL and the source of the source select transistor SST is connected to the common source line CSL. The drain select transistors DST included in the different strings are connected to form a drain select line DSL. The memory cells F0 to Fn included in the different strings are connected to each other to form a plurality of word lines WL0 to WLn. In addition, the source select transistors (SST) included in the different strings are connected to form a source select line (SSL).

5 is a timing chart for explaining a program operation method of a nonvolatile memory device according to the present invention.

4 and 5, a program operation includes a program period for applying a program voltage Vpgm to a selected word line (Sel.LL) connected to a selected memory cell, a verify period for verifying a threshold voltage of the selected memory cell .

In the program period, the program voltage Vpgm is applied to the selected word line (Sel.LL) to raise the threshold voltage of the selected memory cell. At this time, it is preferable to apply a ground voltage (for example, 0 V) to the bit line BL connected to the selected memory cell. Specifically, a case where a program operation is performed on memory cells connected to the first word line WL1 will be described. At this time, in the first cell A connected to the first word line WL1, the second cell B, the third cell C and the fourth cell D (see FIG. 4) ) And the third cell C are memory cells to be programmed and the second cell B and the fourth cell D are memory cells not to be programmed (memory cells to maintain the erase state) .

A ground voltage is applied to the bit line BL connected to the first and third strings ST1 and ST3 including the first cell A and the third cell C and the ground voltage is applied to the second cell B and The power supply voltage is applied to the bit line BL connected to the second and fourth strings ST2 and ST4 including the four cells D. [ Since the program voltage Vpgm is applied to the selected first word line WL1, each memory cell is programmed (first cell and third cell) according to the voltage difference of the bit line BL Two cells and a fourth cell).

In the verify period, the threshold voltage of the memory cells is verified to have reached the target voltage. Specifically, the verify operation pre-charges all the bit lines BL and then verifies whether the program operation is completed by sensing a voltage change of the bit line BL according to a threshold voltage of each memory cell . At this time, in order to prevent an abrupt increase in the amount of current in the common source line CSL, the verify operation is divided into a first section for verifying cells in an erased state and a second section for verifying cells in which a program operation is performed.

The first verify voltage Vf 'is applied to the selected first word line WL1 in the first period and the second verify voltage Vf is applied to the selected first word line WL1 in the second period. At this time, the second verify voltage Vf is a verify voltage for the selected memory cell, and the first verify voltage Vf 'is a verify voltage for selecting cells in an erase state. Therefore, the first verify voltage Vf 'becomes lower than the second verify voltage Vf. For example, the first verify voltage Vf 'may be applied at 0 V or a low voltage of 500 mV or less (preferably 100 mV to 500 mV). In particular, the first verify voltage Vf 'can be maintained at a constant level regardless of the second verify voltage Vf.

The verification operation will be described in detail as follows.

Precharges all bit lines (BL) of the selected memory cell block. Then, the first verify voltage Vf 'is applied to the selected first word line WL1. A channel is not formed under the first cell A and the third cell C because the first verify voltage Vf 'is lower than the threshold voltage of the memory cells in which the program operation is performed. However, only the bit lines BL connected to the second cell B and the fourth cell D are discharged because the channel is formed only under the erase state of the second cell B and the fourth cell D. That is, the current i1 as many as the number of cells in the erase state flows primarily through the common source line CSL. Then, the second verify voltage Vf is applied to the selected first word line WL1. Since the second verify voltage Vf becomes the actual verify voltage, it is possible to confirm whether the first cell A and the third cell C in which the program operation has been performed are programmed. In particular, the threshold voltage of the third cell C rises due to the program operation, but since the target voltage is not reached, a channel is formed under the cell to discharge the bit line BL. At this time, since only the current i2 corresponding to the third cell C flows through the common source line CSL, the voltage rise of the source can be suppressed.

Thus, it is possible to prevent the occurrence of source bouncing, so that it is possible to prevent an error in recognizing a slow cell in which a program is not completed in a verify operation as a program-completed cell.

Meanwhile, it is preferable that the program operation described above is applied to a single level cell (SLC) program operation in which a threshold voltage section has one program period. If the threshold voltage section is applied to a multi-level cell (MLC) program operation having a plurality of program sections, the threshold voltage section can be applied to a verify operation corresponding to the lowest program section of the program section.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

12, 102: X decoder 14, 104: memory cell array
16, 106: page buffer DSL: drain select line
WL0 to WLn: Word line SSL: Source select line
CSL: common source line DST: drain select transistor
F0 to Fn: memory cell SST: source select transistor
BL: bit line ST1 to ST4: string

Claims (10)

Performing a program operation of the memory cells;
Performing a first verify operation by applying a first verify voltage to a selected word line connected to memory cells to maintain an erase state among the memory cells; And
And applying a second verify voltage to the selected word line to perform a second verify operation of remaining memory cells other than the cells to be held in the erase state,
Wherein the first verify voltage is lower than the second verify voltage and is maintained at a constant level regardless of a change in the second verify voltage. Claim 2 has been abandoned due to the setting registration fee. 2. The method according to claim 1,
And applying a program voltage to a word line connected to the memory cells. Claim 3 has been abandoned due to the setting registration fee. 2. The method of claim 1,
Precharging all bit lines connected to a string including the memory cells; And
And verifying only the memory cells to maintain the erase state and discharging the bit line connected to the string including the memory cells to maintain the erase state. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3,
Wherein the first verify voltage is set within a range of 0V to 500mV. Claim 5 has been abandoned due to the setting registration fee. 2. The method of claim 1,
Wherein the bit line connected to the string including the memory cell in which the threshold voltage does not reach the target voltage is discharged and the memory cell in which the threshold voltage reaches the target voltage is included Wherein the bit line connected to the string does not discharge. Claim 6 has been abandoned due to the setting registration fee. 6. The method of claim 5,
Wherein the second verify operation is performed by applying a voltage corresponding to the target voltage to a word line connected to the memory cells in which the program operation is performed. Performing program operations on selected memory cells;
Precharging a bit line coupled to a string including the memory cells; And
After applying a first verify voltage to a selected word line for a first verify operation to discharge a bit line associated with a string containing a memory cell to maintain the erase state and then applying a first verify voltage to the selected word line for a second verify operation, And applying a second verify voltage higher than the verify voltage to perform a verify operation with respect to the remaining memory cells, wherein the first verify voltage is maintained at a constant level regardless of a change in the second verify voltage, A method of operating a program of a device. delete Claim 9 has been abandoned due to the setting registration fee. 8. The method of claim 7,
Wherein the first verify voltage is set within a range of 0V to 500mV. Claim 10 has been abandoned due to the setting registration fee. 8. The method of claim 7,
Wherein the program operation is performed by a single level cell (SLC) or a multi level cell (MLC) type program operation.

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