KR20110000257A - Flash memory device and fabricating method, and operating method for the same - Google Patents

Abstract

PURPOSE: A flash memory device, a fabricating method thereof, and an operating method thereof are provided to manufacture a gate having the width and the height being equivalent to the minimum width by forming a gate in self align manner. CONSTITUTION: A first polysilicon pattern(31) and a second polysilicon pattern(32) are formed on a semiconductor substrate(10). An ONO pattern(20) is formed between the first polysilicon pattern and the semiconductor substrate. A third oxide film pattern is formed between the second polysilicon pattern and the semiconductor substrate.

Description

Flash memory device, manufacturing method, and driving method thereof {flash memory device and fabricating method, and operating method for the same}

Embodiments relate to a flash memory device, a manufacturing method and a driving method thereof.

In general, non-volatile memory has the advantage that the stored data is not lost even when the power is interrupted, such as for PC bias, SettopBox, printer, and network server. It is widely used for data storage, and recently, it is widely used in digital cameras and mobile phones.

Among such nonvolatile memories, an electrically erasable programmable read-only memory (EEPROM) type flash memory device, which has a function of electrically erasing data of memory cells in a batch or sector unit, has a channel array at the drain side during programming. The threshold voltage of the cell transistor is increased by forming channel hot electrons to accumulate electrons in a floating gate.

On the other hand, the erase operation of the flash memory device generates a high voltage between the source / substrate and the floating gate to release electrons accumulated in the floating gate, thereby lowering the threshold voltage of the cell transistor.

Conventional flash memory devices have a problem that the process is complicated and yield is low by using two poly processes to form a gate.

The embodiment provides a flash memory device for reducing the number of processes and a method of manufacturing the same.

The embodiment provides a memory device capable of forming a gate in one poly process and a method of manufacturing the same.

The embodiment provides a flash memory device capable of forming a gate in a self align method and a method of manufacturing the same.

The embodiment provides a flash memory device capable of easily manufacturing a width and a height of a gate with a minimum line width, thereby improving performance, and a method of manufacturing the same.

The embodiment provides a flash memory device and a method of manufacturing the same, which are easily driven by forming a memory gate and a select gate spaced apart from each other.

The flash memory device manufactured according to the embodiment provides a method of driving a flash memory device capable of performing an erase operation by band to band tunneling (BTBT) as well as an erase by F-N tunneling.

In an exemplary embodiment, a flash memory device may include a first polysilicon pattern and a second polysilicon pattern spaced apart from each other on a semiconductor substrate, an ONO pattern formed between the first polysilicon pattern and the semiconductor substrate, and the second polysilicon. A third oxide film pattern formed between the pattern and the semiconductor substrate, a first implant region formed on the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern, and the semiconductor outside the first polysilicon pattern And a drain region formed in the substrate and a source region formed in the semiconductor substrate outside of the second polysilicon pattern.

A method of manufacturing a flash memory device according to an embodiment may include forming a fence on a semiconductor substrate, forming an ONO pattern on a semiconductor substrate on one side of the fence, and forming a first polysilicon pattern on both sidewalls of the fence. And forming a second polysilicon pattern, removing the fence, and forming a first implant region in the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern. Forming source and drain regions on the semiconductor substrate outside the silicon pattern and the semiconductor substrate outside the second polysilicon pattern.

In one embodiment, a method of driving a flash memory device includes: a first polysilicon pattern and a second polysilicon pattern spaced apart from each other on a semiconductor substrate; an ONO pattern formed between the first polysilicon pattern and the semiconductor substrate; A third oxide film pattern formed between the second polysilicon pattern and the semiconductor substrate, a first implant region formed in the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern, and an outer side of the first polysilicon pattern A flash memory device including a drain region formed in the semiconductor substrate and a source region formed in the semiconductor substrate outside the second polysilicon pattern, wherein the voltage is applied to the first polysilicon pattern and the second polysilicon pattern. Hot electrons generated in the first implant region by the difference are injected into the ONO pattern RAM is applied, a negative voltage is applied to the first polysilicon pattern, and a positive voltage is applied to the semiconductor substrate so that the programmed hot electrons exit through the semiconductor substrate and are erased.

In one embodiment, a method of driving a flash memory device includes: a first polysilicon pattern and a second polysilicon pattern spaced apart from each other on a semiconductor substrate; an ONO pattern formed between the first polysilicon pattern and the semiconductor substrate; A third oxide film pattern formed between the second polysilicon pattern and the semiconductor substrate, a first implant region formed in the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern, and an outer side of the first polysilicon pattern A flash memory device including a drain region formed in the semiconductor substrate and a source region formed in the semiconductor substrate outside the second polysilicon pattern, wherein the voltage is applied to the first polysilicon pattern and the second polysilicon pattern. Hot electrons generated in the first implant region by the difference are injected into the ONO pattern. And a negative voltage or a ground voltage are applied to the first polysilicon pattern, and a positive voltage is applied to the second polysilicon pattern so that a hot hole is applied to the ONO pattern. Is erased by injection.

The flash memory device according to the embodiment may form a gate in one poly process, thereby simplifying the process and improving yield.

Flash memory device according to the embodiment can form a gate in a self-aligned (self align) method can be manufactured with a minimum line width width and height of the gate has the effect of easy cell shrink (cell shrink) .

In the flash memory device according to the embodiment, the memory gate and the select gate are formed to be spaced apart from each other, so that the driving of each transistor is easy and there is an effect of preventing the problem of inhibiting each other's operation. As a result, the difference in gate voltage between the memory gate and the select gate can be increased, resulting in an improved program operation efficiency. In addition, in addition to F-N tunneling in an erase operation, fast and efficient erasure is possible using BTBT (band to band tunneling) cancellation.

Since the flash memory device according to the embodiment may be manufactured by reducing the number of poly processes, thermal characteristics of transistors in the logic region may be reduced, thereby improving device characteristics.

Hereinafter, a flash memory device according to an embodiment will be described in detail with reference to the accompanying drawings. However, one of ordinary skill in the art who understands the spirit of the present invention may easily propose another embodiment by adding, adding, deleting, or modifying elements within the scope of the same spirit, but this also belongs to the scope of the present invention. I will say.

Hereinafter, each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure being additionally formed therebetween. Therefore, the meaning should be determined by the technical spirit of the invention.

1 to 14 are flowcharts illustrating a manufacturing process of a flash memory device according to an embodiment.

Although not shown first, an isolation layer defining an active area is formed in the semiconductor substrate 10 on which the flash memory device is formed. The device isolation layer may be formed by etching the semiconductor substrate 10 to a predetermined depth to form a trench, and filling an insulating layer in the trench.

As shown in FIG. 1, a thermal oxide film 11 is formed on the semiconductor substrate 10.

The thermal oxide film 11 may be formed by thermal oxidation on the entire surface of the semiconductor substrate 10.

After that, as shown in FIG. 2, an insulating film 12a for forming a fence is formed on the thermal oxide film 11.

The insulating film 12a may be formed of, for example, a nitride film.

The nitride film may be formed using chemical vapor depostion (CVD).

The height and width of the memory gate and the select gate of the flash memory device may be determined according to the thickness of the insulating layer 12a.

As shown in FIG. 3, a first photoresist pattern 51 is formed on the insulating film 12a.

The first photoresist pattern 51 may be formed by applying a photoresist film on the insulating film 12a, selectively exposing and removing the exposed or unexposed portions using a developing solution.

As shown in FIG. 4, the insulating layer 12a is etched using the photoresist pattern 51. The insulating layer 12a may be etched using a method such as reactive ion etching to form a fence 12. The thermal oxide film 11 on the semiconductor substrate 10 is exposed by the fence 12.

As shown in FIG. 5, the exposed thermal oxide film 11 may be removed to expose the semiconductor substrate 10.

Alternatively, the thermal oxide film 11 may be used as a dielectric film of the memory gate without removing the thermal oxide film 11. That is, it may be used as the first oxide film of the ONO film formed under the memory gate.

The thermal oxide layer 11 is etched by wet etching, thereby forming a thermal oxide layer pattern 11a between the fence 12 and the semiconductor substrate 10.

As illustrated in FIG. 6, the entire surface of the semiconductor substrate 10 may be oxidized to form a first oxide layer 21a on the exposed semiconductor substrate 10.

The first oxide film 21a may be formed by, for example, a heat treatment process.

The first oxide film 21a may be formed to a thickness of 10 to 100 Å.

Thereafter, a nitride film 25a may be formed on the first oxide film 21a.

The nitride layer 25a may be formed using one of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process.

The nitride film 25a may be formed to a thickness of 10 to 100 mm 3.

A second oxide film 22a may be formed on the nitride film 25a.

The second oxide layer 23a may be formed on the nitride layer 25a by using one of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process.

The second oxide film 22a may be formed to a thickness of 10 to 100 Å.

The fence 12 may be formed of a nitride film, and the first oxide film may be formed on the side and the top surface of the fence 12 when the first oxide film 21a is formed by oxidizing the semiconductor substrate 10 by a heat treatment process. 21a may not be formed.

As a result, an ONO film 20a may be formed of the first oxide film 21a, the nitride film 25a, and the second oxide film 22a. The nitride layer 25a may be used as a charge trap layer in a program operation of a flash memory device.

As shown in FIG. 7, a second photoresist pattern 52 is formed on the ONO film 20a.

The second photoresist pattern 52 is formed to cover a portion of the ONO film 20a and one sidewall of the fence 12 at one side of the fence 12.

9, the ONO layer 20a is etched using the second photoresist pattern 52 as an etch mask to form an ONO pattern 20.

The ONO pattern 20 is formed along the semiconductor substrate 10 on one side of the fence 12 and on one sidewall of the fence 12.

In the ONO pattern 20, the first oxide layer pattern 21, the nitride layer pattern 25, and the second oxide layer pattern 22 are formed on the semiconductor substrate 10 on one side of the fence 12. The nitride layer pattern 25 and the second oxide layer pattern 22 are formed on sidewalls of the fence 12. That is, the first oxide layer pattern 21 is formed only on the semiconductor substrate 10 and is not formed on the sidewall of the fence 12.

Thereafter, the semiconductor substrate 10 exposed by the ONO pattern 20 and the fence 12 using a heat treatment process or the like on the entire surface of the semiconductor substrate 10 on which the ONO pattern 20 and the fence 12 are formed. ) Is oxidized to form a third oxide film 23a.

Thereafter, a polysilicon film 30a is formed on the third oxide film 23a.

The polysilicon layer 30a may be laminated to a thickness of about 2000 to 6000 kPa by a process such as low pressure chemical vapor deposition (LPCVD).

As shown in FIG. 10, the polysilicon layer 30a is etched by blanket etching to form a first polysilicon pattern 31 and a second polysilicon pattern 32 on both sides of the fence 12. ). In this case, the third oxide layer 23a may also be selectively removed to form a third oxide layer pattern 30 under the second polysilicon pattern 32.

Widths of the first polysilicon pattern 31 and the first polysilicon pattern 32 may be 80 to 250 nm.

Since the third oxide film 23 of the select transistor is formed separately from the process of forming the ONO pattern 20, the thickness of the third oxide film can be stably formed.

Since the first polysilicon pattern 31 and the second polysilicon pattern 32 are formed in a self align by the fence 12, misses that may occur when the pattern is formed by a photo process Misalignment can be prevented. Therefore, process margins may be secured when the polysilicon pattern is formed, and the first polysilicon pattern 31 and the second polysilicon pattern 32 may be formed to have a uniform width.

The first polysilicon pattern 31 acts as a memory gate and the second polysilicon pattern 32 acts as a select gate, and the first and second polysilicon patterns 31 and 32 are different from each other. It can be formed using the poly process of the yield is increased and the effect is to reduce the manufacturing cost.

In addition, since the first polysilicon pattern 31 and the second polysilicon pattern 32 for the flash memory device are formed in one poly process, thermal applied to the transistors in the logic region due to polysilicon deposition. Thermal budget can be reduced.

The first polysilicon pattern 31 is formed on the ONO pattern 20 on one side of the fence 12. The second polysilicon pattern 32 may be formed on the sidewall of the fence 12 and a part of the semiconductor substrate 10 at the other side of the fence 12.

Due to the ONO pattern 20, the thicknesses of the first polysilicon pattern 31 and the second polysilicon pattern 32 may be different from each other, but the first and second poly from the semiconductor substrate 10 may be different from each other. The heights up to the top surfaces of the silicon patterns 31 and 32 may be the same.

Thereafter, as shown in FIG. 11, the first polysilicon pattern 31. A third photoresist pattern 53 is formed on the semiconductor substrate 10 on which the second polysilicon pattern 32 is formed.

The third photoresist pattern 53 exposes the fence 12 formed between the first polysilicon pattern 31 and the second polysilicon pattern 32.

A portion of the upper surface of the first polysilicon pattern 31 and a portion of the upper surface of the second polysilicon pattern 32 may be exposed by the third photoresist pattern 53.

As shown in FIG. 12, the fence 12 is removed using the third photoresist pattern 53 as an etching mask.

Thereafter, the thermal oxide pattern 11a under the fence 12 may also be removed.

Subsequently, a first concentration having a high concentration in the active region of the semiconductor substrate 10 exposed by the first and second polysilicon patterns 31 and 32 using the third photoresist pattern 53 as an ion implantation mask. The first implant region 61 is formed by implanting conductive impurities.

An interval between the first polysilicon pattern 31 and the first polysilicon pattern 32 facing each other may be 80 to 250 nm.

The first implant region 61 may be formed between the first polysilicon pattern 31 and the second polysilicon pattern 32.

The first implant region 61 may be used as a source region of a memory transistor including the first polysilicon pattern 31. At the same time, the first implant region 61 may be used as a drain region of the select transistor including the second polysilicon pattern 32. Accordingly, a hot carrier formed by the select transistor is transferred from the select transistor to the memory transistor through the first implant region 61, and the nitride layer pattern 25 of the ONO pattern 20 of the memory transistor is formed. Can be trapped).

Next, the third photoresist pattern 53 is removed.

As shown in FIG. 13, a low concentration of the first conductive type impurity is implanted onto the semiconductor substrate 10 to form one side of the first polysilicon pattern 31 and one side of the second polysilicon pattern 32. Second implant region 62 is formed.

The second implant region 62 is formed on one side of the first polysilicon pattern 31 in which the first implant region 61 is not formed. In addition, the second implant region 62 is formed on one side of the second polysilicon pattern 32 in which the first implant region 62 is not formed.

The second implant region 62 may be an LDD region.

Here, the first conductive impurity may be an n-type impurity or a p-type impurity.

Subsequently, as shown in FIG. 14, an insulating film is formed on the entire surface of the semiconductor substrate 10 on which the first polysilicon pattern 31 and the second polysilicon pattern 32 are formed and etched back to form the first polysilicon pattern. Gate spacers 35 may be formed on sidewalls of the silicon pattern 31 and the second polysilicon pattern 32.

Next, the third implant region 63 may be formed by implanting a high concentration of the first conductive type impurity into the semiconductor substrate 10.

The third implant region 63 may be formed deeper in the second implant region 62 exposed by the gate spacer 35.

The third implant region 63 may be a source / drain region implanted with high concentration.

The third implant region 63 may form a drain region of the first polysilicon pattern 31.

The third implant region 63 may form a source region of the second polysilicon pattern 32_.

Thereby, the memory transistor and the select transistor of the flash memory element can be formed.

Although not shown, a bit line may be formed through a contact electrode and a wiring forming process contacting the drain region of the memory transistor. In addition, a word line may be formed through a contact electrode and a wiring forming process in contact with the first polysilicon pattern. In addition, the contact electrode and the wiring contacting the source region and the second polysilicon pattern of the select transistor may be formed through the contact electrode and the wiring forming process.

The program operation of the flash memory device manufactured by the above process is as follows.

A voltage of about the threshold voltage Vt is applied to the gate of the select transistor.

Then, a high voltage Vpp is applied to the gate of the memory transistor.

A voltage of Vdd is then applied to the drain (bit line) of the memory transistor.

Due to the sudden voltage difference between the gate of the select transistor and the memory transistor, a deep depletion region is formed therebetween, thereby forming a potential well. At this time, a lot of hot carriers are generated by a strong electric field, and thus the program efficiency is improved. This is called hot carrier injection (HCI).

An erase operation of a flash memory device according to an embodiment is as follows.

The drain (bit line) of the memory transistor and the source of the select transistor are floated.

In addition, a ground voltage is applied to the gate of the select transistor.

When a high voltage Vpp is applied to the semiconductor substrate and -Vpp is applied to the gate (word line) of the memory transistor, carriers trapped in the nitride film pattern of the ONO pattern of the memory transistor are ejected through the bulk. Erase is made. This is called F-N tunneling.

The flash memory device manufactured according to the embodiment may not only erase by F-N tunneling but also erase by band to band tunneling (BTBT).

In order to increase the erase efficiency by the BTBT, the concentration of the first implant region may be higher.

The drain (bit line) of the memory transistor may be floated or a high voltage Vpp may be applied. The source of the select transistor is connected to ground.

In addition, a high voltage Vpp is applied to the gate of the select transistor.

When the semiconductor substrate is floated and a -Vpp or ground voltage GND is applied to the gate (word line) of the memory transistor, hot holes are injected into the nitride layer pattern of the ONO pattern of the memory transistor to erase the semiconductor substrate. Is done.

When the flash memory device is erased using the BTBT method as described above, byte erasing is possible for each cell as compared to the FN tunneling method in which all cells are erased through bulk. Can be.

In addition, the BTBT method erases by injecting a hot hole, and there is an advantage in that the erase operation can be performed with a smaller bias than the F-N tunneling method, which requires biasing a high voltage to escape the trapped charge through the bulk.

The above description is merely an example for explaining the operation of the flash memory device according to the embodiment, and may be changed according to the design of the device. In particular, there is no need to apply negative bias to the word line, which can simplify circuit design.

The flash memory device according to the embodiment may form a gate in one poly process, thereby simplifying the process and improving yield.

Flash memory device according to the embodiment can form a gate in a self-aligned (self align) method can be manufactured with a minimum line width width and height of the gate has the effect of easy cell shrink (cell shrink) .

In the flash memory device according to the embodiment, the memory gate and the select gate are formed to be spaced apart from each other, so that the driving of each transistor is easy and there is an effect of preventing the problem of inhibiting each other's operation. As a result, the difference in gate voltage between the memory gate and the select gate can be increased, resulting in an improved program operation efficiency. In addition, in addition to F-N tunneling in an erase operation, fast and efficient erasure is possible using BTBT (band to band tunneling) cancellation.

Since the flash memory device according to the embodiment may be manufactured by reducing the number of poly processes, thermal characteristics of transistors in the logic region may be reduced, thereby improving device characteristics.

Although the above has been described with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above unless they depart from the essential characteristics of the present embodiments. It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 14 are flowcharts illustrating a manufacturing process of a flash memory device according to an embodiment.

Claims (19)

A first polysilicon pattern and a second polysilicon pattern spaced apart from each other on the semiconductor substrate; An ONO pattern formed between the first polysilicon pattern and the semiconductor substrate; A third oxide film pattern formed between the second polysilicon pattern and the semiconductor substrate; A first implant region formed in the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern; A drain region formed on the semiconductor substrate outside of the first polysilicon pattern; And And a source region formed on the semiconductor substrate outside the second polysilicon pattern. The method of claim 1, A gate spacer formed on sidewalls of the first polysilicon pattern and the second polysilicon pattern; And And a second implant region formed in the semiconductor substrate under the gate spacer. The method of claim 1, Flash memory device, characterized in that the width of the first polysilicon pattern and the second polysilicon pattern is the same. The method of claim 1, And a height of the first polysilicon pattern and the second polysilicon pattern is the same from the semiconductor substrate. Forming a fence on the semiconductor substrate: Forming an ONO pattern on the semiconductor substrate on one side of the fence; Forming a first polysilicon pattern and a second polysilicon pattern on both sidewalls of the fence; Removing the fence; Forming a first implant region in the semiconductor substrate between the first polysilicon pattern and the second polysilicon pattern: And forming source and drain regions on the semiconductor substrate outside of the first polysilicon pattern and the semiconductor substrate outside of the second polysilicon pattern. The method of claim 5, Before forming the first polysilicon pattern and the second polysilicon pattern, And forming a third oxide film on the semiconductor substrate having the ONO pattern formed thereon. The method of claim 5, Forming the fence, Forming a thermal oxide film on the semiconductor substrate; Forming a nitride film on the thermal oxide film; And And patterning the nitride film to form the fence. The method of claim 5, In the step of forming the ONO pattern, Forming a first oxide film on the semiconductor substrate on which the fence is formed, a nitride film on the first oxide film, and a second oxide film on the nitride film; Forming a first photoresist pattern on the second oxide film; The second oxide film, the nitride film, and the first oxide film are etched using the first photoresist pattern as a mask to include a first oxide pattern, a nitride film pattern, and a second oxide film pattern on the semiconductor substrate on one side of the fence. A method of manufacturing a flash memory device comprising the step of forming an ONO pattern. The method of claim 8, And forming the nitride layer pattern and the second oxide layer pattern on one sidewall of the fence to extend from the nitride layer pattern and the second oxide layer pattern of the ONO pattern. The method of claim 8, And the first oxide film is formed by a heat treatment process, and the nitride film and the second oxide film are formed by a deposition process. The method of claim 5, In the forming of the first polysilicon pattern and the second polysilicon pattern, Forming a polysilicon film on an entire surface of the semiconductor substrate on which the ONO pattern and the fence are formed; Etching the entire polysilicon layer to form the first polysilicon pattern on the ONO pattern on one side of the fence and the second polysilicon pattern on the other side of the fence. The method of claim 5, In the step of removing the fence, Forming a second photoresist pattern exposing the fence on the semiconductor substrate; And removing the fence by using the second photoresist pattern as a mask. The method of claim 12, The first implant region is formed by implanting a first conductive type impurity between the first polysilicon pattern and the second polysilicon pattern using the second photoresist pattern as a mask to form the first implant region. . The method of claim 5,  Forming source and drain regions on the semiconductor substrate; Implanting first conductive impurities into the semiconductor substrate to form second implant regions on the outer side of the first and second polysilicon patterns, respectively; Forming a gate spacer on sidewalls of the first polysilicon pattern and the second polysilicon pattern; And And implanting first conductive impurities into the semiconductor substrate to form third implant regions on the outer side of the first and second polysilicon patterns, respectively. The method of claim 14, The impurity concentration of the first and third implant region is higher than the impurity concentration of the second implant region. The method of claim 6, The width of the first polysilicon pattern and the second polysilicon pattern is the same method of manufacturing a flash memory device. The method of claim 6, And a height of the first polysilicon pattern and the second polysilicon pattern from the semiconductor substrate is the same. The flash memory device according to any one of claims 1 to 4, wherein The hot electrons generated in the first implant region are injected into the ONO pattern by a voltage difference applied to the first polysilicon pattern and the second polysilicon pattern, and a program is performed. and a negative voltage is applied to the semiconductor substrate so that the programmed hot electrons exit through the semiconductor substrate and are erased. The flash memory device according to any one of claims 1 to 4, wherein The hot electrons generated in the first implant region are injected into the ONO pattern by a voltage difference applied to the first polysilicon pattern and the second polysilicon pattern, and the program is performed. A negative voltage or a ground voltage is applied to a silicon pattern, and a positive voltage is applied to the second polysilicon pattern to inject a hot hole into the ONO pattern to erase the flash memory device. Driving method.

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