KR20100135093A - Method for detecting pattern error - Google Patents

Method for detecting pattern error Download PDF

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Publication number
KR20100135093A
KR20100135093A KR1020090053555A KR20090053555A KR20100135093A KR 20100135093 A KR20100135093 A KR 20100135093A KR 1020090053555 A KR1020090053555 A KR 1020090053555A KR 20090053555 A KR20090053555 A KR 20090053555A KR 20100135093 A KR20100135093 A KR 20100135093A
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KR
South Korea
Prior art keywords
pattern
layout
wafer
image
simulation
Prior art date
Application number
KR1020090053555A
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Korean (ko)
Inventor
김중찬
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090053555A priority Critical patent/KR20100135093A/en
Publication of KR20100135093A publication Critical patent/KR20100135093A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Data of the layout of the target pattern to be transferred onto the wafer is obtained, an image of the wafer pattern formed by transferring the layout of the target pattern onto the wafer is obtained, and the layout of the target pattern is simulated. A simulation model is used to obtain data of a simulation contour on the layout of the target pattern. By overlaying the layout of the simulation contour and the target pattern, the curved portion of the simulation contour is recognized as a straight line. Pattern error of the semiconductor device which performs image matching overlapping the image of the simulation contour and the wafer pattern based on the part recognized as a straight line, and extracts a point generated during image matching as a pattern error. ) Provides a detection method.

Description

Method for detecting pattern error of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to a method for more precisely detecting hot spots in which pattern errors are caused.

In the process of manufacturing a semiconductor device, a target layout to be implemented on a wafer is designed, data thereof is built into a database, a photomask conforming to the target layout is formed. In addition, the exposure process using a photomask is performed, including transferring the pattern onto the wafer. A process of detecting a pattern error is performed to confirm whether the pattern implemented on the wafer is normally implemented. By detecting the killing hot spots, the reliability of the pattern implemented on the wafer is ensured, and the characteristics of the semiconductor device constituted by these patterns are secured.

Metrology tools are used for the detection of pattern errors, and for more accurate error detection, a method of detecting errors is attempted by comparing the shape of the wafer pattern implemented on the actual wafer with the data of the designed target layout. have. However, due to various factors such as chip makers, semiconductor device types, and application of low dielectric constant k1 materials, the shape and target layout of the actual wafer pattern on the wafer may be different from each other. do. Accordingly, it is difficult to simply match an image of the target layout with the measured wafer pattern, and it is difficult to proceed with the inspection by such image comparison. As such, the image matching itself is difficult, and thus a limit is generated in detecting a real hot spot. Therefore, there is a demand for developing a method capable of more accurately inducing image matching and more accurately detecting pattern errors.

The present invention proposes a method for more accurately detecting a pattern error of a wafer pattern by image matching using an image of a pattern implemented on a wafer.

One aspect of the present invention includes the steps of obtaining data of a layout of a target pattern to be transferred onto a wafer; Acquiring an image of a wafer pattern formed by transferring the layout of the target pattern onto the wafer; Obtaining data of a simulation contour on the layout of the target pattern by using a model simulating the layout of the target pattern; Overlapping the layout of the simulation contour and the target pattern to recognize a curved portion of the simulation contour as a straight line; An image matching step of overlapping the simulation contour and the image of the wafer pattern based on the portion recognized as the straight line; And extracting a point generated at the time of image matching as a pattern error.

An embodiment of the present invention may propose a method for more accurately detecting a pattern error of a wafer pattern by image matching using an image of a pattern implemented on a wafer.

1 to 8 are diagrams illustrating a pattern error detection method of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a target layout of a pattern to be implemented on a wafer is designed by a pattern transfer process such as exposure and etching, and the data is constructed as a DB (110). This target layout may be presented in the form of a layout 210 as shown in FIG. An image of the wafer pattern formed by transferring the target layout 210 to the pattern transfer process may be presented as the image 220 shown in FIG. 3, and the image of the wafer pattern is acquired and also constructed in the DB as data. (120 of FIG. 1).

The target layout 210 is included in the portion 211 where the target layout 210 and the wafer pattern image 220 are fundamentally different from each other. That is, since the target layout 210 is designed in consideration of the optical proximity effect (OPE) during the exposure process, step shapes or projections may be completely different from those of the pattern image 220 implemented on the actual wafer. The edges of the target layout 210 and the wafer pattern image 220 are detected and set as the matching criteria, and the target layout 210 and the wafer pattern image 220 are matched with each other (Fig. 1, 130). At this time, it is determined whether the image matching is normal (140 in FIG. 1), and if normal, a pattern error value (170 in FIG. 1) is extracted.

When it is determined that the image matching is abnormal and fails, the process of extracting a subsequent pattern error value cannot be performed. As the cause of the image matching failure, it may be considered that the edge detection is difficult due to the portion 211 where the wafer pattern image 220 and the target layout 210 are different. If the edge detection fails, image matching is substantially impossible and subsequent pattern error detection cannot be performed.

In this case, in the embodiment of the present invention, as shown in FIG. 4, data of a simulation contour 230 for the target layout (210 in FIG. 2) is obtained (150 in FIG. 1). This simulation process can be performed using an EDA program. That is, data of a simulation contour 230 of the layout 210 of the target pattern may be obtained by simulating using a model simulating the layout 210 of the target pattern. In this case, the simulation model may be a model that simply processes a step shape or a projection into a curve or a straight line, or a model simulating a process of transferring a pattern onto a wafer.

According to the conditions used in the simulation, the resulting contour 230 is a shape in which protrusions or staircases have been removed, and are processed as curves. Considering the partially enlarged contour 231 of FIG. 5, which partially shows the portion of the simulation contour 230 of FIG. 4, there is a portion 233 processed by the curve 232 by the simulation. Such curves 232 may be recognized as straight portions in the measurement equipment. However, when the curves are distorted beyond the recognition criteria in the measurement equipment and curved or deviate greatly from the straight lines, the curves 232 may be restricted to recognize the image and match images in the measurement equipment. .

Considering the enlarged layout 212 of FIG. 5 in which the target layout 210 of FIG. 2 is partially enlarged, the enlarged target layout 212 may include a difference portion 213 in which protrusions such as staircases or teeth are arranged. do. In the simulation contour 240 of FIG. 7, which is a result of simulating this, the difference portion 213 is curved and the portion 241 is displayed as a result. However, in order to ensure that the portion 241 processed by such a curve is normally recognized by the measurement equipment, as shown in FIG. 8, the simulation contour 240 and the layout 212 of the target pattern are overlapped to form the curved portion of the simulation contour. Is set to be recognized as a straight line 250 (160 in FIG. 1). In the process of recognizing a straight line, the virtual straight line 250 is set such that a curved portion corresponding to the straight line of the layout 212 of the target pattern is recognized as a straight line.

Based on the portion recognized as the straight line 250, image matching is performed to overlap the simulation contour 250 and the image of the wafer pattern (220 in FIG. 3). The point where the difference occurs as an image matching result is extracted as a pattern error (170 of FIG. 1).

As described above, the present invention utilizes the data of the simulation contour in which the target layout is modified when the data of the target layout and the image of the wafer pattern are matched and inspected. In consideration of the simulation contour data and the data of the target layout at the same time, the inspection data in which the curved portion is recognized as a straight line is generated, thereby inducing image matching to be performed without a matching failure. Since image matching failure is suppressed, more accurate pattern error detection is possible, and more accurate quantitative data can be collected and used.

1 is a flowchart illustrating a pattern error detection method of a semiconductor device according to an exemplary embodiment of the present invention.

2 to 8 are layout diagrams provided to explain a method for detecting a pattern error of a semiconductor device according to an exemplary embodiment of the present invention.

Claims (3)

Obtaining data of a layout of a target pattern to be transferred onto the wafer; Acquiring an image of a wafer pattern formed by transferring the layout of the target pattern onto the wafer; Obtaining data of a simulation contour on the layout of the target pattern using a simulation model of the layout of the target pattern; Overlapping the layout of the simulation contour and the target pattern to recognize a curved portion of the simulation contour as a straight line; An image matching step of overlapping the simulation contour and the image of the wafer pattern based on the portion recognized as the straight line; And And extracting a point generated during the image matching as a pattern error. The method of claim 1, The simulation model A pattern error detection method of a semiconductor device constructed to curve a stepped shape or an arrangement of protrusions existing in the target pattern layout. The method of claim 1, The simulation model And a pattern error detection method of a semiconductor device constructed by simulating a process of transferring the target pattern layout onto the wafer.
KR1020090053555A 2009-06-16 2009-06-16 Method for detecting pattern error KR20100135093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090053555A KR20100135093A (en) 2009-06-16 2009-06-16 Method for detecting pattern error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090053555A KR20100135093A (en) 2009-06-16 2009-06-16 Method for detecting pattern error

Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210020086A (en) * 2018-07-12 2021-02-23 에이에스엠엘 네델란즈 비.브이. Automatically utilizes pattern recognition to improve SEM contour measurement accuracy and stability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210020086A (en) * 2018-07-12 2021-02-23 에이에스엠엘 네델란즈 비.브이. Automatically utilizes pattern recognition to improve SEM contour measurement accuracy and stability

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