KR101033225B1 - Method for performing OPC on pattern layout - Google Patents

Abstract

First modeling using a contour and a line width (CD) of a resist pattern obtained by obtaining a test layout and pattern transfer onto a wafer, and then obtained by etching using the resist pattern as an etching mask. Second modeling using an image of the wafer pattern is performed, and a simulation model by the first and second modeling is obtained. After obtaining the original layout to be implemented on the wafer, the original layout is optically corrected by optical proximity effect (OPC) and verified using a simulation model to correct the optically corrected layout when defects are detected during verification. We present a method for compensating the pattern layout for optical proximity effects.

OPC, CD, Contact Hole, SEM

Description

Method for performing OPC on pattern layout

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of laying out a pattern layout (OPC: Optical Proximity Correction).

As semiconductor devices such as memory devices are rapidly integrated and pattern sizes are reduced, a higher resolution is required for an exposure process for transferring a pattern onto a wafer. An original, which is a layout of target pattern designed for pattern transfer, in order to compensate for the optical proximity effect (OPE) that may be caused during pattern transfer by the exposure process and to transfer the pattern with higher precision. The original layout is OPC corrected. In order to confirm in advance whether the result of the pattern transfer of the OPC corrected layout by the exposure process matches the layout of the target pattern, a verification process after the OPC is performed. After the OPC verification process, a simulation contour is obtained using a simulation model reflecting the exposure process of the OPC layout, and the simulation contour and the target pattern layout are compared to verify whether or not it is matched.

The process of modeling an OPC process or a simulation model for OPC verification is being formulated to describe how the original layout modified and modified by OPC is implemented on the actual wafer. The results of this simulation model can be presented as a contour depicting the shape or shape of the resist pattern implemented on the actual wafer. The simulation model introduces a test exposure and development process to obtain an image of a resist pattern embodied on an actual wafer, and the shape of the image and process conditions such as exposure and development used therein as variables. It is extracted and built. Therefore, the simulation model is effective to provide a contour for predicting the shape or shape of a resist pattern to be formed into a wafer pattern, and has a high predictive power for this, and is used as a means of increasing OPC accuracy.

The wafer patterns forming semiconductor devices are diversified, and the process margin of the selective etching process performed after the resist pattern formation is becoming more and more stringent, so that no particular problem is found in the simulation contour of the predicted resist pattern. Nevertheless, weak points such as pattern defects are occurring in the final wafer pattern. This has been confirmed to be caused by a slope of the pattern shape due to the difference in the line width caused by the selective etching performed after the resist pattern formation, that is, the etch bias. Therefore, the development of a method to verify OPC results more accurately is required.

The present invention is to propose a method for correcting the optical proximity effect of the pattern layout that can more accurately verify the optical proximity effect correction (OPC) layout by introducing a simulation model that can predict the shape or shape of the resulting pattern after etching.

One aspect of the invention, the step of obtaining a test layout (test layout); A first modeling step using a contour and a line width CD of a resist pattern obtained by pattern transfer of the test layout onto a wafer; A second modeling step using an image of a wafer pattern obtained by etching using the resist pattern as an etching mask; Obtaining a simulation model by the first and second modeling; Obtaining an original layout to implement on the wafer; Optical proximity effect correction (OPC) the original layout; Verifying the optical proximity effect corrected layout using the simulation model; And correcting the optical proximity effect corrected layout when a defect is detected during the verification.

The second modeling step may be performed by extracting a line width (CD) of the wafer pattern from the image of the wafer pattern and applying the variable to the simulation model.

The second modeling step may be performed by extracting a top contour and a bottom contour of the wafer pattern from the image of the wafer pattern and applying the variable to the simulation model.

Extracting a top CD from a top contour of the wafer pattern, extracting a bottom CD from the bottom contour, and extracting the wafer pattern from the top line width and the bottom line width. It can be performed by estimating the side slope of the applied to the simulation model as a variable.

A top CD is extracted from a top contour of the wafer pattern, a bottom CD is extracted from the bottom contour, and a bridge between the wafer patterns is formed from the top line width. bridge) and applying it as a variable to the simulation model to verify whether the wafer pattern is open defective from the bottom line width.

According to an embodiment of the present invention, by adding a variable of a simulation model using an image of a result pattern after etching, prediction based on the result pattern after etching can be performed to more accurately verify the OPC layout. have.

1 to 6 are diagrams provided to explain a method of verifying an optical proximity corrected layout according to an embodiment of the present invention.

Referring to FIG. 1, a database (DB) is obtained by obtaining data of an original layout in which a layout of a target pattern for pattern transfer is designed through exposure, development, and etching process on a wafer. To build (110). Optical proximity effect correction (OPC) modeling and OPC process is performed to modify the original layout (120). Thereafter, a verification model for verifying an OPC layout is constructed (130).

Such verification modeling is a process of reflecting a variable or condition representing a transcription process in a simulation model simulating a pattern transcription process. In the embodiment of the present invention, not only the variables extracted from the image of the resist pattern for verification modeling but also the variables extracted from the image of the wafer pattern resulting from the selective etching using the resist pattern as an etching mask are used. . To this end, image data of the resist pattern and the wafer pattern may be secured by scanning electron microscopy (SEM).

In order to secure the image data of the resist pattern and the wafer pattern, after obtaining a test layout, a process of pattern transfer of the test layout onto the wafer may be performed. In this case, the original layout may be used as the test layout, and the result layout of the OPC may be used as the test layout. An exposure process of pattern transfer of the test layout or the original layout to the resist layer applied on the wafer is performed and developed to form a resist pattern. SEM images of the resist patterns are obtained, and first modeling is performed by measuring line widths (CDs) and the like from the obtained image data and applying them to the simulation model as variables (131).

When the original layout is applied to the simulation model as a test procedure, the simulation contour 210 as shown in FIG. 2 may be obtained. In this case, an image of the resist pattern embodied on the actual wafer may be obtained by the image 230 shown in FIG. 3. Comparing the contour 210 and the image 230 of Figs. 2 and 3, it can be seen that the prediction of the resist image through the simulation is relatively accurate.

After performing the first modeling, a wafer pattern is implemented on the wafer as a result of selective etching using a resist pattern having a shape such as the image 230 of FIG. 3 as an etch mask. SEM images for this wafer pattern are obtained with an image 250 as shown in FIG. 4. Comparing the image 250 of FIG. 4 with the image 230 of FIG. 3, it can be seen that a significant linewidth (CD) reduction occurs at the portion indicated by the horizontal dotted line of the image 250 of FIG. 4.

When the original layout of the OPC is verified using a simulation model in which variables are reflected only by the first modeling, it is determined that a normal pattern is formed as in the simulation contour 210 of FIG. 2, so that the original layout is not detected as a defect. Considering the horizontal dotted line portion 250 of FIG. 4, the horizontal dotted line portion should be detected as a pattern defect that does not secure the required line width. This decrease in line width is interpreted as a result of the slope of the pattern side accompanying etching, and by the occurrence of this slope, the top CD of the wafer pattern may meet the required line width, but the bottom line width (bottom CD) May fall short of). It is possible to determine whether the bridge between the patterns from the upper line width, but it is not possible to determine whether the contact hole is open or the bottom line width of the damascene pattern is secured by the upper line width. Therefore, accurate OPC modeling and verification cannot be achieved by reflecting variables in the simulation model considering only the resist pattern.

After performing the first modeling 131 to apply the data of the resist contour obtained from the resist image 230 and the resist line width (CD) extracted from the contour to the simulation model, an image of the resulting wafer pattern after etching (FIG. 4) We introduce an additional modeling process that applies other variables extracted from the model to the simulation model. For example, the second modeling may be performed by extracting the line width CD of the pattern from the image of the wafer pattern 250 (FIG. 4) and applying the variable to the simulation model (133 of FIG. 1). In addition, the top contour and bottom contour of the wafer pattern are extracted from the image of the wafer pattern (250 in FIG. 4), the top line width (CD) of the pattern is extracted from the top contour, and the bottom contour is extracted from the bottom contour. The lower line width CD of the pattern may be extracted and third modeling applied as a variable to the simulation model may be performed (135 of FIG. 1).

As described above, simulation modeling is performed by further using an image of the wafer pattern, and verification of the layout in which the original layout is OPC is performed using the modeled simulation model (140 of FIG. 1). As a result of applying the OPC layout to the modeled simulation model, the simulation contour 260 is obtained as shown in FIG. 5. Simulation contour 260 will provide a top contour 261 and a bottom contour 263 that depict the top and bottom contours of the wafer pattern. The upper line width 261 may be extracted from the upper contour 261 to detect whether the OPC layout is defective, or the bottom line width may be extracted from the bottom contour 263 to detect whether the OPC is defective. 1, 150). At this time, by considering the upper contour 261 and the bottom contour 263 together, it is also possible to determine whether there is a defect according to the degree of inclination of the wafer pattern at the weak point 265. Accordingly, more accurate OPC results and OPC verification results can be obtained than in the case of modeling and verifying only variables obtained from the image of the resist pattern (230 of FIG. 3).

Referring to FIG. 6, when the contact hole pattern is formed as a wafer pattern, a modeling process of extracting the upper contour 271 from the image 270 of the obtained contact hole pattern and applying it to the simulation model may be performed. By applying the data of the upper contour 271, for example, the upper separation line width 272 as a variable to the simulation model, it is possible to check the upper separation interval in the simulation contour according to the OPC modified layout during OPC verification, resulting in bridge defects You can check whether or not. In addition, a modeling process of applying the bottom contour 273 to the simulation model may be performed from the image 270. By applying the data of the floor contour 273, for example, the floor line width 274 as a variable to the simulation model, the contact hole is opened by whether or not the floor line width is secured in the simulation contour according to the OPC modified layout during OPC verification. Can be checked. As a result, more accurate and accurate OPC verification is possible.

Defects may be detected by OPC verification (150 in FIG. 1), and the process of correcting the OPC again or correcting the OPC may be performed when the defect is detected.

In the embodiment of the present invention, by applying the image of the wafer pattern after etching to the modeling of the simulation model, the modeling accuracy can be improved, and the weak point that can be generated due to the inclination of the pattern side can be detected, thereby OPC The reliability of the verification can be increased.

1 is a flowchart illustrating a method of verifying an optical proximity effect corrected layout according to an exemplary embodiment of the present invention.

2 to 6 are image diagrams provided to explain a method of verifying a light proximity effect corrected layout according to an exemplary embodiment of the present invention.

Claims (4)

Obtaining a test layout; A first modeling step using a contour and a line width CD of a resist pattern obtained by pattern transfer of the test layout onto a wafer; A second modeling step using an image of a wafer pattern obtained by etching using the resist pattern as an etching mask; Obtaining a simulation model by the first and second modeling; Obtaining an original layout to implement on the wafer; Optical proximity effect correction (OPC) the original layout; Verifying the optical proximity effect corrected layout using the simulation model; And And correcting the optical proximity effect corrected layout when a defect is detected during the verification. The method of claim 1, The second modeling step Extracting a top contour and a bottom contour of the wafer pattern from the image of the wafer pattern and applying the variable to the simulation model as a variable. The method of claim 2, Extracting a top CD from a top contour of the wafer pattern, extracting a bottom CD from the bottom contour, and extracting the wafer pattern from the top line width and the bottom line width. Estimating the lateral slope of and applying it as a variable to the simulation model. The method of claim 2, A top CD is extracted from a top contour of the wafer pattern, a bottom CD is extracted from the bottom contour, and a bridge between the wafer patterns is formed from the top line width. and applying a variable to the simulation model to verify the open defect of the wafer pattern from the bottom line width.

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