KR20100134455A - Method of fabricating transistor for improving breakdown characteristics - Google Patents
Method of fabricating transistor for improving breakdown characteristics Download PDFInfo
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- KR20100134455A KR20100134455A KR1020090053080A KR20090053080A KR20100134455A KR 20100134455 A KR20100134455 A KR 20100134455A KR 1020090053080 A KR1020090053080 A KR 1020090053080A KR 20090053080 A KR20090053080 A KR 20090053080A KR 20100134455 A KR20100134455 A KR 20100134455A
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- implantation
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- implanting
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 230000015556 catabolic process Effects 0.000 title abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 132
- 238000002513 implantation Methods 0.000 claims abstract description 128
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000010438 heat treatment Methods 0.000 claims abstract description 24
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 109
- 239000002019 doping agent Substances 0.000 claims description 45
- 239000012535 impurity Substances 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 20
- 238000010884 ion-beam technique Methods 0.000 claims description 11
- 239000007943 implant Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A transistor manufacturing method for improving breakdown characteristics of the present invention includes forming a gate stack on a semiconductor substrate, and having a relatively high first injection energy and a relatively low first dose with respect to the semiconductor substrate exposed by the gate stack. Performing a first ion implantation, and performing a second ion implantation for the source / drain regions on the exposed portion of the semiconductor substrate on which the first ion implantation is performed, with an implantation energy lower than the first implantation energy and a higher dose than the first dose And performing heat treatment on the semiconductor substrate on which the first ion implantation and the second ion implantation are performed.
Description
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a transistor manufacturing method for improving breakdown characteristics.
Recently, as the integration degree of a semiconductor device is rapidly increased, the size of a transistor constituting the semiconductor device is also rapidly decreasing. As the size of the transistor becomes smaller, the width of the gate becomes narrower, and accordingly, the channel length overlapping the gate becomes shorter. If the channel length becomes shorter than a certain level, a short channel effect appears. The short channel effect is known to adversely affect the operation characteristics of the device. For example, when the channel length decreases so that the source region and the drain region are too close, the switching function by the gate may be lost. Therefore, various methods have been applied for suppressing short channel effects while maintaining the density of devices, and continuous research is being conducted.
One of the methods for suppressing the short channel effect is to form source / drain regions into shallow junctions with very shallow depths. However, when the source / drain regions are formed by the shallow junction under the same dose condition, the overall concentration is lowered, resulting in a problem that the on-operation characteristics of the device, in particular, the amount of on-current is reduced. Therefore, in order to form the source / drain regions of the shallow junction, the injection energy must be small while the dose amount must be high.
1 is a graph showing the concentration distribution according to the depth of the source / drain region formed under such a low injection energy and a high dose condition. As shown in FIG. 1, when ion implantation is performed at a low implantation energy and a high dose condition to form a shallow junction to form a source / drain region, the concentration is the highest at the vicinity of the surface, and the depth increases as the depth is increased. Indicating concentration profile 110 is reduced. However, in this case, there is a problem in that the depth decreases as the depth increases, that is, the concentration gradient sharply appears. If the concentration gradient is steep, the intensity of the electric field is increased, resulting in low breakdown voltage between the source region and the drain region, or between the source / drain region and the semiconductor substrate, resulting in poor device reliability.
An object of the present invention is to provide a method of manufacturing a transistor capable of forming a source / drain region of a shallow junction without deterioration of breakdown voltage characteristics.
According to an embodiment of the present invention, a method of manufacturing a transistor includes: forming a gate stack on a semiconductor substrate, and applying a relatively high first injection energy and a relatively low first dose to a semiconductor substrate exposed by the gate stack. Performing ion implantation, and performing second ion implantation for the source / drain region on the exposed portion of the semiconductor substrate on which the first ion implantation is performed, with an implantation energy lower than the first implantation energy and a dose higher than the first dose And performing heat treatment on the semiconductor substrate on which the first ion implantation and the second ion implantation are performed.
In one example, the first ion implantation and the second ion implantation may be performed using a beam line implantation method.
The first ion implantation by the beam line implantation method may be performed by implanting the dopant B under an implantation energy of 15 KeV to 30 KeV and a dose condition of 1.0e13 to 1.0e14 atoms / cm 2.
The first ion implantation by the beam line implantation method may be performed by implanting dopant BF2 under implantation energy of 65 KeV to 130 KeV and a dose condition of 1.0e12 to 1.0e13 atoms / cm 2.
The first ion implantation by the beam line implantation method may be performed by implanting the dopant P under an implantation energy of 30 KeV to 50 KeV and a dose condition of 1.0e13 to 1.0e14 atoms / cm 2.
The first ion implantation by the beam line implantation method may be performed by implanting the dopant As under an implantation energy of 70 KeV to 90 KeV and a dose condition of 1.0e12 to 1.0e13 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting the dopant BF under an implantation energy of 5 KeV to 10 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting the dopant BF2 under the implantation energy of 7KeV to 20KeV and the dose conditions of 1.0e15 to 1.0e16 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting the dopant P under an implantation energy of 3 KeV to 10 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting dopant As under implantation energy of 5KeV to 20KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
In one example, the second ion implantation may be performed using a plasma doping method or a cluster ion beam implantation method.
The second ion implantation using the plasma doping method may be performed by implanting the dopant B2H6 under an implantation energy of 3 KeV to 10 KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2.
The second ion implantation using the plasma doping method may be performed by implanting the dopant BF3 under a dosing condition of 5KeV to 15KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2.
The second ion implantation by the cluster ion beam implantation method may be performed by implanting dopant B18H22 under a dosing condition of 20KeV to 50KeV and 1.0e15 to 1.0e16 atoms / cm 2.
In one example, the heat treatment may be performed for 15 seconds to 30 seconds at a temperature of 900 to 1100 ℃ by a rapid heat treatment method using a lamp.
In one example, the heat treatment may be performed for 1 second to 30 seconds at a temperature of 1000 to 1150 ℃ by a rapid heat treatment method using a heat block.
In another embodiment of the present invention, a transistor manufacturing method includes forming a first gate stack and a second gate stack in a first region and a second region of a semiconductor substrate, and exposing a first mask layer pattern. And implanting p-type impurity ions at a relatively high first implantation energy and a relatively low first dose to the semiconductor substrate of the first region exposed by the first mask film pattern and the first gate stack. Performing a first ion implantation, and performing a second ion implantation for the p-type source / drain region on the exposed portion of the semiconductor substrate on which the first ion implantation is performed, the implantation energy lower than the first implantation energy and the higher than the first dose Implanting p-type impurity ions into the dose, removing the first mask pattern, forming a second mask pattern exposing the second region, and forming a second mask layer Performing a third ion implantation for implanting n-type impurity ions at a relatively high second implantation energy and a relatively low second dose to the semiconductor substrate in the second region exposed by the turn and the second gate stack; The fourth ion implantation for the n-type source / drain region is performed by implanting n-type impurity ions with an implantation energy lower than the second implantation energy and a dose higher than the second dose to the exposed portion of the semiconductor substrate on which the third ion implantation is performed. And removing the second mask layer pattern, and performing heat treatment on the semiconductor substrate on which the first to fourth ion implantations have been performed.
In one example, the first to fourth ion implantation may be performed using a beam line implantation method.
The first ion implantation by the beam line implantation method may be performed by implanting the dopant B under an implantation energy of 15 KeV to 30 KeV and a dose condition of 1.0e13 to 1.0e14 atoms / cm 2.
The first ion implantation by the beam line implantation method may be performed by implanting the dopant BF2 under a implantation energy of 65 KeV to 130 KeV and a dose condition of 1.0e12 to 1.0e13 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting the dopant BF under an implantation energy of 5 KeV to 10 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
The second ion implantation by the beam line implantation method may be performed by implanting the dopant BF2 under the implantation energy of 7KeV to 20KeV and the dose conditions of 1.0e15 to 1.0e16 atoms / cm 2.
The third ion implantation by the beam line implantation method may be performed by implanting the dopant P under an implantation energy of 30 KeV to 50 KeV and a dose condition of 1.0e13 to 1.0e14 atoms / cm 2.
The third ion implantation by the beam line implantation method may be performed by implanting the dopant As under an implantation energy of 70 KeV to 90 KeV and a dose condition of 1.0e12 to 1.0e13 atoms / cm 2.
The fourth ion implantation by the beam line implantation method may be performed by implanting the dopant P under an implantation energy of 3 KeV to 10 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
The fourth ion implantation by the beam line implantation method may be performed by implanting dopant As under implantation energy of 5 KeV to 20 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
In one example, the second ion implantation may be performed using a plasma doping method or a cluster ion beam implantation method.
The second ion implantation using the plasma doping method may be performed by implanting the dopant B2H6 under an implantation energy of 3 KeV to 10 KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2.
The second ion implantation using the plasma doping method may be performed by implanting the dopant BF3 under a dosing condition of 5KeV to 15KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2.
The second ion implantation by the cluster ion beam implantation method may be performed by implanting the dopant B18H22 under the implantation energy of 20 KeV to 50 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2.
In one example, the heat treatment may be performed for 15 seconds to 30 seconds at a temperature of 900 to 1100 ℃ by a rapid heat treatment method using a lamp.
In one example, the heat treatment may be performed for 1 second to 30 seconds at a temperature of 1000 to 1150 ℃ by a rapid heat treatment method using a heat block.
According to the present invention, the concentration gradient can be smoothed by performing ion implantation with relatively high implantation energy and low dose before ion implantation for forming source / drain regions, thereby degrading breakdown characteristics due to rapid concentration gradient. The advantage is that it can be suppressed.
2 to 6 are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.
Referring to FIG. 2, a first gate stack 310 and a
Next, a first
Next, as indicated by arrows in the drawing, the p-type impurity ions are formed on the
The first ion implantation may be performed using a conventional ion implantation apparatus, that is, using a beam line implantation method. In this case, boron (B) is used as the p-
Referring to FIG. 3, after the first ion implantation is performed, as shown by an arrow in the figure, a second ion implantation for forming a p-type source / drain region is performed. The second ion implantation is performed at a lower implantation energy than the first implantation energy and a higher dose condition than the first dose. As the second ion implantation is performed at a relatively low implantation energy and a relatively high dose condition, the peak concentration and the concentration at the tail portion are not affected by the second ion implantation. Is maintained. The second ion implantation may be performed using a beam line implantation method, a plasma doping method, or a cluster ion beam implantation method. As the p-
When using the beam line injection method, BF or BF2 may be used as a source for forming the beam line. When using BF as a source for forming a beam line, the second ion implantation is performed by implanting dopant BF under an implantation energy of 5KeV to 10KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2. When BF2 is used as a source for forming the beam line, the second ion implantation is performed under an implantation energy of 7KeV to 20KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2. When using the plasma doping method, B2H6 or BF3 may be used as a source for plasma formation. When B2H6 is used as a source for plasma formation, the second ion implantation is performed under an implantation energy of 3KeV to 10KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2. When BF3 is used as a source for plasma formation, the second ion implantation is performed at an implantation energy of 5 KeV to 15 KeV and a dose condition of 1.0e16 to 1.0e17 atoms / cm 2. In the case of using the cluster ion beam implantation method, B18H22 is used as a source for forming the cluster ion beam, in which case the second ion implantation is performed under an implantation energy of 20KeV to 50KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2. .
Referring to FIG. 4, after implanting the p-
The third ion implantation may be performed using a beam line implantation method. In this case, as the n-
Referring to FIG. 5, after the third ion implantation is performed, as shown by the arrow in FIG. 5, the fourth ion implantation for forming the n-type source / drain region is performed. The fourth ion implantation is performed by using a beam line implantation method with a implantation energy lower than the second implantation energy during the third ion implantation and a dose condition higher than the second dose. As such, as the fourth ion implantation is performed at a relatively low implantation energy and a relatively high dose condition, the peak concentration and the concentration at the tail portion are not affected by the fourth ion implantation. Is maintained. The n-type impurity implanted by the fourth ion implantation may use a temperature phosphor (P) or an asnic (As). In the case of using the phosphorus (P), the fourth ion implantation is performed under an implantation energy of 3 KeV to 10 KeV and a dose condition of 1.0e15 to 1.0e16 atoms / cm 2. When using Asonic (As), the fourth ion implantation is performed under the implantation energy of 5KeV to 20KeV and the dose conditions of 1.0e15 to 1.0e16 atoms / cm 2.
Referring to FIG. 6, after implanting n-type impurity ions (431 in FIG. 5) into the source / drain regions of the
Figure 7 is a graph shown for comparing the concentration profile of the source / drain region formed in accordance with the present invention compared with the conventional case.
As shown in FIG. 7, when ion implantation for reducing concentration gradient, ie, first ion implantation or third ion implantation, is performed (620) according to the present invention, ions for forming source / drain regions as in the conventional case. It was found that the concentration gradient according to the depth was alleviated as compared with the case where implantation, ie, only the second ion implantation or the fourth ion implantation was performed (610), and thus, in the present invention, degradation of the breakdown characteristic of the device can be prevented. Can be.
1 is a graph showing a concentration profile of a source / drain region formed by a conventional transistor manufacturing method.
2 to 6 are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.
7 is a graph showing the concentration profile of the source / drain regions formed by the transistor manufacturing method according to the present invention in comparison with the conventional case.
Claims (32)
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KR1020090053080A KR20100134455A (en) | 2009-06-15 | 2009-06-15 | Method of fabricating transistor for improving breakdown characteristics |
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KR1020090053080A KR20100134455A (en) | 2009-06-15 | 2009-06-15 | Method of fabricating transistor for improving breakdown characteristics |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9613811B2 (en) | 2013-12-06 | 2017-04-04 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9613811B2 (en) | 2013-12-06 | 2017-04-04 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
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