KR20100133725A - Organic light emitting diode display and fabricating method of thereof - Google Patents

Abstract

PURPOSE: An organic light emitting diode display device is provided to supply a driving voltage from the outside to the transparent electrode of each pixel by contacting an assistant wire to the transparent electrode of each pixel. CONSTITUTION: A pixel array includes a plurality of pixel rows and columns. An organic light emitting diode is formed in the pixel. A plurality of auxiliary wirings(104) crosses the pixel rows or the pixel rows. A first insulation layer is contacted with the auxiliary wiring under the auxiliary wiring. The first insulation layer comprises a groove formed in a part corresponding to the auxiliary wiring. A common wiring mutually supplies a driving voltage to the auxiliary wirings. The transparent electrode(124) of the organic light emitting diode is directly contacted with the auxiliary wiring through a contact hole passing through at least one second insulation layer. The organic compound layer(122) of the organic light emitting diode is located in the groove.

Description

Organic light emitting diode display device and manufacturing method thereof {ORGANIC LIGHT EMITTING DIODE DISPLAY AND FABRICATING METHOD OF THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display device that emits light in a top emission method, and more particularly, to an organic light emitting diode display device and a method of manufacturing the same, which can prevent luminance unevenness in a display panel by reducing resistance of a transparent electrode.

An active matrix type organic light emitting diode display (AMOLED) is a thin film transistor ("TFT") using an organic light emitting diode device ("OLED"). An image is displayed by controlling the flowing current. The organic light emitting diode display displays an image in a form of a top emission method or a bottom emission method according to the structure of an OLED including an anode electrode, a cathode electrode, and an organic compound layer. While the bottom emission method displays visible light generated in the organic compound layer toward the lower side of the substrate on which the TFT is formed, the top emission method displays visible light generated in the organic compound layer toward the upper part of the substrate on which the TFT is formed.

A top emission organic light emitting diode display device includes a display panel including a pixel array including a plurality of pixels P and a common wiring 12 for supplying driving voltages to the pixels P in common, as shown in FIG. 1. Has The pixels P are formed at the intersections of the data lines and the gate lines in the effective display area EA of the display panel, and include OLEDs formed of reflective electrodes, organic compound layers 15, and transparent electrodes 16, respectively. The reflective electrode is patterned in units of pixels P, and the organic compound layer 15 and the transparent electrode 16 are formed on the entire display panel without patterning. The common wiring 12 is formed in the non-display area SA outside the effective display area EA, and is electrically contacted with the OLED through contact holes CTH penetrating through the insulating layers 13 and 14 to make the OLED transparent. The high potential driving voltage or the low potential driving voltage is supplied to the electrode 16. In FIG. 1, reference numeral 10 denotes a substrate, and reference numeral 11 denotes a gate insulating film.

However, such a conventional organic light emitting diode display has the following problems.

The surface resistance of the transparent electrode 16 is very large. As a result, in the conventional organic light emitting diode display device in which the common wiring 12 is formed only at the outer portion of the pixel array, the driving voltage applied to the pixel P according to the separation distance between the common wiring 12 and the pixel P is determined. The size is changed to cause a luminance non-uniformity between the pixels (P). In particular, the electrical resistance of the transparent electrode 16 is further increased when the organic compound layer 15 is positioned between the common wiring 12 and the transparent electrode 16 during electrical connection through the contact hole CTH as shown in FIG. 1. do. This is because the reverse bias is applied to the OLED when the driving voltage applied to the common wiring 12 is transferred to the transparent electrode 16 through the organic compound layer 15. This increased resistance not only reduces the overall brightness of the display panel but also deepens the brightness unevenness between the pixels P.

On the other hand, the organic compound layer 15 is positioned between the common wiring 12 and the transparent electrode 16 to reduce the increase in resistance of the transparent electrode 16 near the electrical contact between the common wiring 12 and the transparent electrode 16. It has been proposed to prevent this from happening. However, in order to prevent the organic compound layer 15 from being deposited near the non-display area SA where the common wiring 12 and the transparent electrode 16 are in contact with each other, the organic compound layer 15 is formed as shown in FIG. 2. Since the area around the non-display area SA needs to be covered every time using the shadow mask 20, there is a problem of increasing the process steps and manufacturing costs.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device and a method of manufacturing the same in a top emission type organic light emitting diode display device which can prevent a luminance unevenness in a display panel by reducing the resistance of the transparent electrode. have.

In order to achieve the above object, an organic light emitting diode display according to an embodiment of the present invention comprises a pixel array including a plurality of pixel rows and pixel columns, each organic light emitting diode is formed in each pixel; A plurality of auxiliary wires traversing the pixel rows or pixel columns, respectively; A first insulating layer in contact with the auxiliary wiring under the auxiliary wiring and having a groove formed in a portion corresponding to the auxiliary wiring; And common wirings for supplying a driving voltage to the auxiliary wirings in common; A transparent electrode of the organic light emitting diode that transmits display light is in direct contact with the auxiliary line through a contact hole corresponding to the groove and penetrating through at least one second insulating layer; The organic compound layer of the organic light emitting diode is located in the groove.

The transparent electrodes are in contact with both side surfaces of the auxiliary line formed by an etching process.

The width between both sides of the auxiliary line is larger than the diameter of the contact hole.

The auxiliary wiring includes a single metal layer or multiple metal layers.

The etching ratio of the uppermost metal layer of the multiple metal layers is smaller than that of the lower metal layer.

The depth of the groove is 500 kPa or more within a range not exceeding the total thickness of the first insulating layer.

In addition, according to an embodiment of the present invention, a method of manufacturing an organic light emitting diode display device having a pixel array including a plurality of pixel rows and pixel columns, in which an organic light emitting diode is formed for each pixel, may include forming a first insulating layer. Making; Forming a plurality of auxiliary wires across the pixel rows or pixel columns, the plurality of auxiliary wires being commonly supplied with a driving voltage through a common wire, on the first insulating layer; Forming at least one second insulating layer on the auxiliary wirings; Exposing a portion of the auxiliary line through a contact hole penetrating the second insulating layer; The exposed auxiliary wiring is etched to form an undercut structure in the region corresponding to the contact hole, and the first insulating layer is etched to form a groove in the first insulating layer corresponding to the contact hole. Forming; And sequentially depositing the organic compound layer and the transparent electrode of the organic light emitting diode to form the organic compound layer in the groove, and directly contacting the transparent electrode to the auxiliary line.

An organic light emitting diode display and a method of manufacturing the same according to the present invention form auxiliary wirings to cross pixel rows (or pixel columns), respectively, and drive them from the outside by bringing the auxiliary wirings into point contact with the transparent electrodes of each pixel. Voltage is supplied to the transparent electrode of each pixel. Accordingly, the present invention can greatly alleviate occurrence of uneven luminance by position in the display panel.

Furthermore, in the present invention, during the electrical connection between the auxiliary lines and the transparent electrode, the auxiliary lines are etched to form an undercut structure, and then the organic compound layer and the transparent electrode are continuously deposited. Accordingly, since the transparent electrode is directly side-contacted to the auxiliary wiring so that the electrical contact resistance of the transparent electrode is greatly reduced to 10 dB or less per unit pixel, the present invention can of course increase the overall brightness of the display panel. Star luminance non-uniformity can be alleviated more greatly.

Furthermore, the present invention additionally forms grooves in the buffer layer or the gate insulating layer under the auxiliary wiring when the undercut structure is formed, so that the organic compound layer is reliably isolated from the auxiliary wiring, and the deposition gas stays in the transparent electrode deposition process. It is possible to improve the deposition efficiency of the transparent electrode on the exposed side of the auxiliary wiring by securing a wide exposure space.

Furthermore, the present invention can simplify the overall etching process when forming the undercut structure by selecting the auxiliary wiring as a material reacting to dry etching.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 20B.

<First Embodiment>

3 to 12b are related to an organic light emitting diode display and a method of manufacturing the same according to a first embodiment of the present invention.

3 to 8, an organic light emitting diode display according to a first exemplary embodiment of the present invention includes a pixel array including a plurality of pixel P rows, and a plurality of auxiliary crossings across the pixel P rows, respectively. The display panel includes the wirings 104 and the common wiring 150 for supplying a driving voltage to the auxiliary wirings 104 in common. The organic light emitting diode display includes a gate pad (not shown) connected to the gate line GL and a data pad (not shown) connected to the data line.

The pixels P are formed at the intersections of the data line DL and the gate line GL in the effective display area EA of the display panel, respectively, and the buffer layer 101, the switch TFT SWTFT, and the driving TFT DRTFT, respectively. ), A storage capacitor Cst, an overcoat layer 116, a bank pattern 120, and an OLED. The OLED consists of a transparent electrode 124 in contact with the auxiliary wiring 104, a reflective electrode 118 connected to the driving TFT (DRTFT), and an organic compound layer 122 positioned between them 124, 118. The reflective electrode 118 is patterned in pixel P units, and the organic compound layer 122 and the transparent electrode 124 except for the light emitting layer are formed on the entire display panel without patterning. The emission layer is patterned in units of pixels P of red, green, and blue.

The common wiring 150 is formed in the non-display area SA outside the effective display area EA, and the high potential driving voltage VDD or the low potential driving voltage VSS is applied from the outside according to the OLED connection structure. Is supplied to the auxiliary wirings 104. In the structure of a normal OLED (hereinafter referred to as "NOD") in which the anode electrode functions as the reflective electrode 118 and the cathode electrode functions as the transparent electrode 124 as shown in FIG. 7, the common wiring 150 is applied from the outside. The low potential driving voltage VSS is supplied to the auxiliary lines 104. On the other hand, in the Inverted OLED (hereinafter, referred to as "IOD") structure in which the cathode electrode functions as the reflective electrode 118 and the anode electrode functions as the transparent electrode 124, as shown in FIG. The high potential driving voltage VDD applied from the outside is supplied to the auxiliary lines 104. In FIG. 7, the reflective electrode 118 may include at least one transparent dielectric layer and a metal layer located below or between the dielectric layers, and the transparent electrode 124 may increase transmittance without increasing surface resistance. To the dielectric layer (s) and one or two layers of metal. In FIG. 8, the reflective electrode 118 may comprise a single layer or multiple layers comprising a metal or metal alloy, and the transparent electrode 124 may include dielectric layer (s) to increase transmittance without increasing surface resistance. It may include one or two metal layers.

The auxiliary lines 104 are formed in a direction parallel to the gate line GL to cross the rows of the pixels P, respectively, so that the driving voltage VDD or VSS from the common line 150 is transparent to each pixel P. Supply to electrode 124. The auxiliary wires 104 are in point-to-point contact with the transparent electrode 124 of each pixel P through the transparent electrode contact hole CTH3 formed for each pixel P, thereby providing luminance for each position in the display panel. It greatly reduces the occurrence of non-uniformity. In addition, the auxiliary wirings 104 may have a transparent electrode 124 through an undercut structure as shown in FIG. 5 to reduce electrical contact resistance of the transparent electrode 124 during electrical connection through the transparent electrode contact hole CTH3. And are directly side contacted. As a result, the overall luminance of the display panel is increased, and the luminance nonuniformity for each position is alleviated even more.

The undercut structure forms a transparent electrode contact hole CTH3 penetrating the passivation layer 114 and the gate insulating layer 106 through a photolithograph and dry etching process, and a transparent electrode contact hole. It is obtained by wet etching a part of the auxiliary wiring 104 exposed through CTH3 and dry etching the buffer layer 101 under the auxiliary wiring 104 exposed by the wet etching. The wet etching of the auxiliary wiring 104 is performed until the width D2 between the exposed sides of the auxiliary wiring 104 becomes larger than the diameter D1 of the transparent electrode contact hole CTH3. ) Until it is secured (overetching). In general, the organic compound layer 122 tends to be deposited only in the vertical direction, not in the horizontal direction. Using this, it is preferable to adjust the degree of overetching to such an extent that the organic compound layer 222 is not deposited on the exposed side surfaces of the auxiliary line 204. On the other hand, the transparent electrode 124 is easily deposited on the exposed side surfaces of the auxiliary line 104 because the deposition rate is good not only in the vertical direction but also in the horizontal direction. However, when forming the auxiliary wiring 104 as a single metal layer such as AlNd, Al, Ti, Mo, W, etc. as shown in FIG. have. In this case, as shown in FIG. 6, when the step coverage is secured in duplicate by using the auxiliary line 104 formed of the double metal layers having different etching ratios, the decrease in the deposition rate may be solved. To this end, in the double metal layer, the etching ratio of the upper metal layer 104b is preferably smaller than the etching ratio of the lower metal layer 104a. Since the upper metal layer 104b having a relatively small etching ratio is less etched than the lower metal layer 104a, the upper metal layer 104b functions to facilitate deposition of the transparent electrode 124. Since it is etched much compared to 104b), the organic compound layer 122 functions to reliably block the possibility that the organic compound layer 122 is deposited on the exposed side surfaces of the auxiliary line 104. As a result, when the auxiliary wiring 104 is formed of a double metal layer having different etching ratios, the deposition margin of the transparent electrode 124 is improved, so that the yield is improved, and the etching time can be easily adjusted, thereby increasing process convenience. . As the double metal layer, Ti / AlTi, Cu / MoTi, Mo / AlNd, or the like may be used. Meanwhile, the auxiliary line 104 may be formed of a metal triple layer of MoTi / Cu / MoTi, ITO / Cu / MoTi, and the like having different etching ratios.

The etching depth D3 with respect to the buffer layer 101 is a depth capable of reliably separating the organic compound layer 122 to be deposited on the etched portion from the auxiliary line 104, for example, the total thickness of the buffer layer 101. It is preferable to set it as 500 Hz or more within the range which does not exceed. When grooves are formed in the buffer layer 101 under the auxiliary wiring 104, the exposure space S in which the deposition gas can stay in the transparent electrode 124 deposition process is widened, and the auxiliary wiring 104 is formed. The deposition efficiency of the transparent electrode 124 with respect to the exposed sides of is increased.

Meanwhile, when the passivation layer 114, the gate insulation layer 106, the auxiliary line 104, and the buffer layer 101 are sequentially dry, wet, and dry etched as described above, the entire etching process may be complicated. Accordingly, the present invention can form the auxiliary wiring 104 as a metal layer capable of dry etching, such as Mo. In this case, since the etching targets 114, 106, 104, and 101 are etched at once through one dry etching process, the overall etching process may be much simplified.

Looking at the structure of the pixel (P) having the above configuration in detail as follows.

The buffer layer 101 is positioned on the substrate 100 by using an organic insulating material such as polyimide, photoacrylic, or an inorganic insulating material such as SiNx or SiO ₂ , so that the auxiliary wiring 104 and the substrate ( By securing the space between the 100, it contributes to improve the deposition efficiency during the deposition of the transparent electrode 124 as described above.

The gate line GL is connected to the gate driver through the gate pad, and supplies the scan pulse from the gate driver to the gate electrode of the switch TFT (SWTFT). The data line DL is connected to the data driver through the data pad, and supplies data from the data driver to the switch TFT (SWTFT).

The source electrode of the switch TFT SWTFT is connected to the data line DL, and the drain electrode of the switch TFT SWTFT contacts the gate electrode 102 of the driving TFT DRTFT through the first contact hole CTH1. . The gate electrode of the switch TFT (SWTFT) is connected to a gate line GL to which scan pulses are sequentially supplied. The switch TFT SWTFT is turned on in response to the scan pulse from the gate line GL, thereby supplying data from the data line DL to the gate electrode 102 of the driving TFT DRTFT. The switch TFT may be implemented with an N type MOSFET or a P type MOSFET.

The source electrode 110 of the driving TFT (DRTFT) is connected to the reflective electrode 118 of the OLED through the second contact hole CTH2, and the drain electrode 112 of the driving TFT (DRTFT) is connected to the auxiliary line 104. It is connected to a driving power source for generating a driving voltage opposite to the supplied driving voltage. For example, as can be clearly seen in FIGS. 7 and 8, the drain electrode 112 of the driving TFT (DRTFT) is connected to a high potential voltage source when the low potential driving voltage VSS is supplied to the auxiliary line 104. In contrast, when the high potential driving voltage VDD is supplied to the auxiliary wiring 104, the auxiliary wiring 104 is connected to the low potential voltage source. The gate electrode 102 of the driving TFT (DRTFT) is connected to the drain electrode of the switch TFT (SWTFT). The driving TFT DRTFT adjusts the amount of current flowing through the OLED based on data applied to its gate electrode 102 through the switch TFT SWTFT. The driving TFT may be implemented as an N type MOSFET or a P type MOSFET.

The passivation layer 114 is positioned on the TFTs (SWTFT, DRTFT) with an organic insulating material such as polyimide, photoacrylic, or an inorganic insulating material such as SiNx, SiO _2, and the TFTs from the external environment. Protect (SWTFT, DRTFT). In some cases, the passivation layer 114 may be omitted in the top gate structure in which the gate electrode is located on the source / drain electrode.

The storage capacitor Cst keeps the voltage difference between the gate electrode 102 and the source electrode 110 of the driving TFT DRTFT constant for one frame.

The overcoat layer 116 is positioned on the passivation layer 114 with an organic insulating material such as polyimide or photoacrylic to remove the step due to the TFTs (SWTFT, DRTFT). A portion of the source electrode 110 is exposed through the second contact hole CTH2 passing through the overcoat layer 116 and the passivation layer 114 in the driving TFT (DRTFT). In order to shield out-gassing from the overcoat layer 116 which is an organic film, a buffer layer (not shown) may be further interposed between the overcoat layer 116 and the reflective electrode 118.

The reflective electrode 118 serves as a lower electrode of the OLED and is positioned on the overcoat layer 116 and is in contact with the source electrode 110 of the exposed driving TFT (DRTFT). In the NOD structure of FIG. 7, the reflective electrode 118 may include at least one transparent dielectric layer including an oxide such as ITO or IZO, and a metal layer of Al, Ag, AlNd, etc. having high reflectance and opacity. On the other hand, in the IOD structure as shown in FIG. 8, the reflective electrode 118 may include a metal layer of Al, Ag, AlNd or the like having high reflectance and opacity.

The bank pattern 120 is positioned on the substrate 100 on which the reflective electrode 118 is formed to partition the opening area and the non-open area of the pixel P.

The organic compound layer 122 includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (Electron). Including an injection layer (EIL), it is positioned on the reflective electrode 118 and the bank pattern 120.

The transparent electrode 124 serves as an upper electrode of the OLED that transmits display light and is positioned on the organic compound layer 122 and may include a dielectric layer (s) and one or two metal layers. In the NOD structure of FIG. 7 and the IOD structure of FIG. 8, the transparent electrode 124 may be formed of a dielectric layer, a metal layer / dielectric layer, a dielectric layer / metal layer / dielectric layer, or the like. Here, the dielectric layer may be any one of ITO, IZO, WO _{3 and} AZO, and the metal layer may be any one of Ag, Al, Mg, and Mg: ag. Thus, when the transparent electrode 124 is formed in multiple layers, the surface resistance of the transparent electrode is somewhat reduced.

When the driving voltage is applied to the reflective electrode 118 and the transparent electrode 124 in the organic light emitting diode display having the above structure, electrons passing through the hole transport layer (HTL) and electron transport layer (ETL) It is moved to the emission layer EML to form excitons, and as a result, the gradation is realized by the emission layer EML generating visible light.

The organic light emitting diode display according to the first exemplary embodiment of the present invention is manufactured through a TFT process and an OLED process as shown in FIGS. 9A to 12B.

9A and 9B, an inorganic insulating material such as SiO ₂ , SiNx, or an organic insulating material such as polyimide and photoacrylic may be formed on a substrate 100 made of transparent glass or plastic material. The buffer layer 101 is formed by full deposition through this CVD process. Subsequently, any one metal among Al, AlNd, Mo Ti, and W or two or more metals or alloys (Ti / AlTi, Cu / MoTi, Mo / AlNd, MoTi / Cu /) is formed on the substrate 100 on which the buffer layer 101 is formed. Gate metals selected from MoTi, ITO / Cu / MoTi) are deposited by a sputtering process. Gate metals are patterned through photolithography and wet etching processes. As a result, the substrate 100 includes a gate electrode of the switch TFT (SWTFT), a gate electrode 102 of the driving TFT DTFT, a gate line GL connected to the gate electrode 102, an auxiliary line 104, and the like. A gate metal pattern is formed.

10A and 10B, an inorganic insulating material such as SiO ₂ or SiNx and a semiconductor material such as amorphous silicon or polysilicon may be formed on a substrate 100 on which a gate metal pattern is formed by a chemical vapor deposition (CVD) process or the like. Continuous deposition. Subsequently, the semiconductor layer of the remaining portion except for the necessary portion is removed through the photolithography process and the dry etching process. As a result, the gate insulating layer 106 covering the gate electrode of the switch TFT (SWTFT) and the first active pattern formed thereon, the gate insulating layer 106 covering the gate electrode 102 of the driving TFT (DRTFT) and thereon The formed second active pattern 108 is formed on the substrate 100.

On the substrate 100 on which the gate insulating layer 106 and the active patterns are formed, a data metal having a single layer or a double layer structure of a metal such as Al, Mo, Cr, Cu, Al alloy, Mo alloy, Cu alloy is sputtered on the front surface. After deposition, it is patterned through a photolithography process and a wet etching process. As a result, a data metal pattern including a source electrode and a drain electrode of the switch TFT (SWTFT), a source electrode 110 of the driving TFT (DRTFT), a drain electrode 112, and the like are formed on the substrate 100, respectively.

11A and 11B, an inorganic insulating material such as SiO ₂ , SiNx, or an organic insulating material such as polyimide, photoacrylic, or the like is deposited on the substrate 100 on which the data metal pattern is formed. After full deposition through the photolithography process and the dry etching process, the inorganic / organic insulating material (or with the gate insulating layer 106) is partially removed. As a result, the first contact hole CTH1 exposing a part of the drain electrode of the switch TFT SWTFT, the second contact hole CTH2 exposing a part of the source electrode 110 of the driving TFT DRTFT, and the auxiliary wiring ( A passivation layer 114 having a transparent electrode contact hole CTH3 exposing the 104 and a portion of the buffer layer 101 is formed.

A portion of the auxiliary line 104 exposed through the transparent electrode contact hole CTH3 and the buffer layer 101 thereunder are sequentially wet-etched and dry-etched or dry-etched at the same time to form an undercut structure. Wet etching uses a mixed acid of phosphoric acid, nitric acid, acetic acid in the case of the auxiliary wiring 104 including a material capable of etching the auxiliary wiring 104, for example, AlNd, Mo, Al, and the like, and the auxiliary including Cu, MoTi, and the like. In the case of the wiring 104, a mixture of fruit tree and hydrofluoric acid is used. In the case of the auxiliary wiring 104 including Ti and W, a mixture of hydrofluoric acid and oxane is used. In the case of the auxiliary wiring 104 including ITO, oxalic acid is used. Until the step coverage is secured (overetching). Dry etching is performed until a step coverage is secured using a material capable of simultaneously etching the auxiliary wiring 104 and the buffer layer 101 including Mo and the like, such as SF6 (overetching).

After the organic insulating material such as polyimide or photoacrylic is entirely deposited on the substrate 100 on which the auxiliary wiring 104 and the buffer layer 101 are etched, the photolithography process and The dry etching process partially removes the organic insulating material. As a result, the overcoat layer 116 is formed to be opened in the vicinity of the first and second contact holes CTH1 and CTH2 and the transparent electrode contact hole CTH3.

The lower electrode layer (s) is deposited on the substrate 100 on which the overcoat layer 116 is formed by a sputtering method. Subsequently, the lower electrode layer (s) are patterned through a photolithography process and an etching process to form the reflective electrode 118. The reflective electrode 118 is in contact with the source electrode 110 of the driving TFT DRTFT through the second contact hole CTH2.

12A and 12B, an organic insulating material such as polyimide or photoacrylic is deposited on the substrate 100 on which the reflective electrode 118 is formed through a CVD process, and then photo The organic insulating material is partially removed through the lithography process and the dry etching process. As a result, a bank pattern 120 is formed in the pixel P to divide the open area and the non-open area.

The electron injection layer material, the electron transport layer material, the light emitting layer material, the hole transport layer material, and the hole injection layer material are successively deposited on the substrate 100 on which the bank pattern 120 is formed by thermal evaporation. 122 is formed. The electron injection layer material, the electron transport layer material, the hole transport layer material, and the hole injection layer material are entirely deposited without a shadow mask. The light emitting layer material is deposited by the shadow mask in units of red, green, and blue pixels (P). Since the organic compound layer 122 tends not to be deposited in the horizontal direction but only in the vertical direction, the organic compound layer 122 is not deposited on the exposed sides of the auxiliary line 104, and the etching of the auxiliary line 104 and the buffer layer 101 is performed. It is deposited only in the direction perpendicular to the exposure space S formed by.

The transparent electrode 124 is deposited on the substrate 100 on which the organic compound layer 122 is formed by a sputtering process or a thermal deposition process. The transparent electrode 124 is easily deposited on the exposed sides of the auxiliary line 104 because the deposition rate is good not only in the vertical direction but also in the horizontal direction. In other words, the transparent electrode 124 is directly side contacted to the exposed side surfaces of the auxiliary line 104 by an undercut structure. As a result, the overall luminance of the display panel is increased, and the phenomenon of luminance unevenness for each position is greatly alleviated.

Second Embodiment

13 to 20b are related to an organic light emitting diode display and a method of manufacturing the same according to a second embodiment of the present invention.

13 through 16, an organic light emitting diode display according to a second exemplary embodiment of the present invention includes a pixel array including a plurality of pixel P columns, and a plurality of auxiliary crossings respectively crossing the pixel P columns. The display panel includes the wirings 204 and the common wiring 250 for supplying a driving voltage to the auxiliary wirings 204 in common. The organic light emitting diode display includes a gate pad (not shown) connected to the gate line GL and a data pad (not shown) connected to the data line.

The pixels P are formed at the intersections of the data line DL and the gate line GL in the effective display area EA of the display panel, and each of the switch TFT SWTFT, the driving TFT DRTFT, and the storage capacitor Cst), overcoat layer 216, bank pattern 220, and OLED. The OLED consists of a transparent electrode 224 in contact with the auxiliary wiring 204, a reflective electrode 218 connected to the driving TFT (DRTFT), and an organic compound layer 222 positioned between them 224, 218. The reflective electrode 218 is patterned in units of pixels P, and the organic compound layer 222 and the transparent electrode 224 are formed on the entire display panel without patterning.

The common wiring 250 is formed in the non-display area SA outside the effective display area EA, and the high potential driving voltage VDD or the low potential driving voltage VSS is applied from the outside according to the OLED connection structure. Is supplied to the auxiliary wirings 204. In the NOD structure in which the anode electrode functions as the reflective electrode 218 and the cathode electrode functions as the transparent electrode 224, as shown in FIG. 7, the common wiring 250 supports the low potential driving voltage VSS applied from the outside. To 204. On the other hand, in the IOD structure in which the cathode electrode functions as the reflective electrode 218 and the anode electrode functions as the transparent electrode 224, as shown in FIG. 8, the common wiring 250 receives the high potential driving voltage VDD applied from the outside. The auxiliary wires 204 are supplied. In FIG. 7, the reflective electrode 218 may include at least one or more transparent dielectric layers and a metal layer located below or between the dielectric layers, and the transparent electrode 224 may increase transmittance without increasing surface resistance. To the dielectric layer (s) and one or two layers of metal. In FIG. 8, the reflective electrode 218 may comprise a single layer or multiple layers comprising a metal or metal alloy, and the transparent electrode 224 may be provided with dielectric layer (s) to increase transmittance without increasing surface resistance. It may include one or two metal layers.

The auxiliary lines 204 are formed in a direction parallel to the data line DL to cross the columns of the pixels P, respectively, so that the driving voltage VDD or VSS from the common line 250 is transparent to each pixel P. It is supplied to the electrode 224. The auxiliary wirings 204 are in point-to-point contact with the transparent electrode 224 of each pixel P through the transparent electrode contact hole CTH3 formed for each pixel P, thereby providing luminance for each position in the display panel. It greatly reduces the occurrence of non-uniformity. In addition, the auxiliary wirings 204 are formed by the undercut structure as shown in FIG. 15 in order to reduce the electrical contact resistance of the transparent electrode 224 during electrical connection through the transparent electrode contact hole CTH3. And are directly side contacted. As a result, the overall luminance of the display panel increases, and the phenomenon of luminance unevenness for each position is alleviated even more.

The undercut structure forms a transparent electrode contact hole CTH3 penetrating the passivation layer 214 through photolithography and a dry etching process, and a part of the auxiliary wiring 204 exposed through the transparent electrode contact hole CTH3. Is wet etched, and is obtained by dry etching the gate insulating layer 206 under the auxiliary wiring 204 exposed by the wet etch. The wet etching of the auxiliary line 204 is performed until the width D2 between the exposed side surfaces of the auxiliary line 204 becomes larger than the diameter D1 of the transparent electrode contact hole CTH3. Until coverage is secured (overetching). In general, the organic compound layer 222 tends to be deposited only in the vertical direction, not in the horizontal direction. Using this, it is preferable to adjust the degree of overetching to such an extent that the organic compound layer 222 is not deposited on the exposed side surfaces of the auxiliary line 204. On the other hand, the transparent electrode 224 is easily deposited on the exposed side surfaces of the auxiliary line 204 because the deposition rate is good not only in the vertical direction but also in the horizontal direction. However, when forming the auxiliary line 204 as a single metal layer such as AlNd, Al, Ti, Mo, W, etc. as shown in FIG. 15, when the degree of overetching is excessive, the deposition rate of the transparent electrode 224 may drop. have. In this case, as shown in FIG. 16, when the step coverage is secured in duplicate by using the auxiliary wiring 204 formed of the double metal layers having different etching ratios, the decrease in the deposition rate can be solved. To this end, in the double metal layer, the etching ratio of the upper metal layer 204b is preferably smaller than the etching ratio of the lower metal layer 204a. Since the upper metal layer 204b having a relatively small etching ratio is less etched than the lower metal layer 204a, the upper metal layer 204b serves to facilitate the deposition of the transparent electrode 224. Since it is etched much compared to 204b, the organic compound layer 222 functions to reliably block the possibility that the organic compound layer 222 is deposited on the exposed sides of the auxiliary line 204. As a result, when the auxiliary wiring 204 is formed of a double metal layer having different etching ratios, the deposition margin of the transparent electrode 224 may be improved, so that the yield may be improved, and the etching time may be easily adjusted, thereby greatly increasing the process convenience. . As the double metal layer, Ti / AlTi, Cu / MoTi, Mo / AlNd, or the like may be used. Meanwhile, the auxiliary line 204 may be formed of a metal triple layer of MoTi / Cu / MoTi, ITO / Cu / MoTi, and the like having different etching ratios.

The etching depth D3 with respect to the gate insulating layer 206 is a depth that can reliably separate the organic compound layer 222 to be deposited in the etched portion from the auxiliary wiring 104, for example, the gate insulating layer 206. It is preferable to set it as 500 kPa or more within the range which does not exceed the total thickness of. When grooves are formed in the gate insulating layer 206 under the auxiliary wiring 204, the exposure space S in which the deposition gas may stay in the transparent electrode 224 deposition process may be widened, thereby forming the auxiliary wiring ( The deposition efficiency of the transparent electrode 224 on the exposed sides of 204 is increased.

Meanwhile, when the passivation layer 214, the auxiliary line 204, and the gate insulation layer 206 are sequentially dry, wet, or dry etched as described above, the overall etching process may be complicated. Accordingly, the present invention can form the auxiliary wiring 204 as a metal layer capable of dry etching, such as Mo. In this case, the etching targets 214, 204, and 206 are etched at one time through one dry etching process, so that the entire etching process may be much more easily digested.

Looking at the structure of the pixel (P) having the above configuration in detail as follows.

The gate line GL is connected to the gate driver through the gate pad, and supplies the scan pulse from the gate driver to the gate electrode of the switch TFT (SWTFT). The data line DL is connected to the data driver through the data pad, and supplies data from the data driver to the switch TFT (SWTFT). The gate insulating layer 206 is positioned on the substrate 200 by using an inorganic insulating material such as SiO ₂ or SiNx to secure a space between the auxiliary wiring 204 and the substrate 200, thereby providing the transparent electrode 124. ) Contributes to improving its deposition efficiency.

The source electrode of the switch TFT SWTFT is connected to the data line DL, and the drain electrode of the switch TFT SWTFT contacts the gate electrode 202 of the driving TFT DRTFT through the first contact hole CTH1. . The gate electrode of the switch TFT (SWTFT) is connected to a gate line GL to which scan pulses are sequentially supplied. The switch TFT SWTFT is turned on in response to a scan pulse from the gate line GL, thereby supplying data from the data line DL to the gate electrode 202 of the driving TFT DRTFT. The switch TFT (SWTFT) may be implemented as an N type MOSFET or a P type MOSFET.

The source electrode 210 of the driving TFT (DRTFT) is connected to the reflective electrode 218 of the OLED through the second contact hole CTH2, and the drain electrode 212 of the driving TFT (DRTFT) is connected to the auxiliary line 204. It is connected to a drive power supply which generates a drive voltage opposite to that supplied. For example, as can be clearly seen in FIGS. 7 and 8, the drain electrode 212 of the driving TFT (DRTFT) is connected to a high potential voltage source when the low potential driving voltage VSS is supplied to the auxiliary line 204. In contrast, when the high potential driving voltage VDD is supplied to the auxiliary wiring 204, the auxiliary wiring 204 is connected to the low potential voltage source. The gate electrode 202 of the driving TFT (DRTFT) is connected to the drain electrode of the switch TFT (SWTFT). The driving TFT DRTFT adjusts the amount of current flowing through the OLED based on data applied to its gate electrode 202 through the switch TFT SWTFT. The driving TFT may be implemented as an N type MOSFET or a P type MOSFET.

The passivation layer 214 is positioned on the TFTs (SWTFT, DRTFT) with an organic insulating material such as polyimide, photoacrylic, or an inorganic insulating material such as SiNx, SiO _2, and the like from the external environment. Protect (SWTFT, DRTFT). The passivation layer 214 may be omitted in some cases, namely, in the top gate structure in which the gate electrode is located on the source / drain electrode.

The storage capacitor Cst keeps the voltage difference between the gate electrode 202 and the source electrode 210 of the driving TFT DRTFT constant for one frame.

The overcoat layer 216 is positioned on the passivation layer 214 with an organic insulating material such as polyimide or photoacrylic to remove the step due to the TFTs (SWTFT, DRTFT). A portion of the source electrode 210 in the driving TFT DRTFT is exposed through the second contact hole CTH2 penetrating through the overcoat layer 216 and the passivation layer 214. In order to shield out-gassing from the overcoat layer 216 which is an organic film, a buffer layer (not shown) may be further interposed between the overcoat layer 216 and the reflective electrode 218.

The reflective electrode 218 serves as a lower electrode of the OLED and is positioned on the overcoat layer 216 and is in contact with the source electrode 210 of the exposed driving TFT (DRTFT). In the NOD structure of FIG. 7, the reflective electrode 218 may include at least one transparent dielectric layer including an oxide such as ITO or IZO, and a metal layer of Al, Ag, AlNd, etc. having high reflectance and opacity. On the other hand, in the IOD structure as shown in FIG. 8, the reflective electrode 218 may include a metal layer of Al, Ag, AlNd or the like having high reflectance and opacity.

The bank pattern 220 is disposed on the substrate 200 on which the reflective electrode 218 is formed to partition the opening area and the non-open area of the pixel P.

The organic compound layer 222 includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (Electron). An injection layer (EIL) is disposed on the reflective electrode 218 and the bank pattern 220.

The transparent electrode 224 serves as an upper electrode of the OLED that transmits display light and is positioned on the organic compound layer 222 and may include a dielectric layer (s) and one or two metal layers. In the NOD structure as shown in FIG. 7 and the IOD structure as shown in FIG. 8, the transparent electrode 224 may be formed of a dielectric layer, a metal layer / dielectric layer, a dielectric layer / metal layer / dielectric layer, or the like. Here, the dielectric layer may be any one of ITO, IZO, WO _3, AZO, and the metal layer may be any one of Ag, Al, Mg, and Mg: ag. Thus, when the transparent electrode 224 is formed in multiple layers, the surface resistance of the transparent electrode is somewhat reduced.

When a driving voltage is applied to the reflective electrode 218 and the transparent electrode 224 in the organic light emitting diode display having the above structure, electrons passing through the hole transport layer HTL and electron passing through the ETL It is moved to the emission layer EML to form excitons, and as a result, the gradation is realized by the emission layer EML generating visible light.

The organic light emitting diode display according to the second exemplary embodiment of the present invention is manufactured through a TFT process and an OLED process as shown in FIGS. 17A to 20B.

17A and 17B, any one of Al, AlNd, Mo Ti, and W or two or more metals or alloys (Ti / AlTi, Cu / MoTi) on a substrate 200 made of transparent glass or plastic material , Gate metals selected from Mo / AlNd, MoTi / Cu / MoTi, ITO / Cu / MoTi) are deposited by a sputtering process. Gate metals are patterned through photolithography and wet etching processes. As a result, a gate metal pattern including a gate electrode of the switch TFT (SWTFT), a gate electrode 202 of the driving TFT DTFT, a gate line GL connected to the gate electrode 202, and the like is formed on the substrate 200. .

18A and 18B, an inorganic insulating material such as SiO ₂ or SiNx and a semiconductor material such as amorphous silicon or polysilicon may be formed on a substrate 200 on which a gate metal pattern is formed by a chemical vapor deposition (CVD) process or the like. Continuous deposition. Subsequently, the semiconductor layer of the remaining portions except for the necessary portions is removed through the photolithography process and the dry etching process. As a result, the gate insulating layer 206 covering the gate electrode of the switch TFT (SWTFT) and the first active pattern formed thereon, the gate insulating layer 206 covering the gate electrode 202 of the driving TFT (DRTFT) and thereon The formed second active pattern 208 and the like are formed on the substrate 200.

On the substrate 200 on which the gate insulating layer 206 and the active patterns are formed, a data metal having a single layer or a double layer structure of a metal such as Al, Mo, Cr, Cu, Al alloy, Mo alloy, or Cu alloy is sputtered. After deposition, it is patterned through a photolithography process and a wet etching process. As a result, the data metal pattern including the source electrode and the drain electrode of the switch TFT (SWTFT), the source electrode 210 and the drain electrode 212 of the driving TFT (DRTFT), the auxiliary wiring 204, and the like, on the substrate 200, respectively. Is formed.

19A and 19B, an inorganic insulating material such as SiO ₂ , SiNx, or an organic insulating material such as polyimide and photoacrylic may be deposited on a substrate 200 on which a data metal pattern is formed. After full deposition through the photolithography process and the dry etching process, the inorganic / organic insulating material (or along with the gate insulating layer 206) is partially removed. As a result, the first contact hole CTH1 exposing a part of the drain electrode of the switch TFT SWTFT, the second contact hole CTH2 exposing a part of the source electrode 210 of the driving TFT DRTFT, and the auxiliary wiring ( A passivation layer 214 having a transparent electrode contact hole CTH3 exposing 204 and a portion of the gate insulating layer 206 is formed.

A portion of the auxiliary line 204 exposed through the transparent electrode contact hole CTH3 and the gate insulating layer 206 thereunder are sequentially wet-etched and dry-etched or dry-etched at the same time to form an undercut structure. Wet etching uses a mixed acid of phosphoric acid, nitric acid, acetic acid in the case of the auxiliary wiring 204 including a material capable of etching the auxiliary wiring 204, for example, AlNd, Mo, Al, and the like. In the case of the wiring 204, a mixture of fruit tree and hydrofluoric acid is used. In the case of the auxiliary wiring 204 including Ti and W, a mixture of hydrofluoric acid and oxane is used. In the case of the auxiliary wiring 204 including ITO, oxalic acid is used. Until the step coverage is secured (overetching). Dry etching is performed until a step coverage is secured using a material capable of simultaneously etching the auxiliary wiring 204 including Mo, and the gate insulating layer 206, such as SF6 (overetching). ).

After the organic insulating material such as polyimide or photoacrylic is completely deposited on the substrate 200 on which the auxiliary wiring 204 and the gate insulating layer 206 are etched, the photolithography is performed. The organic insulating material is partially removed through the process and the dry etching process. As a result, the overcoat layer 216 that is opened near the first and second contact holes CTH1 and CTH2 and the transparent electrode contact hole CTH3 is formed.

The lower electrode layer (s) are deposited on the substrate 200 on which the overcoat layer 216 is formed by sputtering. Subsequently, the lower electrode layer (s) are patterned through a photolithography process and an etching process to form the reflective electrode 218. The reflective electrode 218 is in contact with the source electrode 210 of the driving TFT DRTFT through the second contact hole CTH2.

20A and 20B, an organic insulating material such as polyimide or photoacrylic is deposited on the substrate 200 on which the reflective electrode 218 is formed through a CVD process, and then photolithography. The organic insulating material is partially removed through the process and the dry etching process. As a result, a bank pattern 220 is formed which partitions the opening region and the non-opening region in the pixel P. As shown in FIG.

The electron injection layer material, the electron transport layer material, the light emitting layer material, the hole transport layer material, and the hole injection layer material are successively deposited on the substrate 200 on which the bank pattern 220 is formed by thermal evaporation. 222 is formed. The electron injection layer material, the electron transport layer material, the hole transport layer material, and the hole injection layer material are entirely deposited without a shadow mask. The light emitting layer material is deposited by the shadow mask in units of red, green, and blue pixels (P). Since the organic compound layer 222 tends not to be deposited in the horizontal direction but only in the vertical direction, the organic compound layer 222 is not deposited on the exposed sides of the auxiliary line 204 and is formed by etching the auxiliary line 204. Deposition only in the vertical direction.

The transparent electrode 224 is deposited on the substrate 200 on which the organic compound layer 222 is formed by a sputtering process or a thermal deposition process. The transparent electrode 224 is easily deposited on the exposed sides of the auxiliary line 204 because the deposition rate is good not only in the vertical direction but also in the horizontal direction. In other words, the transparent electrode 224 is directly side contacted to the exposed side surfaces of the auxiliary line 204 by an undercut structure. As a result, the overall luminance of the display panel is increased, and the phenomenon of luminance unevenness in each position is greatly alleviated.

As described above, the organic light emitting diode display and the manufacturing method thereof according to the present invention form auxiliary wirings to cross the pixel rows (or pixel columns), respectively, and the auxiliary wirings are in point contact with the transparent electrodes of each pixel. The drive voltage from the outside is supplied to the transparent electrode of each pixel. Accordingly, the present invention can greatly alleviate occurrence of uneven luminance by position in the display panel.

Furthermore, in the present invention, during the electrical connection between the auxiliary lines and the transparent electrode, the auxiliary lines are etched to form an undercut structure, and then the organic compound layer and the transparent electrode are continuously deposited. Accordingly, since the transparent electrode is directly side-contacted to the auxiliary wiring so that the electrical contact resistance of the transparent electrode is greatly reduced to 10 dB or less per unit pixel, the present invention can of course increase the overall brightness of the display panel. Star luminance non-uniformity can be alleviated more greatly.

Furthermore, the present invention additionally forms grooves in the buffer layer or the gate insulating layer under the auxiliary wiring when the undercut structure is formed, so that the organic compound layer is reliably isolated from the auxiliary wiring, and the deposition gas stays in the transparent electrode deposition process. It is possible to improve the deposition efficiency of the transparent electrode on the exposed side of the auxiliary wiring by securing a wide exposure space.

Furthermore, the present invention can simplify the overall etching process when forming the undercut structure by selecting the auxiliary wiring as a material reacting to dry etching.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view schematically showing a display panel of a conventional top emission type organic light emitting diode display.

Figure 2 shows a shadow mask to prevent the conventional organic compound layer is partially deposited.

3 is a schematic view of a display panel of an organic light emitting diode display according to a first exemplary embodiment of the present invention.

4 is a plan view specifically illustrating a pixel of FIG. 3;

FIG. 5 is a cross-sectional view of a portion taken along the line II ′ of FIG. 4; FIG.

FIG. 6 is a cross-sectional view showing another example of portion “A” of FIG. 5;

7 is a pixel equivalent circuit diagram of a NOD method.

8 is a pixel equivalent circuit diagram of an IOD method.

9A to 12B are plan and cross-sectional views illustrating a method of manufacturing an organic light emitting diode display device according to a first embodiment of the present invention.

13 is a schematic view of a display panel of an organic light emitting diode display according to a second exemplary embodiment of the present invention.

14 is a plan view specifically showing a pixel of FIG. 13;

FIG. 15 is a cross-sectional view of a portion of FIG. 14 taken along line II-II '; FIG.

FIG. 16 is a cross-sectional view showing another example of the portion “B” of FIG. 15.

17A to 20B are plan and cross-sectional views illustrating a method of manufacturing an organic light emitting diode display device according to a second exemplary embodiment of the present invention.

Claims (13)

A pixel array comprising a plurality of pixel rows and pixel columns, in which an organic light emitting diode is formed for each pixel; A plurality of auxiliary wires traversing the pixel rows or pixel columns, respectively; A first insulating layer in contact with the auxiliary wiring under the auxiliary wiring and having a groove formed in a portion corresponding to the auxiliary wiring; And A common wiring for supplying a driving voltage to the auxiliary wirings in common; A transparent electrode of the organic light emitting diode that transmits display light is in direct contact with the auxiliary line through a contact hole corresponding to the groove and penetrating through at least one second insulating layer; And an organic compound layer of the organic light emitting diode is located in the groove. The method of claim 1, And the transparent electrode is in contact with both side surfaces of the auxiliary line formed by an etching process. The method of claim 2, The width of both sides of the auxiliary wiring is larger than the diameter of the contact hole, the organic light emitting diode display device. The method of claim 1, And the auxiliary line includes a single metal layer or multiple metal layers. The method of claim 4, wherein And an etch ratio of an uppermost metal layer of the multiple metal layers is smaller than an etch ratio of a lower metal layer. The method of claim 1, And a depth of the groove is 500 를 or more within a range not exceeding the total thickness of the first insulating layer. A method of manufacturing an organic light emitting diode display device having a pixel array including a plurality of pixel rows and pixel columns, wherein an organic light emitting diode is formed for each pixel. Forming a first insulating layer; Forming a plurality of auxiliary wires across the pixel rows or pixel columns, the plurality of auxiliary wires being commonly supplied with a driving voltage through a common wire, on the first insulating layer; Forming at least one second insulating layer on the auxiliary lines; Exposing a portion of the auxiliary line through a contact hole penetrating the second insulating layer; The exposed auxiliary wiring is etched to form an undercut structure in the region corresponding to the contact hole, and the first insulating layer is etched to form a groove in the first insulating layer corresponding to the contact hole. Forming; And And depositing the organic compound layer of the organic light emitting diode and the transparent electrode sequentially to form the organic compound layer in the groove, and directly contacting the transparent electrode to the auxiliary line. Manufacturing method. The method of claim 7, wherein And the transparent electrode is in contact with both side surfaces of the auxiliary wiring formed by the under cut structure. The method of claim 8, The width of both sides of the auxiliary wiring is larger than the diameter of the contact hole, the manufacturing method of the organic light emitting diode display device. The method of claim 7, wherein And the auxiliary line is formed of a single metal layer or a multiple metal layer. The method of claim 10, And an etching ratio of the uppermost metal layer among the multiple metal layers is smaller than that of the lower metal layer. The method of claim 7, wherein The depth of the groove is a method of manufacturing an organic light emitting diode display device, characterized in that 500 초과 or more within the range not exceeding the total thickness of the first insulating layer. The method of claim 7, wherein The auxiliary line may be a wet etching or dry etching method of manufacturing an organic light emitting diode display device.

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