KR20100131710A - Voltage generating circuit - Google Patents

Abstract

PURPOSE: A voltage generating circuit is provided to generate high voltage of a certain voltage level by changing the period of a clock. CONSTITUTION: A first voltage generation unit(210) outputs a first voltage. A second voltage generation unit(240) outputs a second voltage. The second voltage is changed according to the variation of the external input power source. A clock generator(220) outputs a clock signal. The clock generator changes the period of the clock according to the input of the external power supply. A voltage pump(230) pumps high voltage according to the clock signal.

Description

Voltage generating circuit

The present invention relates to a voltage generator circuit, and more particularly, to a voltage generator circuit that can adjust the amount of current in the output voltage by controlling the clock cycle in accordance with the input voltage level.

In general, an internal clock is used to operate internal devices in a memory, an IC chip, and the like. In nonvolatile memory devices, an internal clock is used in a macro controller or a pump circuit. To this end, a circuit that generates a reference clock may have a large cycle change when a PVT variation occurs in process, voltage, temperature, and the like.

In particular, in the case of a voltage generation circuit that generates an operating voltage of the nonvolatile memory device, the voltage pump generates the high voltage VPP by the input clock and the external power supply VDD. Therefore, when the external power source VDD is changed from the outside, the high voltage VPP output by the pump is also changed. Since a device such as a nonvolatile memory device requires a constant voltage supply for proper operation, a change in the high voltage VPP due to a change in the external power supply VDD may cause an error in operation.

The larger the change range of the external power supply VDD is, the larger the change of the high voltage VPP is, and the lower the external power supply is, the lower the power supply capability of the high voltage is and thus the output is unstable.

1 shows a general voltage generator circuit.

Referring to FIG. 1, the voltage generation circuit 100 includes a voltage down converter (VDC) 110, a clock generator 120, and a voltage pump 130.

The voltage down converter 110 generates and outputs an internal input power VDC using the reference voltage Vref and the input power VDD. The clock generator 120 generates a clock signal CLK using an internal input power source VDC.

The voltage pump 130 generates and outputs a high voltage VPP by the input power supply VDD and the clock signal CLK.

The voltage down converter 110 generates a constant internal input power source VDC regardless of the voltage level of the input power source VDD. The clock generator 120 outputs the clock signal CLK using the internal input power source VDC. Therefore, the period of the clock signal CLK is kept constant regardless of the external input power source VDD.

The high voltage VPP output from the voltage pump 130 pumping the voltage using the clock signal CLK should also be maintained at a constant voltage level regardless of the external input power source VDD.

At this time, the pumping current Ivpp output by the voltage pump 130 should also be kept constant. However, the pumping current Ivpp is affected by the external input voltage VDD. Therefore, when the external input voltage VDD is changed, the pumping current Ivpp is changed.

If the pumping current (Ivpp) is changed, devices that must consume a constant current may malfunction.

Accordingly, an aspect of the present invention is to provide a voltage generator circuit that generates and outputs a constant high voltage current by changing a clock period according to an externally input voltage level.

Voltage generation circuit according to a feature of the invention,

A first voltage generator configured to output a first voltage; A second voltage generator configured to output a second voltage changed according to a change in an external input power source; A clock generator for outputting a clock signal by the first and second voltages, and changing a period of the clock signal according to the external input power source; And a voltage pump for pumping and outputting a high voltage according to the clock signal.

The first voltage generator includes: a first reference voltage generator configured to generate a first reference voltage maintained at a constant voltage level; Comparing the first and second resistance groups, the first feedback voltage and the first reference voltage to distribute the external input voltage by a first control signal to output the first voltage and the first feedback voltage, And a first comparator for outputting the first control signal according to the comparison result.

The second voltage generator includes: a second reference voltage generator for generating a second reference voltage whose voltage level is changed according to a change in the external input voltage; Comparing the third and fourth resistance groups for dividing the external input voltage by a second control signal to output the second voltage and the second feedback voltage, and comparing the second feedback voltage and the second reference voltage. And a second comparator for outputting the second control signal according to the comparison result.

The clock generator may include: a first inverter connected between the second voltage and a ground node and inverting a third control signal to output a third voltage; A second inverter connected between the second voltage and a ground node and outputting a fourth voltage by inverting a fourth control signal; A third reference voltage generator configured to divide the first voltage to generate a third reference voltage; A third comparator comparing the third voltage with the third reference voltage and outputting a fifth control signal according to the result; A fourth comparator comparing the fourth voltage with the third reference voltage and outputting a sixth control signal according to the result; And a logic calculator configured to output the third and fourth control signals according to the fifth and sixth control signals, and invert the third control signal to output the clock signal.

The clock signal may be changed in cycle according to the magnitude of the second voltage.

A first transistor connected between an output terminal of the third comparator and the external input power input terminal and turned on or off by an enable signal; and an inversion of the enable signal connected between an output terminal of the fourth comparator and a ground node And a second transistor turned on or off by a signal.

The clock signal is generated when the first and second transistors are turned from a turn on state to a turn off state.

The logic operation unit is configured in the form of an SR latch circuit.

Voltage generation circuit according to another feature of the invention,

A first inverter connected between a first voltage and a ground node changed according to an external input power source, a first inverter for inverting a first control signal and outputting the first voltage, a second inverter connected between the first voltage and a ground node, and a second control A second inverter for inverting the signal and outputting the second voltage; a reference voltage generator for generating a reference voltage by distributing a second voltage maintaining a constant voltage level regardless of the external input power; the first voltage and the reference A first comparator comparing the voltage and outputting a third control signal according to the result, a second comparator comparing the second voltage and the reference voltage and outputting a fourth control signal according to the result, and the third and A clock generator for outputting the first and second control signals by a fourth control signal, the clock generator inverting the first control signal and outputting the clock signal as a clock signal; And a voltage pump generating a high voltage by the clock signal input from the clock signal.

Voltage generation circuit according to another feature of the present invention,

A first voltage generator configured to generate a first voltage using a first reference voltage having a constant voltage level and an external input power source; A first voltage generator configured to generate a second reference voltage whose voltage level is changed according to the change of the external input power and a second voltage using the external input power; A clock generator for outputting a clock signal by the first and second voltages and changing a cycle of the clock signal according to a change in the external input power; And a voltage pump for pumping and outputting a high voltage according to the clock signal.

The second reference voltage may increase with a constant slope as the external input power increases.

As described above, the voltage generation circuit according to the present invention can supply a stable operating voltage by changing the clock period in accordance with the power input from the outside so that the pump circuit generates and outputs a voltage and a current of a predetermined magnitude.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2A illustrates a voltage generation circuit according to an embodiment of the present invention.

2A, the voltage generation circuit 200 according to an embodiment of the present invention includes a first VDD down converter (VDC) generator 210, a second voltage down converter 240, a clock generator 220, and a voltage pump. 230.

The first voltage down converter 210 generates and outputs a first VDC voltage VDC1 having a predetermined level using a reference voltage and an input power source VDD input from the outside. The second voltage down converter 240 generates and outputs a second VDC voltage VDC2 that is changed according to a change in the voltage level of the external input power source VDD.

The clock generator 220 generates a clock signal CLK by using the first and second VDC voltages VDC1 and VDC2 according to the enable signal en, and the voltage pump 230 is connected to the clock signal CLK. Generates and outputs a high voltage (VPP).

The first voltage down converter 210 is configured as follows.

FIG. 2B shows the first voltage down converter of FIG. 2A.

Referring to FIG. 2B, the first voltage down converter 210 includes a reference voltage generator 211, a first comparator COM1, a first PMOS transistor P1, and first and second resistors R1 and R2. do.

The reference voltage generator 211 generates and outputs a first reference voltage Vrefc. The first comparator COM1 compares the first reference voltage Vrefc with the first feedback voltage Vf1 and outputs the result.

The reference voltage generator 211 constantly outputs the first reference voltage Vrefc to a process, voltage, and temperature (PVT), such as a bandgap or a Widlar generator.

The first reference voltage Vrefc is input to the inverting terminal (-) of the first comparator COM1, and the first feedback voltage Vf1 is input to the non-inverting terminal + of the first comparator COM2.

The first PMOS transistor P1 is connected between the external input power supply VDD and the node K1, and the gate of the first PMOS transistor P1 is connected to the output terminal of the first comparator COM1.

The first and second resistors R1 and R2 are connected in series between the node K1 and the ground node. The first VDC voltage VDC1 is output from the node K1, and the first feedback voltage Vf1 is output from the node K2, which is a contact point to which the first and second resistors R1 and R2 are connected.

Since the first reference voltage Vrefc maintains a constant voltage level regardless of the external input power VDD, the first VDC voltage VDC1 output by the first voltage down converter 210 is the external input power VDD. Maintain a constant voltage level.

The second voltage down converter 240 is as follows.

FIG. 2C shows the second voltage down converter of FIG. 2A.

Referring to FIG. 2C, the second voltage down converter 240 includes third to fifth resistors R3 to R5, first and second NMOS transistors N1 and N2, a second comparator COM2, and a second PMOS. Transistor P2.

The third resistor R3 and the first and second NMOS transistors N1 and N2 are connected in series between an external input power source VDD and a ground node. The second reference voltage Vref_c is output from the node K3, which is a contact point of the third resistor R3 and the first NMOS transistor N1. The second reference voltage Vref_c is a voltage changed by the external input power supply VDD.

The third resistor R3 and the first and second NMOS transistors N1 and N2 cause the second reference voltage Vref_C to increase with a constant slope as the external input power source VDD increases.

The first and second NMOS transistors N1 and N2 are connected in a diode form.

The second comparator COM2 compares the second reference voltage Vref_c with the second feedback voltage Vf2 and outputs a control signal according to the result. The second reference voltage Vref_c is input to the inverting terminal (-) of the second comparator COM2, and the second feedback voltage Vf2 is input to the non-inverting terminal + of the second comparator COM2.

The second PMOS transistor P2 is connected between the external input power source VDD and the node K4, and the gate of the second PMOS transistor P2 is at the output terminal of the second comparator COM2.

The fourth and fifth resistors R4 and R5 are connected in series between the node K4 and the ground node. The second VDC voltage VDC2 is output from the node K4, and the second feedback voltage Vf2 is output from the node K5, which is a contact point of the fourth resistor R4 and the fifth resistor R5.

Since the second reference voltage Vref_c is changed by the external input power VDD, the second VDC voltage VDC2 output by the second voltage down converter 240 is changed according to the external input power VDD. do.

2D is a diagram comparing output voltages of the first and second voltage down converters.

Referring to FIG. 2D, it can be seen that the second reference voltage Vref_c and the second VDC voltage VDC2 are changed according to the external input power source VDD.

The clock generator 220 for outputting the clock signal CLK by the first and second VDC voltages VDC1 and VDC2 is configured as follows.

FIG. 2E shows the clock generator of FIG. 2A.

Referring to FIG. 2E, the clock generator 220 may include first and second voltage generators 221 and 222, a reference voltage generator 223, third and fourth comparators COM3 and COM4, and an SR latch unit ( 224, a first inverter IN1, a fifth PMOS transistor P5, and a fifth NMOS transistor N5.

The first voltage generator 221 and the second voltage generator 222 generate and output first and second voltages V1 and V2 according to the values of the second VDC voltage VDC2 and the resistance and the capacitor, respectively. . The reference voltage generator 223 distributes the first VDC voltage VDC1 by the resistance ratio to generate the reference voltage Vref.

The third and fourth comparators COM3 and COM4 compare the first voltage V1 and the reference voltage Vref, and the second voltage V2 and the reference voltage Vref, respectively. Output voltages Vout1 and Vout2 are output respectively.

The SR latch unit 224 latches the first and second output voltages Vout1 and Vout2 and outputs them to the first and second outputs Q and / Q. The first output Q is inverted and output by the first inverter IN1. The output signal of the first inverter IN1 is the clock signal CLK.

The fifth PMOS transistor P5 and the fifth NMOS transistor N5 serve to enable clock generation by the enable signal en and the enable inversion signal enb, respectively.

The first voltage generator 221 includes a third PMOS transistor P3, a third NMOS transistor N3, a sixth resistor R6, and a first capacitor C1, and the second voltage generator 222. Includes a fourth PMOS transistor P4, a fourth NMOS transistor N4, a seventh resistor R7, and a second capacitor C2.

The reference voltage generator 223 includes eighth and ninth resistors R8 and R9. The SR latch unit 224 includes first and second NAND gates NA1 and NA2.

The third PMOS transistor P3, the sixth resistor R6, and the third NMOS transistor N6 are connected in series between an input terminal of the second VDC voltage VDC2 and a ground node, and are connected to the third PMOS transistor P3. The first output Q is input to the gate of the third NMOS transistor N3.

The first voltage V1 is output from the node K6, which is a contact point of the third PMOS transistor P3 and the sixth resistor R6.

The first capacitor C1 is connected between the node K6 and the ground node. The node K6 is connected to the inverting terminal (−) of the third comparator COM3.

The fourth PMOS transistor P4 and the seventh resistor R7 and the fourth NMOS transistor N4 are connected in series between the input terminal of the second VDC voltage VDC2 and the ground node, and the fourth PMOS transistor P4 and the fourth PMOS transistor P4 are connected in series. The second output / Q is input to the gate of the 4 NMOS transistor N4.

The second voltage V2 is output at the node K7 which is a contact point of the fourth PMOS transistor P4 and the seventh resistor R7.

The second capacitor C2 is connected between the node K7 and the ground node. The node K7 is connected to the inverting terminal (−) of the fourth comparator COM4.

The eighth and ninth resistors R8 and R9 are connected between the input terminal of the first VDC voltage VDC1 and the ground node. The reference voltage Vref is output from the node K8, which is a contact point of the eighth resistor R8 and the ninth resistor R9. The node K8 is connected to the non-inverting terminal + of the third and fourth comparators COM3 and COM4.

The first output voltage Vout1 is output from the node K9 that is the output terminal of the third comparator COM3, and the second output voltage Vout2 is output from the node K10 that is the output terminal of the fourth comparator COM4.

The fifth PMOS transistor P5 is connected between the input terminal of the external input power supply VDD and the node K9, and the fifth NMOS transistor N5 is connected between the node K10 and the ground node.

The enable signal en is input to the gate of the fifth PMOS transistor P5, and the enable inversion signal enb is input to the gate of the fifth NMOS transistor N5.

The node K9 is connected to one input terminal of the first NAND gate NA1, and the node K10 is connected to one input terminal of the second NAND gate NA2.

The other input terminal of the first NAND gate NA1 is connected to the output terminal of the second NAND gate NA2, and the other input terminal of the second NAND gate NA2 is connected to the output terminal of the first NAND gate NA1. .

The output signal of the first NAND gate NA1 is the first output Q, and the output signal of the second NAND gate NA2 is the second output / Q.

The operation of the clock generator 220 is as follows.

When the enable signal en is input at a low level, since the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are turned on, the first and second outputs Q and / Q are kept constant so that the clock signal ( CLK) is not generated.

The enable signal en becomes high and the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are turned off. At this time, the node K9 is in a high level state, and the node K10 is in a low level state.

The NAND operation outputs a high signal regardless of the other input value if either input is low level. Therefore, the output of the second NAND gate NA2 is at a low level. Therefore, the second output / Q is at the low level.

The first NAND gate NA1 outputs a high level by the node K9 of the high level and the second output / Q of the low level. Therefore, the first output Q is at a high level. In addition, the second NAND gate NA2 changes the second output / Q to a low level and outputs the output as the first output Q is changed to a high level.

Accordingly, the first voltage generator 221 outputs the low level first voltage V1, and the second voltage generator 222 outputs the high level second voltage V2.

The first and second voltages V1 and V2 are affected by the external input power supply VDD by the circuit configurations of the first and second voltage generators 231 and 232 and the reference voltage generator 233. The reference voltage Vref is a constant voltage level that is not affected by the external input power supply VDD.

The first and second voltages V1 and V2 are changed by delay values of the resistor and the capacitor.

The first voltage V1 is lower than the reference voltage Vref and the second voltage V2 is higher than the reference voltage Vref. Accordingly, the third comparator COM3 outputs a low level signal, and the fourth comparator COM4 outputs a high level signal.

Accordingly, the output signal of the first NAND gate NA1 is changed from the high level to the low level. The second NAND gate NA1 outputs a high level signal at a low level. As the operation continues, the first output Q is changed to a high level and a low level to generate a clock signal CLK.

At this time, since the first and second voltages V1 and V2 are changed by the second VDC voltage VDC2 changed by the external input power VDD, the clock signal CLK is also changed by the external input power VDD. .

That is, the period of the clock signal CLK increases when the external input power supply VDD increases, and the period of the clock signal CLK decreases when the external input power supply VDD decreases.

Accordingly, the voltage pump 230 generates the high voltage VPP having the same voltage level, and when the external input power supply VDD increases, the period of the clock signal CLK increases, so that the pumping operation is slowed down, thereby decreasing the current.

When the external input power supply VDD is reduced, the period of the clock signal CLK is reduced, so that the pumping operation is faster, and the current is increased. Therefore, the current output from the voltage pump 230 is controlled according to the variation of the external input power VDD, thereby stably providing the amount of current when supplying the internal power.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 shows a general voltage generator circuit.

2A illustrates a voltage generation circuit according to an embodiment of the present invention.

FIG. 2B shows the first voltage down converter of FIG. 2A.

FIG. 2C shows the second voltage down converter of FIG. 2A.

2D is a diagram comparing output voltages of the first and second voltage down converters.

FIG. 2E shows the clock generator of FIG. 2A.

* Brief description of the main parts of the drawings *

210: first voltage down converter 220: clock generator

230: voltage pump 240: second voltage down converter

Claims (11)

A first voltage generator configured to output a first voltage; A second voltage generator configured to output a second voltage changed according to a change in an external input power source; A clock generator for outputting a clock signal by the first and second voltages, and changing a period of the clock signal according to the external input power source; And A voltage pump that pumps and outputs a high voltage according to the clock signal Voltage generation circuit comprising a. The method of claim 1, The first voltage generator, A first reference voltage generator configured to generate a first reference voltage maintained at a constant voltage level; First and second resistance groups for distributing the external input voltage by a first control signal to output the first voltage and the first feedback voltage; And a first comparator comparing the first feedback voltage with the first reference voltage and outputting the first control signal according to the comparison result. 3. The method of claim 2, The second voltage generator, A second reference voltage generator configured to generate a second reference voltage whose voltage level is changed in response to a change in the external input voltage; Third and fourth resistance groups for dividing the external input voltage by a second control signal to output the second voltage and the second feedback voltage; And a second comparator comparing the second feedback voltage with the second reference voltage and outputting the second control signal according to the comparison result. The method of claim 3, wherein The clock generator, A first inverter connected between the second voltage and a ground node and outputting a third voltage by inverting a third control signal; A second inverter connected between the second voltage and a ground node and outputting a fourth voltage by inverting a fourth control signal; A third reference voltage generator configured to divide the first voltage to generate a third reference voltage; A third comparator comparing the third voltage with the third reference voltage and outputting a fifth control signal according to the result; A fourth comparator comparing the fourth voltage with the third reference voltage and outputting a sixth control signal according to the result; A logic calculator configured to output the third and fourth control signals according to the fifth and sixth control signals, And inverting the third control signal to output the clock signal. The method of claim 4, wherein The clock signal generator, characterized in that the cycle is changed in accordance with the magnitude of the second voltage. The method of claim 4, wherein A first transistor connected between an output terminal of the third comparator and the external input power input terminal and turned on or off by an enable signal; And a second transistor connected between an output terminal of the fourth comparator and a ground node, the second transistor being turned on or off by an inversion signal of the enable signal. The method of claim 6, And the clock signal is generated when the first and second transistors are turned from a turn on state to a turn off state. The method of claim 4, wherein And the logic operation unit is configured in the form of an SR latch circuit. A first inverter connected between the first voltage and the ground node changed according to an external input power, and inverting the first control signal to output the first voltage; A second inverter connected between the first voltage and a ground node and inverting a second control signal to output a second voltage; A reference voltage generator for distributing a second voltage maintaining a constant voltage level regardless of the external input power to generate a reference voltage; A first comparator comparing the first voltage with the reference voltage and outputting a third control signal according to the result; A second comparator comparing the second voltage with the reference voltage and outputting a fourth control signal according to the result; A clock generator for outputting the first and second control signals according to the third and fourth control signals, and inverting the first control signal to output the clock signal as a clock signal; And And a voltage pump generating a high voltage by the clock signal inputted from the clock signal. A first voltage generator configured to generate a first voltage using a first reference voltage having a constant voltage level and an external input power source; A first voltage generator configured to generate a second reference voltage whose voltage level is changed according to the change of the external input power and a second voltage using the external input power; A clock generator for outputting a clock signal by the first and second voltages and changing a cycle of the clock signal according to a change in the external input power; And A voltage pump that pumps and outputs a high voltage according to the clock signal Voltage generation circuit comprising a. The method of claim 10, And the second reference voltage increases with a constant slope as the external input power increases.

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