KR20100129272A - Pillar devices and methods of making thereof - Google Patents

Abstract

A method of manufacturing a semiconductor device includes providing an insulating layer comprising a plurality of openings, forming a first semiconductor layer over the insulating layer and in the plurality of openings in the insulating layer, and forming a first semiconductor layer. Removing the first portion of the first semiconductor layer such that a second portion of the first conductivity type remains below the plurality of openings in the insulating layer and the top of the plurality of openings in the insulating layer remains uncharged. The method also includes forming a second semiconductor layer over the insulating layer and over the plurality of openings in the insulating layer, and removing the first portion of the second semiconductor layer located over the insulating layer. A second conductive second portion of the second semiconductor layer remains on top of the plurality of openings in the insulating layer to form a plurality of pillar-type diodes in the plurality of openings.

Description

PILLAR DEVICES AND METHODS OF MAKING THEREOF}

Cross Reference to Related Patent Application

This application claims priority to US Application Nos. 12 / 007,780 and 12 / 007,781, filed January 15, 2008, both of which are hereby incorporated by reference in their entirety. .

Technical field

TECHNICAL FIELD The present invention generally relates to the field of semiconductor device processing, and more particularly to pillar devices and methods of manufacturing the devices.

US Patent Application No. 10 / 955,549 (corresponding to US Patent Application Publication No. 2005/0052915 A1), filed on September 29, 2004, incorporated by reference herein, discloses a three-dimensional memory array. In this three-dimensional memory array, the data state of a memory cell is stored in a resistive state of a polycrystalline semiconductor material of a pillar-type semiconductor junction diode. Subtractive methods are used to fabricate such pillar diode devices. The method includes depositing one or more layers of silicon, germanium or other semiconductor material. The deposited semiconductor layer or layers are then etched to obtain a semiconductor pillar. As a hard mask for pillar etching, an SiO ₂ layer can be used, which is then removed. Next, SiO ₂ or other gap filling dielectric material is deposited between and over the pillars. A chemical mechanical polishing (CMP) or etch back step is then performed to planarize the gap filling dielectric with the top surface of the pillar.

Further description of the subtractive pillar manufacturing process is described in US Patent Application No. 11 / 015,824, "Nonvolatile Memory Cells with Reduced Height Vertical Diodes," filed December 17, 2004, and July 2007. See US patent application Ser. No. 11 / 819,078, filed 25.

In the subtractive method, however, care must be taken for small diameter and width pillared devices to avoid undercutting of the pillars at the base of the pillars during the etching step. The undercut pillar device is likely to fall during subsequent processing. In addition, for smaller pillar devices, the height of the semiconductor pillar may be limited by the thin, flexible photoresist used as an etch mask, and the oxide gap filling step presents processing challenges when the aspect ratio of the openings between the pillars increases. Imparted, the CMP process or etch back of the gap filling layer can remove significant thickness of the deposited semiconductor material.

One embodiment of the present invention provides a method of manufacturing a semiconductor device, the method comprising providing an insulating layer comprising a plurality of openings, in a plurality of openings of the insulating layer, and over the insulating layer; Forming a layer. In addition, the method further includes the first semiconductor such that the first conductive second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the insulating layer, and the upper portion of the plurality of openings in the insulating layer remains uncharged. Removing the first portion of the layer. The method also includes forming a second semiconductor layer over the insulating layer and the plurality of openings over the insulating layer and removing the first portion of the second semiconductor layer located over the insulating layer. The second conductive second portion of the second semiconductor layer remains on top of the plurality of openings in the insulating layer to form a plurality of pillar-type diodes in the plurality of openings.

Another embodiment provides a method of manufacturing a semiconductor device, the method comprising forming a plurality of tungsten electrodes, nitriding a tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes, and a tungsten nitride barrier Forming an insulating layer comprising a plurality of openings such that the semiconductor layer is exposed at the plurality of openings in the insulating layer, and forming a plurality of semiconductor devices on the tungsten nitride barrier at the plurality of openings in the insulating layer.

Another embodiment provides a method of manufacturing a semiconductor device, the method comprising forming a plurality of tungsten electrodes, selectively forming a plurality of conductive barriers on an exposed top surface of the tungsten electrode, and Forming an insulating layer comprising a plurality of openings such that the barrier is exposed at the plurality of openings in the insulating layer, and forming a plurality of semiconductor devices on the conductive barrier at the plurality of openings.

Another embodiment provides a method of manufacturing a semiconductor device, the method comprising forming a plurality of bottom electrodes on a substrate, and forming a plurality of first openings having a first width such that the bottom electrodes are exposed within the first openings. Forming an insulating layer comprising: forming a first semiconductor region of a first conductivity type in the first opening, forming a sacrificial material in the plurality of first openings over the first semiconductor region, and sacrificial material Forming a plurality of second openings in the insulating layer having a second width greater than the first width, exposing sacrificial material from the first openings through the second openings; Forming a conductive second semiconductor region, and forming an upper electrode in the second opening in the insulating layer such that the upper electrode is in contact with the second semiconductor region, the first and second semiconductor regions First to form a pillar shaped diodes in the first opening.

Another embodiment provides a method of making a pillar device comprising providing an insulating layer having an opening and selectively depositing a germanium or germanium rich silicon germanium semiconductor material into the opening to form a pillar device.

The present invention has the effect of providing a pillar device and a method of manufacturing the device.

1A, 1C and 1E are side cross-sectional views illustrating the step of forming a pillar device according to a first embodiment of the present invention, in which FIGS. 1B and 1D are three-dimensional views of the steps shown in FIGS. 1A and 1C, respectively. Drawing.
2A-2C are side cross-sectional views illustrating the step of forming a pillar device according to a second embodiment of the present invention.
3A-3E are side cross-sectional views illustrating the step of forming a pillar device according to a third embodiment of the present invention.
3F-3G are micrographs of an exemplary device made according to the third embodiment.
4 is a three dimensional view of a completed pillar device according to one or more embodiments of the present invention.
FIG. 5A is a plot of etch rate versus polysilicon doping according to the prior art, and FIGS. 5B-5E are side cross-sectional views illustrating the step of forming a pillar device according to a fourth embodiment of the present invention.
6A-6G are side cross-sectional views illustrating the step of forming a pillar device according to a fifth embodiment of the present invention.
7A and 7B are side cross-sectional views of device features made in accordance with an embodiment of the invention.
8A-8D are side cross-sectional views illustrating steps of forming a pillar device according to an embodiment of the present invention.
8E is a three dimensional view of a completed pillar device according to one embodiment of the present invention.
9A is a cross-sectional SEM of a 40 nm thick Ge film deposited by GeH ₄ on 380 ° C. and 1 torr for 10 minutes on a silicon seed film deposited on TiN by SiH ₄ decomposition for 60 minutes at 380 ° C. and 1 torr. It is a video. 9B is a cross-sectional SEM image of the surface of SiO ₂ after two identical SiH ₄ and GeH ₄ CVD treatments, in which no Ge deposition was observed on SiO ₂ .

The inventors have found that for semiconductor pillar devices having at least two different conductivity type regions, such as diodes, which comprise both p-type and n-type semiconductor regions, such devices when the device is formed in an opening in an insulating layer. It was recognized that special steps must be taken to avoid shorts.

For example, if the conductive barrier layer is simply deposited in the opening and then planarized, then the conductive barrier layer will extend along the sidewall of the opening from the bottom of the opening to the top. Then, when the semiconductor diode is deposited in the opening, a conductive barrier layer located along the sidewall of the opening shorts the p-type region of the diode to the n-type region of the diode.

In addition, where the semiconductor layer of the diode is formed by a method such as low pressure chemical vapor deposition (LPCVD), then conformal deposition fills the opening from the side as well as the bottom. Thus, if an n-type semiconductor is first deposited in the opening, it is then also located along or filling the entire sidewall of the opening. If the n-type region is located along the sidewall of the opening and the p-type region is located at the center of the opening, then the upper electrode is in contact with both the p-type and n-type regions. If the n-type region fills the entire opening, then there is no place to form a p-type region in the opening to form a diode.

Embodiments of the present invention provide a method for overcoming these problems. In the first embodiment, the barrier layer is selectively formed so as not to short-circuit the diode formed in the opening in the insulating layer over the barrier. In a first aspect of the first embodiment, the barrier layer can be formed by nitriding the lower tungsten electrode to form a tungsten nitride barrier layer before or after forming the insulating layer. When the tungsten nitride barrier is formed after the formation of the insulating layer, the barrier layer is formed by nitriding a portion of the tungsten electrode exposed to the opening of the insulating layer. This nitriding step through the openings in the insulating layer is used to selectively form a tungsten nitride barrier layer on the bottom of the openings. In an alternative aspect of the first embodiment, the barrier layer is formed by nitriding on the electrode prior to the formation of the insulating layer.

In a second embodiment, the barrier layer is formed by selective deposition on the bottom electrode. In a third embodiment, selective silicon that can be precisely controlled to concave one conductive silicon layer in the opening, prior to forming a silicon layer of opposite conductivity in the opening in the opening created by the recess etch. Recess etch is used.

1 and 2 illustrate a method of manufacturing a nitrided barrier layer according to an alternative aspect of the first embodiment. 1A and 1B show side cross-sectional and three-dimensional views, respectively, of a plurality of conductive electrodes 1 separated from each other by an insulating material or layer 3. The electrode may have any suitable thickness, such as about 200 nm to about 400 nm. The electrode 1 may comprise tungsten or another conductive material that may be nitrided. The insulating material may include any suitable insulating material, such as high dielectric constant insulating material, such as silicon oxide, silicon nitride, aluminum oxide, tantalum pent oxide or organic insulating material. The electrode deposits a layer of tungsten on any suitable substrate, photolithographic patterns the layer of tungsten with electrode 1, deposits an insulating layer over and between the electrodes 1, and insulates the insulating layer with chemical mechanical polishing (CMP). Or by forming an insulating material region 3 that is flattened by an etch back to isolate the electrodes 1 from each other. Alternatively, the electrode 1 may be formed by the damascene method, in which a groove is formed in the insulating layer 3, and a tungsten layer is formed in the groove and on the top surface of the insulating layer 3. Subsequently, planarization of the tungsten layer by CMP or etch back may be followed by forming the electrode 1 in the groove in the insulating layer 3. The electrode 1 may be a rail type electrode, as shown in FIG. 1B. Other electrode 1 shapes can also be used.

1C and 1D illustrate the step of nitriding the tungsten electrode 1 to form a tungsten nitride barrier 5 on the plurality of tungsten electrodes before the damascene type insulating layer is deposited on the electrode 1. Barrier 5 may have any suitable thickness, such as, for example, about 1 nm to about 30 nm. Any nitriding method can be used. For example, a plasma nitridation method can be used, wherein the nitrogen containing plasma, such as ammonia or nitrogen plasma, is provided on the surfaces of tungsten 1 and insulator 3 that are exposed together. Details of exemplary plasma nitridation of tungsten for forming tungsten nitride are described in US Pat. No. 5,780,908, which is incorporated herein by reference in its entirety. The method of US Pat. No. 5,780,908 is used to form a nitrided tungsten surface to provide a barrier between tungsten and an aluminum layer thereon for the purpose of forming a metal gate, instead of forming a barrier layer under the semiconductor device.

Although tungsten has been described as being used as the electrode 1 material, other materials such as titanium, tungsten silicide or aluminum may also be used. For example, the stability of tungsten nitride layers formed by nitriding tungsten silicide surfaces is described in US Pat. No. 6,133,149, which is incorporated herein by reference in its entirety.

Plasma nitridation nitrides the entire exposed surface of the insulating layer 3 and the electrode 1. This leaves a surface, part of which is a tungsten nitride barrier 5 and part of which is a portion of the nitrogen-containing insulating material 7. For example, if the insulating material 3 is silicon oxide, then the upper portion thereof is converted to silicon oxynitride 7 after nitriding. Of course, if the original insulating material 3 is silicon nitride, then nitriding may form a nitrogen rich silicon nitride region 7 on the surface or top of the insulating material 3. Thus, the top of the insulating layer or material 3 separating the adjacent tungsten electrodes 1 from each other is also nitrided during the nitriding step.

As shown in FIG. 1E, a second insulating layer 9 is deposited over the nitrided insulating material 7 and the tungsten nitride barrier 5. The insulating layer 9 may have better adhesion to the tungsten nitride surface than to the unnitrided tungsten surface. The insulating layer 9 may comprise any suitable insulating material, such as high dielectric constant insulating material, such as silicon oxide, silicon nitride, aluminum oxide, tantalum pentoxide or organic insulating material. The material of layer 9 may be the same as or different from the material of insulating layer 3.

A plurality of openings 11 are formed in the insulating layer 9 so that the tungsten nitride barrier 5 is exposed in the plurality of openings 11. The opening 11 forms a photoresist layer over the insulating layer 9, exposes and develops (ie, patterns) the photoresist layer, and opens the opening 11 in the layer 9 using a photoresist pattern as a mask. It may be formed by photolithography patterning such as etching and removing the photoresist pattern.

Thus, in the method of FIGS. 1A-1D, a nitriding step for forming the barrier 5 is performed prior to the step of forming the insulating layer 9. The insulating layer 9 is formed on the tungsten nitride barrier 5, and subsequently, a plurality of openings 11 are formed in the insulating layer 9 to expose the top surface of the tungsten nitride barrier 5.

Thereafter, a plurality of semiconductor devices are formed on the tungsten nitride barrier 5 in the plurality of openings 11 in the insulating layer 9. For example, a silicon layer 13, such as a doped polysilicon or amorphous silicon layer, is deposited on the barrier 5 in the opening 11. The formation of a semiconductor device such as a pillar type diode will be described in more detail with reference to the third to fifth embodiments below.

2A to 2C show an alternative embodiment of the first embodiment in which an insulating layer 9 is formed on the plurality of tungsten electrodes 1 (and on the insulating material or layer 3) before the barrier 5 is formed. Illustrate the method. A plurality of openings 11 are then formed in the insulating layer 9 to expose the top surfaces of the plurality of tungsten electrodes 1 as shown in FIG. 2A. As shown in FIG. 2B, a nitriding step is performed after forming the plurality of openings 11 in the insulating layer 9 such that the upper surfaces of the plurality of tungsten electrodes 1 are nitrided through the plurality of openings 11. . For example, as shown in FIG. 2B, a nitrogen containing plasma 15 is provided into the opening 11 to nitride the tungsten electrode 1. Nitriding forms a tungsten barrier 5 on the tungsten electrode 1 in the opening 11.

Therefore, the nitriding step is performed after forming the plurality of openings 11 in the insulating layer 9 to form a tungsten nitride barrier. Optionally, the nitriding step also nitrides at least one sidewall 12 of the plurality of openings 11 in the insulating layer 9. If the insulating layer 9 is silicon oxide, then the side wall 12 is converted to the silicon oxynitride region 14. As used herein, the term "side wall" refers to both a plurality of side walls of an opening having a polygonal cross section or both one side wall of an opening having a circular or oval cross section for convenience. Thus, the use of the term "side wall" should not be construed as limited to the side walls of the openings having a polygonal cross section. If the insulating layer 9 is made of a material other than silicon oxide, this may also be nitrided. For example, the metal oxide will also be converted to metal oxynitride, the silicon nitride will be converted to nitrogen rich silicon nitride, and the organic material will include a nitrogen rich region 14.

2C shows the formation of the silicon layer 13 in the opening 11. Details of layer 13 deposition will be provided in connection with the third to fifth embodiments described below.

The advantage of performing nitriding after planarization of the electrode 1 as shown in FIGS. 1C and 1D is that no subsequent insulating layer 9 is deposited on the tungsten surface. If the insulating layer is silicon oxide, this may not provide the ideal bonding force to tungsten. However, silicon oxide is better attached on metal nitride barriers such as tungsten nitride barrier 5.

If the gas required for the plasma deposition reactor is supplied through the piping, then plasma nitriding can be performed in the same chamber as the deposition of the insulating layer 9 without adding any process steps. In this process, a nitride plasma such as nitrogen or ammonia plasma is turned on for a predetermined time to nitride the tungsten electrode 1 surface. Thereafter, the nitrogen containing plasma is pumped out of the deposition chamber, and the deposition layer 9 deposition process is started by providing the deposition chamber with a desired precursor, such as silicon and an oxygen containing precursor (e.g., a silane in combination with oxygen or nitrogen oxides). Layer 9 is deposited. Preferably layer 9 is silicon oxide deposited by PECVD.

The advantage of performing nitriding after forming the opening 11 is that if the tungsten electrode sidewall 2 is exposed in the overetched opening 11, then this sidewall 2 is also nitrided as shown in FIG. 2B. will be. This may occur if the overetched insulating layer 9 opening 11 removes the TIN junction layer, which may be located under the tungsten electrode 1. In other words, the plurality of openings 11 in the insulating layer 9 may be partially misaligned with the plurality of tungsten electrodes 1, and the etching step used to form the plurality of openings 11 may be misaligned and overetched. This exposes at least portions of the side wall 2 of the tungsten electrode 1 as shown in FIG. 2A. At this time, the nitriding step is performed by applying the tungsten nitride barrier 6 and the tungsten nitride barrier 5 to the upper surface of the electrode 1 on the exposed portion of the side wall 2 of the tungsten electrode 1 as shown in FIG. 2B. Form.

If misalignment occurs during the formation of the opening 11, the silicon layer 13 may extend into the overetched portion of the opening 11. However, the silicon layer 13 is in contact only with the tungsten nitride barriers 5, 6, as shown in FIG. 2C, and is not in direct contact with the tungsten electrode 1. When the final device, such as a pillar diode, is completed, it is partially misaligned with the tungsten electrode 1, and the tungsten nitride barriers 5 and 6 are located on at least part of the top surface of the tungsten electrode and the side wall of the tungsten electrode. The oxide insulating layer 9 is located around the diode as will be described in more detail below, so that the portion 14 of the oxide insulating layer 9 located adjacent to at least one sidewall of the pillar-type diode is nitrided.

Both of the above non-limiting advantages of nitriding—improved adhesion of the insulating layer 9 to tungsten nitride and formation of the electrode 1 sidewall barrier 6—before the layer 9 deposition and within the layer 9 It will be achieved if nitriding is performed after forming the opening 11. Thus, if desired, electrode 1 nitriding can be performed both after bottom electrode planarization as shown in FIGS. 1C and 1D and after formation of the opening 11 as shown in FIG. 2B.

In the second embodiment, the conductive barrier 5 is formed by selective deposition on the exposed top surface of the tungsten electrode 1. For example, in one aspect of the second embodiment, the metal or metal alloy barrier 5 is formed by selective atomic layer deposition on a plurality of tungsten electrodes. The barrier 5 metal or metal alloy may comprise tantalum, niobium or an alloy thereof. Selective atomic layer deposition of barrier metals such as tantalum or niobium is described in US Patent Application Publication No. 2004/0137721, which is incorporated herein by reference in its entirety. The atomic layer deposition of the barrier 5 is preferably performed prior to depositing the insulating layer 9 as shown in FIGS. 1C and 1D. Selective deposition selectively forms a barrier 5 only on the electrode 1 except the portion adjacent to the insulating layer or material 3. Thus, metal connection from the barrier 5 of the electrode to the top surface of the insulating layer 9 is prevented.

In an alternative method of the second embodiment, the conductive barrier is formed by selectively plating a barrier metal or metal alloy on the plurality of tungsten electrodes. Plating may include electroless plating or electroplating, which selectively plate the barrier 5 only on the electrode 1 except the adjacent insulating layer 3 or 9. The barrier metal or metal alloy may comprise any conductive barrier material that can be selectively plated only on the electrode and not on the insulating layer from a plating solution such as cobalt or cobalt tungsten alloy comprising CoWP. Selective deposition of barrier metal alloys, such as CoWP by plating, is performed by Jeff Gamindo of MRS Abstract No. F5.9, issued April 17-21, 2006 in San Francisco, which is hereby incorporated by reference in its entirety. Co-authors describe "Thermal Oxidation of Ni and Co Alloys Formed by Electroless Plating". Selective plating may be performed prior to the deposition of the insulating layer 9 and / or through the openings 11 in the insulating layer 9. In other words, the plating of the conductive barrier is performed by forming a plurality of insulating layers 9 on the plurality of conductive barriers 5 and subsequently exposing a plurality of layers in the insulating layer 9 so as to expose the top surfaces of the plurality of conductive barriers 5. It may be performed before the step of forming the insulating layer 9 so that the opening 11 is formed. Alternatively, plating of the conductive barrier may be performed after forming the plurality of openings 11 in the insulating layer 9, so that the plurality of conductive barriers are arranged in the plurality of openings 11 in the insulating layer 9. ) Is selectively formed on the upper surface of the plurality of tungsten electrodes (1).

As described above with respect to FIGS. 2A-2C, the openings 11 in the insulating layer 9 may be partially misaligned with the plurality of tungsten electrodes 1, thus forming a plurality of openings 11. Exposes at least a portion of the side wall 2 of the tungsten electrode 1. Selective deposition of the conductive barrier 5, such as selective plating, forms a conductive barrier 6 on the exposed portion of the side walls 2 of the plurality of tungsten electrodes 1 and a conductive barrier 5 on the top surface.

The method according to the third embodiment of the present invention forms a pillar-like device such as a pillar diode in the opening 11 in the insulating layer 9 by a modified process as shown in FIGS. 3A-3E. This device can be formed on the barrier layers 5, 6 of the first or second embodiment. Alternatively, the barrier layers 5 and 6 may be omitted, or the barrier 5 may be formed by non-selective layer deposition and subsequent photolithography patterning instead of the method of the first or second embodiment.

As shown in FIG. 3A, an insulating layer 9 comprising a plurality of openings 11 is provided over the substrate. The substrate may be any semiconductor substrate known in the art, such as IV-IV compounds, III-V compounds, II-VI compounds, such as monocrystalline silicon, silicon-germanium or silicon-germanium-carbon, epitaxial layers or glass on such substrates. Or any other semiconductor or non-semiconductor material, such as a plastic, metal or ceramic substrate. The substrate may include integrated circuits fabricated thereon, such as drive circuits for memory devices. As described above with respect to the first and second embodiments, a lower electrode such as a rail-shaped tungsten electrode 1 covered with a barrier 5 is formed on the substrate as a first step in the fabrication of a nonvolatile memory array. Other conductive materials such as aluminum, tantalum, titanium, copper, cobalt or alloys thereof may also be used. An adhesive layer, such as a TiN adhesive layer, may be included under the electrode 1 to assist the adhesion of the electrode to another material below the electrode 1 or to the insulating layer 3.

The insulating layer 9 can be any electrically insulating material, such as silicon oxide, silicon nitride or silicon oxynitride, or an organic or inorganic high dielectric constant material. If desired, the insulating layer 9 may be deposited as two or more separate sublayers. Layer 9 may be deposited by PECVD or any other suitable deposition method. Layer 9 may have any suitable thickness, such as about 200 nm to about 500 nm, for example.

Next, the insulating layer 9 is photolithographically patterned to form an opening 11 extending to and exposing the top surface of the barrier 5 of the electrode 1. The opening 11 should have approximately the same pitch and approximately the same width as the underlying electrode 1 such that each subsequently formed semiconductor pillar is formed over each electrode 1. As described above, some misalignment can be tolerated. Preferably, the opening 11 in the insulating layer 9 has a half pitch of 45 nm or less, such as 10 nm to 32 nm. Opening 11 with a small pitch forms a positive photoresist on insulating layer 9, exposes the photoresist to radiation such as 193 nm radiation, using an attenuated phase shift mask, patterning the exposed photoresist, and as a mask. It can be formed by etching the opening 11 in the insulating layer 9 using a patterned photoresist. Next, the photoresist pattern is removed. Any other suitable lithography or patterning may also be used. For example, other radiation wavelengths such as 248 nm can be used with or without the phase shift mask. For example, a 120-150 nm wide opening, such as about 130 nm, may be formed in 248 nm lithography, and a 45-100 nm wide opening, such as about 80 nm, may be formed in 193 nm lithography. In addition, various hardmasks and antireflective layers, such as BARC or DARC in combination with insulating hardmasks for 248 nm lithography and BARC or DARC in combination with double W / insulating hardmasks for 193 nm lithography, may also be used in lithography.

The first semiconductor layer 13 is formed in the plurality of openings 11 in the insulating layer 9 and on the insulating layer 9. The semiconductor layer 13 may comprise a compound semiconductor material, such as silicon, germanium, silicon-germanium or a III-V or II-VI material. The semiconductor layer 13 may be a polycrystalline material or an amorphous material such as polysilicon. The amorphous semiconductor material can be crystallized in a subsequent step. The layer 13 is preferably highly doped with a first conductivity type dopant, such as a p-type or n-type dopant, such as doping using a dopant concentration of 10 ¹⁸ to 10 ²¹ cm ⁻³ . For example, it is assumed that layer 13 is conformal deposited n-type doped polysilicon. The polysilicon may be deposited and then doped, but is preferably added to the dopant containing gas (ie silane gas) that provides the n-type dopant atoms, eg, phosphorus or arsenic, during LPCVD deposition of the polysilicon layer. Preferably doped in situ by flowing arsenic gas or phosphine gas). The resulting structure is shown in FIG. 3A.

As shown in FIG. 3B, the top of the semiconductor layer 13, such as the polysilicon layer, is removed. The lower n-type portion 17 of the polysilicon layer 13 remains below the opening 11 in the insulating layer 9, and the upper portion 19 of the plurality of openings 11 in the insulating layer 9. Remains uncharged. N-type portion 17 may be about 5 nm to about 80 nm thick, such as about 10 nm to about 50 nm thick. Other suitable thicknesses may be used instead.

Any suitable method may be used to remove the layer 13 from the upper portion 19 of the opening 11. For example, a two step process can be used. First, the polysilicon layer 13 is planarized with the top surface of the insulating layer 9. Planarization can be performed by CMP or etch back (such as isotropic etching) using optical end point detection. Once the polysilicon layer 13 is planarized with the top surface of the insulating layer 9 (ie, the polysilicon layer 13 fills the opening 11, but is not positioned over the top surface of the insulating layer 9). ), A second recess etch step is performed to concave the layer 13 in the opening 11, so that only the portions 17 of the layer 13 remain in the opening 11. Optionally or preferentially any optional etching step may be used, such as a wet or dry isotropic or anisotropic etching step of etching polysilicon remaining on top of the opening 11 above the insulating material (such as silicon oxide) of the layer 9. have. Preferably a dry etch step is used which provides a controllable etch end point.

For example, as shown in the micrograph of FIG. 3F, the recess etch step is a selective dry anisotropic etch step. In this step, the first semiconductor layer 13 remaining on top of the plurality of openings 11 is etched with a flat level etch front to concave the first semiconductor layer 13. The flat etch front provides that the portions 17 of the first semiconductor layer 13 remaining in the plurality of openings 11 have a substantially flat top surface as shown in FIG. 3F. This makes it possible to form "parfait" type diodes with substantially flat boundaries between regions of different conductivity type.

Alternatively, as shown in FIG. 3G, selective isotropic etching may be used to recess the layer 13. In this case, portions of the first semiconductor layer 13 remaining in the plurality of openings 11 have an annular (ie hollow ring) shape with a groove in the center as shown in FIG. 3G.

As shown in FIG. 3C, a second semiconductor layer 21 is then formed over the insulating layer 9 and in the upper portion 19 of the plurality of openings 11 in the insulating layer 9. The second semiconductor layer 21 may comprise the same or different semiconductor material as the material of the first semiconductor layer 13. For example, layer 21 may also include polysilicon. Of the layer 13 as disclosed in US Pat. No. 7,224,013 to Herner and Walker, entitled " junction diodes comprising a variety of semiconductor compositions, " incorporated herein by reference in its entirety. It may be desirable to deposit a layer 21 having a different semiconductor composition relative to the composition. For example, layer 13 may comprise a silicon-germanium alloy or silicon having a relatively low proportion of germanium, and layer 21 may have a silicon-germanium alloy having a relatively high proportion of germanium relative to layer 13. Or germanium, and vice versa. If a p-n type diode is formed in the opening 11, then the layer 21 may be highly doped with the opposite type of dopant from the conductive type of the layer 13, such as the p-type dopant. If necessary, the second semiconductor layer 21 has the same conductivity type as the first layer 13 but has a lower doping concentration than the layer 13.

When the p-i-n type diode is formed in the opening 11, the second semiconductor layer 21 may be an intrinsic semiconductor material such as intrinsic polysilicon. In this description, regions of semiconductor material that are not intentionally doped are described as intrinsic regions. However, those skilled in the art will understand that the intrinsic region may in fact contain low concentrations of p-type or n-type dopants. The dopant may diffuse from the adjacent region into the intrinsic region or may be present in the deposition chamber during the deposition step due to contamination from previous deposition. It will also be appreciated that the deposited intrinsic semiconductor material (such as silicon) may contain defects, which defects may cause the intrinsic semiconductor material to behave as if it were slightly n-doped. Use of the term "intrinsic" to describe silicon, germanium, silicon-germanium alloy, or some other semiconductor material means that this region does not contain any dopants at all, or that this region is completely electrically neutral. It is not. The second semiconductor layer 21 is then the first of the second semiconductor layer 21 located above the insulating layer 9, leaving a portion 23 of the layer 21 in the upper portion 19 of the opening 11. It is planarized with at least the top surface of the insulating layer 9 using chemical mechanical polishing to remove the portion. Alternatively, etch back may also be used. The intrinsic region or portion 23 may be between about 110 and about 330 nm, such as about 200 nm thick. The resulting device is shown in FIG. 3D.

Then, a dopant of a conductivity type opposite to that of the region 17 is injected into the upper section of the second portion 23 of the second semiconductor layer 21 to form a pin pillar diode. For example, a p-type dopant is injected into the upper section of the intrinsic portion 23 to form the p-type region 25. The p-type dopant is preferably boron or boron implanted as BF ₂ ions. Alternatively, region 25 may be selectively deposited on region 23 (after region 23 is recessed in opening 11), and then planarized instead of implanted into region 23. do. For example, region 25 may be formed by depositing a field p-type doped semiconductor layer by CVD and then planarizing the layer. Region 25 may be, for example, about 10 nm to about 50 nm thick. The pillar-type pin diode 27 located in the opening 11 includes an n-type region 17, an intrinsic region 23 and a p-type region 25 as shown in FIG. 3E. In general, the pillar diode 27 preferably has a substantially cylindrical shape having a circular or approximately circular cross section having a diameter of 250 nm or less. Alternatively, a pillar diode having a polygonal cross-sectional shape such as a rectangular or square shape may also be formed by forming the opening 11 having a polygonal cross-sectional shape instead of a circular or oval cross-sectional shape.

Optionally, by the method described in U.S. Application Publication 2006/0087005, entitled "Deposited Semiconductor Structures That Minimize N-type Dopant Diffusion and Methods for Manufacturing the Same," the disclosure of which is incorporated by reference in its entirety. N + dopant diffusion is prevented during subsequent intrinsic silicon deposition. In this method, an n-type semiconductor layer, such as an n-type polysilicon or an amorphous silicon layer, is covered by a silicon-germanium cover layer having at least 10 atomic percent germanium. The cover layer may be about 10 nm to about 20 nm thick, preferably about 50 nm thick or less, with little or no n-type dopant (ie, the cover layer is preferably a thin intrinsic silicon-germanium layer). Do). An intrinsic layer of a diode, such as a silicon-germanium layer or silicon layer, having less than 10 atomic percent germanium, is deposited on the capping layer. Alternatively, an optional silicon rich oxide (SRO) layer is formed between the intrinsic region 23 and the n-type region 17 of each diode 27. The SRO region forms a barrier that prevents or reduces the diffusion of phosphorus from the bottom n-type region 17 of the diode into the undoped region 23.

In an exemplary embodiment, the bottom region 17 of the diode 27 is N ⁺ (highly doped n-type) and the top region 25 is P ⁺ . However, the vertical pillars may also include other structures. For example, the bottom region 17 is P ⁺ and the top region 25 is N ⁺ . In addition, the intermediate region may be intentionally lightly doped, intrinsic or not intentionally doped. An undoped region can never be completely electrically neutral and always has defects or contaminants, which causes the undoped region to behave as if it is slightly n-doped or p-doped. Such a diode can be considered as a pin diode. ^{Thus, P + / N - / N} +, P + / P - / N +, N + / N - / P + or N ⁺ / P ^- / P ⁺ diode may be formed.

4, the upper electrode 29 can be formed in the same manner as the bottom electrode 1, for example by depositing an additional layer, preferably made of titanium nitride, and preferably a conductive layer made of tungsten. have. The conductive and additional layers are patterned and etched using any suitable masking and etching technique to form a substantially parallel, substantially coplanar conductor rail 29 extending perpendicular to the conductor rail 1. In a preferred embodiment, the photoresist is deposited, patterned by photolithography, the conductive layer is etched, and then the photoresist is removed using standard processing techniques. Alternatively, an optional insulating oxide, nitride or oxynitride layer may be formed on the high doped region 25, the conductor 29 of May 31, 2006, which is incorporated by reference in its entirety herein. The filed invention is formed by a damascene process as described in US Patent Application No. 11 / 444,936 to Radigan et al., Which is a "conductive hard mask to protect patterned features during trench etching." . Rail 29 may be about 200 nm to about 400 nm thick.

Next, another insulating layer (not shown for clarity) is deposited between and on the conductor rails 29. The insulating material may be any known electrical insulating material such as silicon oxide, silicon nitride or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this insulating material. This insulating layer can be planarized with the top surface of the conductor rail 29 by CMP or etch back. A three-dimensional view of the resulting device is shown in FIG. 4.

Pillar devices, such as diode devices, may include one-time programmable (OTP) or rewritable nonvolatile memory devices. For example, each diode pillar 27 may act as a steering element of a memory cell, and another material or layer 31 serving as a resistive switching material (ie, storing data) is shown in FIG. 4. As shown, it is provided in series with the diode 27 between the electrodes 1, 29. Specifically, FIG. 4 shows antifuse (ie, antifuse dielectrics), fuses, polysilicon memory effect materials, metal oxides (such as nickel oxide, perovskite materials, etc.), carbon nanotubes, phase change materials, switchable composites. One nonvolatile memory cell including pillar diode 27 in series with a resistive switching material 31, such as a metal oxide, a conductive bridge element or a switchable polymer, is shown. A resistive switching material 31, such as a thin silicon oxide antifuse dielectric layer, may be deposited over the diode pillar 27, followed by the top electrode 29 on the antifuse dielectric layer. The antifuse dielectric 31 may also be formed by oxidizing the top surface of the diode 27 to form a 1-10 nm thick silicon oxide layer. Alternatively, the resistive switching material 31 may be located underneath the diode pillar 27 such as between the barrier 5 and another conductive layer, such as a TiN layer. In this embodiment, the resistance of the resistance switching material 31 is increased or decreased in response to the forward and / or reverse bias provided between the electrodes 1, 29.

In other embodiments, pillar diode 27 itself may be used as a data storage device. In this embodiment, the resistance of the pillar diode is described in US patent application Ser. No. 10 / 955,549, filed Sep. 29, 2004, both of which are incorporated by reference in their entirety (US Patent Application Publication 2005/0052951 A1). And the forward direction provided between the electrodes 1, 29 as described in US Patent Application No. 11 / 693,845 filed March 30, 2007 (corresponding to US Application Publication 2007/0164309 A1). Or by application of reverse bias. In this embodiment, the resistance switching material 31 can be omitted if necessary. Although nonvolatile memory devices have been described, other devices, such as other volatile or nonvolatile memory devices, logic devices, display devices, light emitting devices, detectors, and the like, can also be formed by the methods described above. Also, while the pillar-type device has been described as being a diode, other similar pillar-type devices such as transistors can also be formed.

The formation of the first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic three dimensional memory array. In some embodiments, the conductors may be shared between memory levels, ie, the top conductor 29 may function as the bottom conductor of the next memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level, the surface is planarized, and the configuration of the second memory level can be started on this planarized interlevel dielectric without any shared conductors.

Monolithic three-dimensional memory arrays are formed with multiple levels of memory on a single substrate, such as a wafer, without any board intervention. The layer forming one memory level is deposited or grown directly on top of an existing level or layers of levels. In contrast, stacked memories are constructed by forming memory levels on separate substrates and adhering these memory levels onto each other, such as in Leedy's US Pat. No. 5,915,167 "three-dimensional structure memory". The substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed on separate substrates, these memories are not truly monolithic three dimensional memory arrays.

The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height on the substrate and a second memory level formed at a second height different from the first height. Three, four, eight or virtually any number of memory levels can be formed over the substrate in such a multilevel array.

In a fourth embodiment of the present invention, alternative etching and doping steps are used to form pillared devices, such as diodes 27. In this embodiment, the etch selectivity of various types of polysilicon is used in the recess etch step to provide end point detection. Specifically, phosphorus-doped polysilicon has a faster etch rate than undoped silicon (data indicating that differently doped polysilicones have different etch rates is available at http://www.clarycon.com/Resources/Slide3t. jpg and http: www.clarycon.com/Resources/Slide5i.jpg). Etch rates from the aforementioned websites for phosphorus doped, boron doped and undoped polysilicon are shown in FIG. 5A.

The depth of the high etch rate n-type doped layer can be tailored according to the dosage and energy injected. One optical etch end point detection method includes monitoring a change in intensity of a wavelength that is characteristic for a particular reactant or product of the etching reaction. When the etch end point has been achieved, there will be a lower density of etch reaction product in the plasma, so that the end point can be triggered and stop the etch. Another etch end point detection uses a mass spectrometer for monitoring specific species in the exhaust stream from the dry etch reaction, called RGA (Residual Gas Analysis). The mass spectrometer may be located in or near the exhaust conduit of the etch reaction chamber. In this case, the RGA monitors phosphorus-containing species in the exhaust stream and provides an end point signal or a trigger for the drop of this signal.

In the method of the fourth embodiment, the first polysilicon layer 13 is undoped deposited (ie intrinsic) as shown in FIG. 5B. The layer 13 is then implanted with phosphorus to a predetermined depth before or after the layer 13 is planarized with the top surface of the insulating layer 9 to form the implant region 101 as shown in FIG. 5C. do. The implant depth is selected such that the bottom 103 of the phosphorus implant region 101 is located at or near the top surface of the region 17 shown in FIG. 3B. The intrinsic portion 105 of the first semiconductor layer 13 remains in the lower portion of the plurality of openings 11.

The first polysilicon layer 13 then uses an anisotropic plasma etch to recess the layer 13 in the opening 11 (eg, SF ₆ , CF ₄ , HBr / Cl ₂ or HBr / O ₂ plasma Is selectively etched). The phosphorus doped region 101 of the first polysilicon layer 13 is etched until the intrinsic portion 105 of the first polysilicon layer is reached, as shown in FIG. 5D. In other words, the bottom 103 of the phosphorus implant region 101 is reached during the etching step, optically or as detected by the RGA (thus, the intrinsic portion 105 of the first polysilicon layer 13 during the etching step). Is reached), the etching is stopped. In particular, when the bottom 103 of the phosphorus doped region 101 is reached, the intensity of the phosphorus characteristic wavelength in optical end point detection is reduced, or the amount of phosphorus containing species detected by the RGA is reduced. The remaining intrinsic portion 105 of the layer 13 in the opening 11 is then infused with phosphorus or arsenic into the portion 105 to form the n-type portion 17 as shown in FIG. 5E, and the like. re-doped with n-type dopant. A second semiconductor layer, such as intrinsic semiconductor layer 21, is then deposited on portion 17 as shown in FIG. 3C, and the process continues as in the third embodiment. To form a diode 27 having a p-type bottom region, the portion 105 is implanted with boron or BF ₂ after the recess etch. In addition, instead of using the phosphorus implant region for end point detection, a boron or BF ₂ implant region is used and the characteristic boron wavelength or RGA signal is monitored instead.

In addition, optical end point detection can be used to determine when layer 13 is planarized along with the top surface of insulating layer 9. After layer 13 is planarized, the top surface of insulating layer 9 is exposed. Thus, the optical signal on the surface changes from a polysilicon signal to a signal characteristic in which both polysilicon and insulator (such as silicon oxide) are present.

In a fifth embodiment of the invention, a sacrificial layer is used to form the pillared device. 6A-6G illustrate the steps of the method of the fifth embodiment.

First, a plurality of lower electrodes 1 are formed on the substrate as described above with respect to the previous embodiment. For example, a tungsten electrode 1 with a barrier 5 of the first and second embodiments may be provided (electrode 1 and barrier 5 are omitted from FIG. 6A for clarity and FIG. 6G Shown in the final device shown in FIG. Then, an insulating layer 9 comprising a plurality of openings 11 having a first width is provided over the electrode 1 and the barrier 5 (one opening 11 is shown in FIG. 6A for clarity). ). An optical hardmask layer 33 is also formed over the insulating layer 9. Thereafter, a first semiconductor region (such as an n-type polysilicon region) 17 of the first conductivity type is formed on the lower electrode. For example, the method of the third or fourth embodiment can be used to form the region 17. A sacrificial material 35 is then formed in the plurality of first openings 11. The sacrificial material can be any suitable dissolvable organic material used in double damascene through the first method. For example, a Wet Gap Fill (WGF) 200 material provided by Brewer Science, Inc. can be used as the sacrificial material 35. The apparatus of this stage of this process is shown in FIG. 6A.

Then, as shown in FIG. 6B, an optional antireflective layer 37, such as BARC layer 37m, is formed over insulating layer 9 and over optional hardmask 33. As shown in FIG. Thereafter, photoresist layer 39 is exposed and patterned over BARC layer 37. The apparatus of this stage of this process is shown in FIG. 6B.

As shown in FIG. 6C, the patterned photoresist is then subjected to a plurality of second openings 41 (one for clarity) in the insulating layer 9 to expose the sacrificial material 35 in the openings 11. Opening 41 is used as a mask to etch). The second opening 41 is wider than the first opening 11. A portion of the sacrificial material 35 may be etched during formation of the second opening. The second opening 41 includes a trench opening, and the sacrificial material is exposed at a portion of the bottom of the trench.

As shown in FIG. 6D, the sacrificial material is selectively removed from the first opening 11 through the second opening 41. Any suitable liquid etch material or developer is used to remove material 35 from opening 11 to expose n-type polysilicon region 17 in opening 11.

Thereafter, as shown in FIG. 6E, a second conductivity type second semiconductor region is formed in the first opening 11. For example, intrinsic polysilicon layer 21 may be formed over insulating layer 9 and in openings 11 and 41.

Thereafter, the polysilicon layer 21 is planarized and concave using the method described in the third embodiment. Preferably, the remaining portion 23 of the polysilicon layer 21 is concave so that its top surface is leveled with the top surface of the opening 11 (ie, the top of the portion 23 is the bottom of the trench 41). And leveling). P-type region 25 is then formed in intrinsic region 23 as described above in the third embodiment. The device of this stage is shown in FIG. 6F. Regions 17, 23, 25 form pillar-shaped diodes 27 in first opening 11.

Then, as shown in FIG. 6G, an upper electrode is formed in the trench 41 in the insulating layer 9 by a damascene process, so that the upper electrode is formed of the p-type semiconductor region 25 of the diode 27. Contact with The upper electrode includes a TiN adhesive layer 43 and a tungsten conductor 29. Thereafter, the upper electrode is planarized by CMP or etch back together with the upper surface of the insulating layer 9. If desired, the lower TiN adhesive layer 45 may also be formed under the lower electrode 1. The trench may be about 200 nm to about 400 nm deep and the diode 27 may be about 200 nm to about 400 nm high, such as about 250 nm high.

The pillared device may be formed using any one or more of the steps described above with respect to any one or more of the first through fifth embodiments. Depending on the process steps used, the finished device may have one or more of the following features shown in FIGS. 7A and 7B.

For example, as shown in FIG. 7A, the n-type region 17 of the diode 27 includes a first vertical junction 47, and the p-type region 25 (and of the diode 27). Intrinsic region 23 may include a second vertical seam 49. Junction lines 47 and 49 may be formed if the deposition of polysilicon layers 13 and 21 does not completely fill the opening 11 during a separate deposition step. The first vertical seam 47 and the second vertical seam 49 do not contact each other. The bond lines do not contact each other because the polysilicon layers 13 and 21 are deposited in separate steps as shown in FIGS. 3A-3E. Specifically, without being limited to a particular theory, since the bottom portion of the layer 21 can completely fill the opening 11, the bottom portion of the layer 21 in contact with the region 17 does not form a seam. It is believed. However, the seam may be omitted depending on the deposition process of the polysilicon layers 13 and 21.

Also, as also shown in FIG. 7A, the sidewalls 51 of the first conductivity type region (such as the n-type region 17) are the second conductivity type region (p-type region 25) of the diode and And / or have a different taper angle than the sidewalls 53 (such as intrinsic region 23). The discontinuities 55 are located on the sidewalls of the diode 27 where the tapered sidewalls 51 and 53 meet differently. In particular, the first conductivity type region 17 has a narrower taper angle than the second conductivity type region 25, and the discontinuities 55 are the intrinsic semiconductor region 23 and the n-type conductivity region 17. ) Is the step in the sidewall of the diode. Without being limited to a particular theory, different taper and discontinuities are possible because the recess etch back of the layer 13 shown in FIG. 3B is more isotropic than the step of etching the opening 11 in the insulating layer 9 shown in FIG. 3A. It is believed that additions can be made. Thus, during the etch back of the layer 13, the upper portion 19 of the opening 11 is also etched and wider than the lower portion of the opening 11. Thus, the layers 13 and 21 filling the lower and upper portions of the opening 11 respectively take different taper of each portion of the opening. Different taper and discontinuities can be avoided if the recess etch step of the layer 13 is performed without expanding the upper portion 19 of the opening.

When the barrier 5 is formed by nitriding the electrode 1 through the opening 11 in the insulating layer 9 as shown in FIG. 2B, it is then adjacent to at least one sidewall of the pillar-shaped diode 27. A portion of the insulating layer 9 which is positioned so as to be nitrided. For example, as shown in FIGS. 2B and 7A, where layer 9 is silicon oxide, then nitrided oxide or nitrogen containing silicon oxide regions 14, such as silicon oxynitride, may be formed around diodes 27. It is formed on the side wall 12 of the opening 11. In addition, if the upper portion of the insulating layer 9 adjacent to the p-type region 25 of the diode comprises a boron gradient, this is to form the region 25, as shown in FIGS. 3E and 7A. In addition to being implanted into the upper portion of the region 23, boron is implanted into the insulating layer 9.

FIG. 7B shows the inset portion of FIG. 7A around the barriers 5, 6. If the pillar-type diode is partially misaligned with the tungsten electrode as shown in Figs. 2A, 2B and 7B, then the tungsten nitride barrier 5 is located on the top surface of the tungsten electrode 1 and the tungsten nitride barrier ( 6) is located at least a part of the side wall of the tungsten electrode 1 as shown in FIG. 7B. Further, when the barrier 5 is formed by nitriding the tungsten electrode 1 prior to forming the insulating layer 9 as shown in Figs. 1C and 1D, at this time, a 1-10 nm thick nitrogen rich region 7 A thin nitrogen rich region such as) is formed on top of the lower insulating layer or material 3. For example, if layer 3 comprises an oxide such as silicon oxide, then its upper portion 7 is nitrided to form silicon oxynitride or nitrogen containing silicon oxide.

Another embodiment of the present invention provides a method of manufacturing a pillar device by selectively depositing germanium or germanium rich silicon germanium pillar into an opening previously formed in an insulating layer to overcome the limitation of the subtractive method used in the prior art. Selective deposition methods include providing electrically conductive materials such as titanium nitride, tungsten or other conductors exposed in the openings in the insulating layer. A silicon seed layer is then deposited on the titanium nitride. Thereafter, germanium or germanium rich silicon germanium (i.e., SiGe containing at least 50 atomic percent Ge) is selectively formed on the silicon seed layer at the opening, with no germanium or germanium rich silicon germanium deposited on the top surface of the insulating layer. Is deposited. This eliminates the oxide CMP or etch back step used in the subtractive method. Preferably the silicon seed layer and the germanium or germanium rich silicon germanium pillar are deposited by chemical vapor deposition at low temperatures such as below 440 ° C.

Electrically conductive materials such as titanium nitride can be provided in the openings by any suitable method. For example, in one embodiment, a titanium nitride layer is formed over the substrate and then photolithographically patterned in a pattern. Alternatively, other materials such as titanium tungsten or tungsten nitride may be used in place of titanium nitride. The pattern may comprise electrodes, such as rail-shaped electrodes. Thereafter, an insulating layer is formed on the titanium nitride pattern, such as a titanium nitride electrode. An opening is then formed in the insulating layer by etching to expose the titanium nitride pattern. In alternative embodiments, the conductive nitride pattern is selectively formed in openings in the insulating layer. For example, a titanium nitride or tungsten nitride pattern may be selectively formed in the opening in the insulating layer by nitriding the titanium or tungsten layer exposed at the bottom of the opening.

The pillar device may comprise part of any suitable semiconductor device, such as a diode, a transistor, or the like. Preferably the pillar device comprises a diode such as a p-i-n diode. In this embodiment, the step of selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening selectively deposits a first conductive type (such as n-type) semiconductor material into the opening to form a pin diode, and subsequently Thereby selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material and subsequently depositing a second conductivity type (such as p-type) germanium or germanium rich silicon germanium semiconductor material. Thus, all three regions of the p-i-n diode are selectively deposited into the openings. Alternatively, in a less preferred embodiment, instead of selectively depositing a second conductivity type semiconductor material, a second, such as p-type dopant, into the upper portion of the intrinsic germanium or germanium rich silicon germanium semiconductor material to form a pin diode. The diode can be completed by injecting a conductive dopant. Of course, the positions of the p-type and n-type regions can be reversed if necessary. To form a pn type diode, a first conductivity type (such as n-type) germanium or germanium rich silicon germanium semiconductor material is selectively deposited into the opening, followed by a second conductivity type (such as p-type) germanium Or a germanium rich silicon germanium semiconductor material is selectively deposited on the semiconductor material of the first conductivity type to form a diode.

8A-8D illustrate a preferred method of forming pillar devices using selective deposition.

Referring to FIG. 8A, an apparatus is formed over a substrate 100. Substrate 100 may be an IV-IV compound, such as monocrystalline silicon, silicon-germanium, or silicon-germanium-carbon, an III-V compound, an II-VI compound, an epitaxial layer on such a substrate, or any such as a glass, plastic, metal, or ceramic substrate. May be any semiconductor substrate known in the art, such as other semiconductor or non-semiconductor materials. The substrate may include integrated circuits fabricated thereon, such as drive circuits for memory devices. The insulating layer 102 is preferably formed on the substrate 100. Insulating layer 102 may be silicon oxide, silicon nitride, a high dielectric constant film, a Si—C—O—H film, or any other suitable insulating material.

The first electrically conductive layer 200 is formed over the substrate 100 and the insulating layer 102. Conductive layer 200 may comprise any conductive material known in the art, such as tungsten and / or other materials including aluminum, tantalum, titanium, copper, cobalt or alloys thereof. An adhesive layer may be included between the insulating layer 102 and the conductive layer to help adhesion of the conductive layer to the insulating layer 102.

A barrier layer 202, such as a TiN layer, is deposited on top of the first conductive layer 200. When the top surface of the first conductive layer 200 is tungsten, tungsten nitride may be formed on the top of the conductive layer 200 instead of TiN by nitriding the top surface of the tungsten. For example, the following conductive layer combinations may be used: Ti (bottom) / Al / TiN (top) or Ti / TiN / Al / TiN or Ti / Al / TiW or any combination of these layers. The bottom Ti or Ti / TiN layer acts as an adhesive layer, the Al layer may act as the conductive layer 200, and the top TiN or TiW layer may be an antireflective coating for patterning the barrier layer 202 and the electrode 204. As an optional polishing stop material for subsequent CMP of insulating layer 108 (when layer 108 is deposited in two steps), and as an optional silicon seed deposition substrate, as described below.

Finally, conductive layer 200 and barrier layer 202 are patterned using any suitable masking and etching process. In one embodiment, a photoresist layer is deposited over the barrier layer 202, patterned by photolithography, and the layers 200, 202 are etched using the photoresist layer as a mask. The photoresist layer is then removed using standard processing techniques. The resulting structure is shown in FIG. 8A. Conductive layer 200 and barrier layer 202 are patterned with rail-shaped bottom electrode 204 of the memory device. Alternatively, the electrode 204 may instead be formed by a damascene method, wherein at least the conductive layer 200 is formed in the groove in the insulating layer by deposition and subsequent planarization.

Next, referring to FIG. 8B, an insulating layer 108 is deposited between and on the electrodes 204. Insulating layer 108 may be any electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 108 is deposited in one step and then planarized by CMP for a predetermined amount of time to obtain a flat surface. Alternatively, insulating layer 108 may be deposited as two separate sublayers, where a first sublayer is formed between electrodes 204, and a second sublayer is formed over electrode 204 and the first sublayer. 1 is deposited over the sublayer. The first CMP step may be used to planarize the first sublayer using the barrier layer 202 as a polishing stop. The second CMP step may be used to planarize the second sublayer for a predetermined amount of time to obtain a flat surface.

The insulating layer 108 is then photolithographically patterned to form openings 110 that extend to and expose the top surface of the barrier 202 of the electrode 204. The opening 110 should have approximately the same pitch and approximately the same width as the electrode 204 below so that each semiconductor pillar 300 shown in FIG. 8C is formed on top of each electrode 204. Some misalignment is allowed. The resulting structure is shown in Figure 8b.

Referring to FIG. 8C, vertical semiconductor pillars 300 are selectively formed in openings 110 over TiN barrier 202. The semiconductor material of the pillar may be germanium or germanium rich silicon germanium. For brevity, this description describes the semiconductor material as germanium, but a skilled practitioner will understand that any suitable material may be selected instead.

Germanium pillar 300 may be selectively deposited by low pressure chemical vapor deposition (LPCVD) on a thin Si seed layer located over the TiN barrier as shown in FIG. 8C. For example, the method disclosed in U.S. Application No. 11 / 159,031 filed on Jun. 22, 2005, published as U.S. Application Publication 2006/0292301 A1, incorporated herein by reference, may be used to deposit Ge pillars. Can be. Preferably the entire pillar 300 is selectively deposited. In a less preferred embodiment, however, only about the first 20 nm of pillar 300 deposited on the seed layer / TiN barrier should have high selectivity for silicon dioxide to prevent sidewall shorting of the diode, with the rest of the pillar being non- May be optionally deposited.

For example, as shown in FIG. 9A, a thin Si seed layer is deposited on TiN by a 500 sccm flow of SiH ₄ for 60 minutes at a pressure of 1 Torr and 380 ° C. Thereafter, the silane flow is stopped and 100 sccm of GeH ₄ is flowed at the same temperature and pressure to deposit Ge. Ge may be deposited at a temperature below 380 ° C., for example 340 ° C. The SEM image of FIG. 9A shows that after 10 minutes deposition, about 40 nm of germanium was selectively deposited on the Si seed layer located on the TiN layer. As shown in FIG. 9B, no germanium deposition is observed on the SiO ₂ surface when the TiN layer is omitted. By using two-step deposition with both steps performed at temperatures below 380 ° C., Ge can be selectively deposited on TiN and not on adjacent SiO ₂ surfaces. An example of two-step deposition of planar Ge films is incorporated herein by reference. ratio. SB Herner's "Electrochmical and Solid-State Letters (9 (5) G161-G163) (2006)". Preferably, the silicon seed layer is deposited at a temperature below 440 ° C. and the germanium pillar is deposited at a temperature below 400 ° C.

In a preferred embodiment, the pillar comprises a semiconductor junction diode. The term junction diode is used herein to refer to a semiconductor device having non-ohmic conducting properties with two terminal electrodes, which is made of a semiconductor material that is p-type at one electrode and n-type at another electrode. Used. Examples include contacting n-type semiconductor materials and p-type semiconductor materials, such as pin diodes and Zener diodes, wherein the intrinsic (non-doped) semiconductor material is interposed between the p-type semiconductor material and the n-type semiconductor material. And pn diodes and np diodes.

Bottom high doped region 112 of diode 300 may be formed by selective deposition and doping. Germanium may be deposited and then doped, but by flowing a dopant containing gas (ie, in the form of phosphorus gas added to germanium gas) that provides n-type dopant atoms, such as phosphorus, during selective CVD of germanium It is preferred to be doped in situ. Highly doped region 112 may preferably be about 10 to about 80 nm thick.

Intrinsic diode region 114 may then be formed by a selective CVD method. Intrinsic region 114 deposition may be performed during a separate CVD step, or may be performed by stopping the flow of dopant gas, such as phosphorus, during the same CVD step as the deposition of region 112. The intrinsic region 114 may be about 110 to about 330 nm, preferably about 200 nm thick. A selective CMP process is then performed to remove any crosslinked intrinsic germanium on top of insulating layer 108 and to planarize the surface for preparation for subsequent lithography steps. Next, p-type upper region 116 is formed by a selective CVD method. The p-type top region 116 deposition may be performed during a separate CVD step from the region 114 deposition step, turning on the flow of dopant gas such as boron trichloride during the same CVD step as the region 114 deposition step. Can be carried out. P-type region 116 may be about 10 to about 80 nm thick. An optional CMP process may then be performed on the top of insulating layer 108 to remove any crosslinked p-type germanium and planarize the surface to prepare for subsequent lithography steps. Alternatively, p-type region 116 may be formed by ion implantation into the upper region of intrinsic region 114. Preferably, the p-type dopant is boron or BF ₂ . Formation of p-type region 116 completes formation of pillar-type diode 300. The resulting structure is shown in FIG. 8C.

In an exemplary embodiment, bottom region 112 is N ⁺ (highly doped n-type) and top region 116 is P ⁺ . However, vertical pillars may also include other structures. For example, bottom region 112 may be P ⁺ with N ⁺ top region 116. In addition, the intermediate region may be intentionally light doped or intrinsic or may not be intentionally doped. The undoped region is never completely electrically neutral and always has defects or contaminants, which causes the undoped region to behave as though it is slightly n-doped or p-doped. Such a diode can be considered a pin diode. ^{Thus, P + / N - / N} +, P + / P - a / P ⁺ or N ⁺ / P ^_ / P ⁺ diode may be formed ^{- / N +, N + /} N.

The pitch and width of the pillar 300 are formed by the opening 110 and may vary as needed. In one preferred embodiment, the pitch of the pillars (distance from the center of one pillar to the center of the next pillar) is about 300 nm, and the width of the pillars varies between about 100 and about 150 nm. In another preferred embodiment, the pitch of the pillars is about 260 nm and the width of the pillars varies between about 90 and about 130 nm. In general, the pillar 300 preferably has a substantially cylindrical shape having a circular or approximately circular cross section having a diameter of 250 nm or less.

Referring to FIG. 8D, the top electrode 400 is deposited, for example, as Ti (bottom) / Al / TiN (top) or Ti / TiN / Al / TiN or Ti / Al / TiW or any combination of these layers. This can be formed in the same manner as the bottom electrode 204. The TiN or TiW layer on the top can function as an antireflective coating for the patterning of the conductors and as a polishing stop material for subsequent CMP of the insulating layer 500 as will be discussed below. The conductive layer described above is patterned and etched using any suitable masking and etching technique to form a substantially flat, substantially coplanar conductor rail 400 extending perpendicular to the conductor rail 204. In a preferred embodiment, the photoresist is deposited, patterned by photolithography, the layer is etched, and then the photoresist is removed using standard processing techniques. Alternatively, an optional insulating oxide, nitride or oxynitride layer is formed on high doped region 116 and filed May 31, 2006, where conductor 400 is incorporated herein by reference in its entirety. It is formed by the damascene process described in US Pat. Appl. 11 / 444,936 to " Conductive Hard Mask to Protect Patterned Features During Trench Etching "

Next, another insulating layer 500 is deposited over and between the conductor rails 400. The layer 500 material may be any known electrically insulating material such as silicon oxide, silicon nitride or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this insulating material. This insulating layer may be planarized with the top surface of the conductor rail 400 by CMP or etch back. A three dimensional view of the resulting device is shown in FIG. 8E.

In the above description, the barrier layer 202 is formed before the insulating layer 108 is deposited. Alternatively, the order of the manufacturing steps can be changed. For example, an insulating layer 108 having an opening may first be formed on the conductor 204 prior to selectively forming a tungsten nitride pattern in the opening to facilitate later germanium or germanium rich silicon germanium deposition. .

Pillar devices, such as diode devices, may include one-time programmable (OTP) or rewritable nonvolatile memory devices. For example, each diode pillar 300 may act as a steering element of a memory cell, and another material or layer 118 that acts as a resistive switching material (ie, stores data), as shown in FIG. 8E. Between the electrodes 204, 400 is provided in series with the diode 300. In particular, FIG. 8E illustrates antifuse (ie, antifuse dielectrics), fuses, polysilicon memory effect materials, metal oxides (such as nickel oxide, perovskite materials, etc.), carbon nanotubes, phase change materials, switchable composites. One non-volatile memory cell including pillar diode 300 in series with a resistive switching material 118, such as a metal oxide, a conductive bridge element or a switchable polymer, is shown. A resistive switching material 118, such as a thin silicon oxide antifuse dielectric layer, may be deposited over the diode pillar 300, followed by the top electrode 400 on the antifuse dielectric layer. Alternatively, the resistive switching material 118 may be located under the diode pillar 300, such as between the conductive layers 200, 202. In this embodiment, the resistance of the resistive switching material 118 is increased or decreased in response to the forward and / or reverse bias provided between the electrodes 204, 400.

In other embodiments, pillar diode 300 itself may be used as a data storage device. In this embodiment, the resistance of pillar diode 300 is disclosed in US patent application Ser. No. 10 / 955,549, filed Sep. 29, 2004, the entirety of which is incorporated herein by reference. 0052951 A1) and US patent application Ser. No. 11 / 693,845 filed March 30, 2007 (corresponding to US application publication 2007/0164309 A1) provided between electrodes 204 and 400. Change by application of forward and / or reverse bias. In the present embodiment, the resistive switching material 118 can be omitted if necessary.

The formation of the first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic three dimensional memory array. In some embodiments, the conductor may be shared between memory levels, ie, the top conductor 400 may function as the bottom conductor of the next memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level, the surface is planarized, and the configuration of the second memory level can be started on this planarized interlevel dielectric without any shared conductors.

Monolithic three-dimensional memory arrays are formed with multiple levels of memory on a single substrate, such as a wafer, without any board intervention. The layer forming one memory level is deposited or grown directly on top of an existing level or layers of levels. In contrast, a stacked memory is constructed by forming memory levels on separate substrates and adhering these memory levels onto each other, as in Ridy's US Pat. No. 5,915,167 "three-dimensional structure memory". The substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed on separate substrates, these memories are not truly monolithic three dimensional memory arrays. In contrast to the process described in Leady, in an embodiment of the invention the diode shares a conductive wire or electrode between two adjacent layers. In this structure, the "bottom" diode will "orient" in the opposite direction to the diode in the "top" layer (ie, the same conducting layer of each diode is in electrical contact with the same wire or electrode located between the diodes). . In this structure, two diodes can share the wire between them, but still have no read or write disturb problem.

The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height on the substrate and a second memory level formed at a second height different from the first height. Three, four, eight or virtually any number of memory levels can be formed over the substrate in such a multilevel array.

In summary, a method of fabricating a germanium pillar device by selective deposition of Ge or Ge rich SiGe into openings etched in an insulating layer has been described. By filling the openings with semiconductor pillars, some difficulties of the conventional subtraction method are overcome and eight processing steps can be eliminated in a four layer device. For example, high aspect ratio oxide gap filling between pillars may be omitted, which allows for the deposition of simple blanket oxide films with good uniformity. Higher germanium pillars up to 8 microns in height can be fabricated in the deep openings in the insulating layer. Higher diodes reduce the reverse leakage of vertical devices. In addition, the alignment of the various layers becomes easier. All layers can be aligned to the main alignment mark without intermediate open frame etching.

Based on the teachings of the present invention, one of ordinary skill in the art is expected to readily practice the present invention. It is believed that the description of the various embodiments provided herein provides a broader discussion and detail of the invention to enable those skilled in the art to practice the invention. Although specific support circuits and fabrication steps have not been described in detail, such circuits and protocols are well known, and no particular advantage is provided by specific modifications of these steps with respect to the practice of the present invention. Also, it is believed that one of ordinary skill in the art will be able to practice the invention without undue experimentation, based on the teachings herein.

The foregoing detailed description has described only a few of the many possible implementations of the invention. For this reason, this detailed description is to be illustrative, and not restrictive. Modifications and variations of the embodiments described herein can be made without departing from the scope and concept of the invention based on the description provided herein. Only the following claims, including all equivalents, are intended to define the scope of the invention.

Claims (66)

In the method of manufacturing a semiconductor device,
Providing an insulating layer overlying the substrate, the insulating layer comprising a plurality of openings;
Forming a first semiconductor layer in the plurality of openings on the insulating layer and the insulating layer,
Removing the first portion of the first semiconductor layer,
A first conductive second portion of the first semiconductor layer remains under the plurality of openings in the insulating layer,
The upper part of the plurality of openings in the insulating layer is left uncharged
Removing the first portion of the first semiconductor layer;
Forming a second semiconductor layer over the insulating layer and the plurality of openings on the insulating layer;
Removing the first portion of the second semiconductor layer located above the insulating layer
Including,
The second conductive type second portion of the second semiconductor layer remains on top of the plurality of openings in the insulating layer to form a plurality of pillar-type diodes in the plurality of openings. The method of claim 1, wherein the first and second semiconductor layers comprise polycrystalline silicon, germanium, or silicon-germanium, but amorphous silicon, germanium, or silicon-germanium that is crystallized in a subsequent step. 3. The semiconductor device of claim 2 wherein the first and second semiconductor layers comprise a polysilicon layer, the first semiconductor layer comprises an in situ n-type doped polysilicon layer, wherein the openings in the insulating layer are no greater than 45 nm. Forming a positive photoresist on the insulating layer, exposing the photoresist to radiation using an attenuating phase shift mask, patterning the exposed photoresist, and patterning as a mask The opening is formed by etching the opening in the insulating layer using a photoresist. The method of claim 3, wherein the radiation comprises radiation having a wavelength of 193 nm. The method of claim 1, wherein removing the first portion of the first semiconductor layer comprises planarizing the first semiconductor layer along with an upper surface of the insulating layer, followed by a plurality of openings in the insulating layer. Selectively etching the first semiconductor layer remaining thereon. 6. The method of claim 5, wherein forming the first semiconductor layer comprises forming an intrinsic semiconductor layer and prior to or after planarizing the first semiconductor layer, wherein the intrinsic portion of the first semiconductor layer is formed of a plurality of openings. Injecting a dopant of a first conductivity type into the first semiconductor layer at a predetermined depth to remain at the bottom,
Selectively etching the first semiconductor layer comprises etching a doped portion of the first semiconductor layer until the intrinsic portion of the first semiconductor layer is reached. 7. The method of claim 6, further comprising: detecting when an intrinsic portion of the first semiconductor layer is reached during the selective etching step;
Doping the intrinsic portion of the first semiconductor layer with the dopant of the first conductivity type after the selective etching step.
Furthermore, the manufacturing method of a semiconductor device. The method of claim 1, wherein forming the second semiconductor layer comprises:
Forming the second semiconductor layer comprising an intrinsic semiconductor material over the insulating layer and over the plurality of openings;
Planarizing the second semiconductor layer with at least the top surface of the insulating layer using chemical mechanical polishing or etch back;
injecting a dopant of the second conductivity type into the upper section of the second portion of the second semiconductor layer to form a pin pillar diode.
The manufacturing method of a semiconductor device containing. 9. The method of claim 8, further comprising forming a silicon rich oxide layer or a silicon-germanium cover layer between the intrinsic and n-type regions of each diode. The method of claim 1, wherein removing the first portion of the first semiconductor layer comprises:
Planarizing the first semiconductor layer with the top surface of the insulating layer using chemical mechanical polishing or etch back with optical end point detection;
After the planarization step, the flattening layer is planarized to concave the first semiconductor layer in the plurality of openings in the insulating layer such that the second portion of the first semiconductor layer remaining in the plurality of openings has a substantially flat top surface. Selectively anisotropically etching the first semiconductor layer remaining on top of the plurality of openings in the insulating layer with a level etch front.
The manufacturing method of a semiconductor device containing. The method of claim 1, wherein removing the first portion of the first semiconductor layer comprises:
Planarizing the first semiconductor layer with the upper portion of the insulating layer using chemical mechanical polishing or etch back with optical end point detection;
After the planarizing step, the insulating layer may be recessed to recess the first semiconductor layer at the plurality of openings in the insulating layer such that the second portion of the first semiconductor layer remaining in the plurality of openings has an annular shape having a groove in the center portion. Selectively isotropically etching the first semiconductor layer remaining on top of the plurality of openings.
The manufacturing method of a semiconductor device containing. The method of claim 1,
The n-type region of the diode comprises a first vertical junction,
The p-type region of the diode comprises a second vertical junction,
The first and second vertical seam lines do not contact each other. The method of claim 1, further comprising forming an antifuse dielectric over and below the diode. The method of claim 1,
Forming a tungsten electrode under the insulating layer,
Nitriding the tungsten electrode to form a tungsten nitride barrier exposed in the plurality of openings in the insulating layer;
Furthermore, the manufacturing method of a semiconductor device. In the method of manufacturing a semiconductor device,
Forming a plurality of tungsten electrodes,
Nitriding the tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes;
Forming an insulating layer including a plurality of openings in the insulating layer to expose the tungsten nitride barrier to the plurality of openings;
Forming a plurality of semiconductor devices on a tungsten nitride barrier in the plurality of openings in the insulating layer
The manufacturing method of a semiconductor device containing. The manufacturing method of a semiconductor device according to claim 15, wherein the plurality of semiconductor devices include a plurality of pillar-type diodes. The method of claim 16, wherein the forming of the plurality of pillar-type diodes comprises:
Forming a first semiconductor layer of a first conductivity type in the openings on the insulating layer and the insulating layer,
Removing the first portion of the first semiconductor layer so that a second portion of the first semiconductor layer remains below the plurality of openings in the insulating layer and the tops of the plurality of openings in the insulator layer remain uncharged. Wow,
Forming a second conductivity-type second semiconductor layer over the plurality of openings in the insulating layer
The manufacturing method of a semiconductor device containing. 16. The method of claim 15,
The forming of the insulating layer includes forming the insulating layer on a plurality of tungsten electrodes, and subsequently forming a plurality of openings in the insulating layer to expose top surfaces of the plurality of tungsten electrodes. ,
The nitriding step is performed after forming the plurality of openings in the insulating layer such that the top surfaces of the plurality of tungsten electrodes are nitrided through the plurality of openings in the insulating layer. 19. The method of claim 18,
The plurality of openings in the insulating layer are partially misaligned with the plurality of tungsten electrodes,
Forming a plurality of openings exposing at least a portion of a sidewall of the tungsten electrode,
The nitriding step forms a tungsten nitride barrier on exposed portions of sidewalls of the plurality of tungsten electrodes and on an upper surface thereof. 16. The method of claim 15,
The nitriding step takes place prior to forming the nitride layer,
The step of forming the insulating layer includes forming the insulating layer on the tungsten nitride barrier, and subsequently forming a plurality of openings in the insulating layer to expose the top surface of the tungsten nitride barrier. And manufacturing method of semiconductor device. 21. The method of claim 20, wherein after forming the plurality of openings in the insulating layer, performing a second nitriding step to strengthen the tungsten nitride barrier and to nitride at least one sidewall of the plurality of openings in the insulating layer. The manufacturing method of a semiconductor device further including. 21. The method of claim 20, wherein the lower insulating layer separates adjacent tungsten electrodes from each other and the nitriding step nitrides the top surface of the lower insulating layer. The method of claim 15, wherein the nitriding step includes a plasma nitriding step. In the method of manufacturing a semiconductor device,
Forming a plurality of tungsten electrodes,
Selectively forming a plurality of conductive barriers on the exposed top surface of the tungsten electrode;
Forming an insulating layer comprising a plurality of openings such that a plurality of conductive barriers are exposed in the plurality of openings in the insulating layer;
Forming a plurality of semiconductor devices on the conductive barrier in the plurality of openings
The manufacturing method of a semiconductor device containing. 25. The method of claim 24, wherein the plurality of semiconductor devices comprise a plurality of pillar-type diodes. The method of claim 25,
Forming the plurality of pillar-type diodes,
Forming a first semiconductor layer of a first conductivity type in the openings on the insulating layer and the insulating layer,
The first portion of the first semiconductor layer is removed such that a second portion of the first semiconductor layer remains below the plurality of openings in the insulating layer and the tops of the plurality of openings in the insulator layer remain uncharged. To do that,
Forming a second conductivity type second semiconductor layer on the plurality of openings in the insulating layer;
The manufacturing method of a semiconductor device containing. 25. The method of claim 24, wherein forming a plurality of conductive barriers comprises selective atomic layer deposition of a barrier metal or metal alloy on the plurality of tungsten electrodes. 28. The method of claim 27, wherein the barrier metal or metal alloy comprises tantalum, niobium, or an alloy thereof. 25. The method of claim 24, wherein forming the plurality of conductive barriers comprises selectively plating a barrier metal or metal alloy on the plurality of tungsten electrodes. 25. The method of claim 24,
Forming the insulating layer includes forming the insulating layer on the plurality of tungsten electrodes, and subsequently forming a plurality of openings in the insulating layer to expose top surfaces of the plurality of tungsten electrodes. and,
Selectively forming a plurality of conductive barriers so that a plurality of conductive barriers are selectively formed on the top surfaces of the plurality of tungsten electrodes through the plurality of openings in the insulating layer, forming a plurality of openings in the insulating layer The manufacturing method of a semiconductor device made after this. The method of claim 30,
The plurality of openings in the insulating layer are partially misaligned with the plurality of tungsten electrodes,
Forming the plurality of openings exposes at least portions of the sidewalls of the tungsten electrode,
Selectively forming the plurality of conductive barriers forms a conductive barrier on exposed portions of sidewalls of the plurality of tungsten electrodes and on a top surface thereof. 25. The method of claim 24,
Selectively forming the plurality of conductive barriers is performed prior to forming the insulating layer,
The forming of the insulating layer includes forming an insulating layer on the plurality of conductive barriers, and subsequently forming the plurality of openings in the insulating layer to expose top surfaces of the plurality of conductive barriers. The manufacturing method of a semiconductor device. In the method of manufacturing a semiconductor device,
Forming a plurality of lower electrodes on the substrate,
Forming an insulating layer including a plurality of first openings having a first width such that the lower electrode is exposed to the first opening;
Forming a first semiconductor region of a first conductivity type in the first opening;
Forming a sacrificial material in the plurality of first openings over the first semiconductor region;
Forming a plurality of second openings in the insulating layer having a second width greater than a first width to expose the sacrificial material;
Removing the sacrificial material from the first opening through the second opening;
Forming a second conductivity-type second semiconductor region in the first opening;
Forming an upper electrode in the second opening in the insulating layer such that the upper electrode contacts the second semiconductor region.
Including,
And the first and second semiconductor regions form pillar-type diodes in the first openings. 34. The method of claim 33, further comprising forming an intrinsic third semiconductor region between the first and second semiconductor regions to form a p-i-n pillar diode. The method of claim 34,
The forming of the first semiconductor region may include forming a first semiconductor layer in the plurality of first openings on the insulating layer and the insulating layer, and subsequently, forming the first semiconductor region below the plurality of first openings. Removing a portion of the first semiconductor layer so that it remains and the tops of the plurality of first openings remain uncharged,
The forming of the second semiconductor region may include forming a second semiconductor layer over the insulating layer and the plurality of first openings over the insulating layer, and subsequently, forming a second semiconductor region in the insulating layer. Removing a portion of the second semiconductor layer located above the insulating layer so as to remain on top of the opening. A pillar-type semiconductor diode comprising a substrate, a region of a first conductivity type located above the substrate, and a region of a second conductivity type located above the region of the first conductivity type,
a) the region of the first conductivity type of the diode comprises a first vertical junction, the region of the second conductivity type of the diode comprises a second vertical junction, and the first and second junctions do not contact each other or , or
b) sidewalls of the region of the first conductivity type have a taper angle different from that of the region of the second conductivity type, and discontinuities are located on the sidewall of the diode. 37. The method of claim 36, wherein the region of the first conductivity type of the diode comprises a first vertical junction, the region of the second conductivity type of the diode comprises a second vertical junction, and the first and second junctions Pillar semiconductor diode, not in contact. 38. The pillar-type semiconductor diode of claim 37, further comprising an intrinsic semiconductor region located between the region of the first conductivity type and the region of the second conductivity type. 37. The pillar-type semiconductor diode of claim 36, wherein the sidewalls of the region of the first conductivity type have a different taper angle than the sidewalls of the region of the second conductivity type, wherein discontinuities are located on the sidewalls of the diode. 40. The method of claim 39,
The region of the first conductivity type has a taper angle narrower than that of the second conductivity type,
An intrinsic semiconductor region is located between the first and second conductivity-type regions,
A discontinuous portion includes a stepped portion on a sidewall of the diode between an intrinsic semiconductor region and a region of a first conductivity type. 37. The method of claim 36,
a) the region of the first conductivity type of the diode comprises a first vertical junction, the region of the second conductivity type of the diode comprises a second vertical junction, the first and second junctions do not contact each other,
b) sidewalls of the region of the first conductivity type have a taper angle different from sidewalls of the region of the second conductivity type, wherein discontinuities are located on the sidewalls of the diode. In a semiconductor device,
Substrate,
Tungsten electrode,
A tungsten nitride barrier on the tungsten electrode,
A pillar diode located on the tungsten nitride barrier;
The upper electrode on the pillar-type diode
It includes a semiconductor device. 43. The semiconductor device of claim 42, wherein the pillar diode comprises a p-i-n diode. 44. The semiconductor device of claim 43, wherein the pillared diode is partially misaligned with the tungsten electrode, and the tungsten nitride barrier is located on at least a portion of the sidewall of the tungsten electrode and on the top surface of the tungsten electrode. 44. The semiconductor device of claim 43, further comprising a first oxide insulating layer positioned around the diode, wherein a portion of the first oxide insulating layer positioned adjacent to at least one sidewall of the pillar-type diode is nitrided. 44. The semiconductor device of claim 43, further comprising a second oxide insulating layer positioned adjacent to a tungsten electrode, wherein an upper portion of the second oxide insulating layer is nitrided. As a method of manufacturing a pillar diode,
Forming a titanium nitride pattern on the substrate,
Forming an insulating layer on the titanium nitride pattern;
Forming openings in the insulating layer to expose the titanium nitride pattern;
Forming a silicon seed layer in the opening on the titanium nitride pattern;
Selectively depositing a first conductivity type germanium or germanium rich silicon germanium semiconductor material on the silicon seed layer in an opening,
Selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material on a germanium or germanium rich silicon germanium semiconductor material of a first conductivity type;
injecting a dopant of a second conductivity type into an upper portion of an intrinsic first conductivity type germanium or germanium rich silicon germanium semiconductor material to form a pin diode.
Including, the manufacturing method of a pillar diode. 48. The method of claim 47, wherein the semiconductor material is germanium. 48. The method of claim 47 wherein the semiconductor material is germanium rich silicon germanium. 48. The method of claim 47, further comprising forming an antifuse dielectric layer on or under the diode. In the method of manufacturing the pillar device,
Providing an insulating layer having an opening,
Selectively depositing germanium or germanium rich silicon germanium semiconductor material into openings to form the pillar device.
A method for producing a pillar device, comprising. 52. The method of claim 51, wherein the semiconductor material is germanium. 52. The method of claim 51, wherein the semiconductor material is germanium rich silicon germanium. 53. The method of claim 51, wherein titanium nitride, titanium tungsten or tungsten nitride is exposed in the opening in the insulating layer. 55. The method of claim 54, further comprising depositing a silicon seed layer on titanium nitride, titanium tungsten or tungsten nitride. 56. The method of claim 55, wherein the silicon seed layer is deposited by chemical vapor deposition at a temperature below 440 ° C. 56. The method of claim 55, wherein the semiconductor material is selectively deposited on a seed layer. 59. The method of claim 57, wherein the semiconductor material is selectively deposited by chemical vapor deposition at a temperature below 440 ° C. The method of claim 54,
Forming a titanium nitride, titanium tungsten or tungsten nitride pattern on the substrate,
Forming an insulating layer on the titanium nitride, titanium tungsten or tungsten nitride pattern;
Forming an opening in the insulating layer to expose the titanium nitride, titanium tungsten or tungsten nitride pattern.
Furthermore, the manufacturing method of a pillar apparatus. The method of claim 54,
Forming the insulating layer on a substrate;
Forming openings in the insulating layer;
Optionally forming a titanium nitride, titanium tungsten or tungsten nitride pattern in the opening.
Furthermore, the manufacturing method of a pillar apparatus. 53. The method of claim 51, wherein the pillar device comprises a diode. 62. The fabrication of a pillar device of claim 61 wherein selectively depositing germanium or germanium rich silicon germanium semiconductor material in the opening comprises selectively depositing germanium or germanium rich silicon germanium semiconductor material of a first conductivity type. Way. The method of claim 62,
Selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material into openings on the first conductivity type material;
injecting a dopant of a second conductivity type into the upper portion of the intrinsic germanium or germanium rich silicon germanium semiconductor material to form a pin diode.
Furthermore, the manufacturing method of a pillar apparatus. The method of claim 62,
Selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material on the first conductivity type semiconductor material into the opening;
selectively depositing a second conductivity type germanium or germanium rich silicon germanium semiconductor material into the opening on the intrinsic germanium or germanium rich silicon germanium semiconductor material to form a pin diode
Furthermore, the manufacturing method of a pillar apparatus. 62. The method of claim 61, further comprising forming an antifuse dielectric layer on or under the diode. 62. The method of claim 61, wherein the pillar device is a nonvolatile memory device.

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