KR100665227B1 - Phase change memory device and fabricating method for the same - Google Patents

Abstract

A phase change memory device and a method of manufacturing the same are provided to pattern a phase change material in a line type by disposing the phase change material parallel with a word line. A phase change memory device includes a semiconductor substrate, bit lines(BL0,BL1,BL2,BL3) and word lines disposed on the semiconductor substrate in a cross direction, and a phase change material strip(152) disposed between the bit lines and the word lines and being substantially parallel with the word lines. The phase change material strip is substantially parallel with at least one portion of the word lines. The phase change material strip has at least two resistance values in response to a current penetrating the material.

Description

Phase change memory device and fabricating method for the same

1 and 2 are block diagrams and circuit diagrams illustrating a phase change memory device according to an exemplary embodiment of the present invention.

3A is a layout diagram illustrating a phase change memory device according to an embodiment of the present invention.

FIG. 3B is a cross-sectional view taken along line BB ′ of FIG. 3A.

3C is a cross-sectional view taken along line CC ′ in FIG. 3A.

3D is a perspective view illustrating a phase change memory device according to an embodiment of the present invention.

4 is a perspective view illustrating a phase change memory device according to another exemplary embodiment of the present invention.

5 is a perspective view illustrating a phase change memory device according to still another embodiment of the present invention.

6A to 8C are layout diagrams and cross-sectional views of intermediate manufacturing processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

 (Explanation of symbols for the main parts of the drawing)

1: Phase change memory device 10_1, 10_2: Row decoder

20_1, 20_2: column decoder 30_1, 30_2, 30_3, 30_4: input / output circuit

100_1, 100_2, 100_3, 100_4: memory bank

BLKi; i = 0 to 7: memory block GBLj; j = 0 to n: Global bit line

BL0, BL1, BL2, BL3: Bit Line

YSELk; k = 0 to 3: column select transistor

DCHk; k = 0 to 3: discharge transistor

110 semiconductor substrate 120 lower mold film pattern

130: upper mold layer pattern 132: first semiconductor pattern

134: second semiconductor pattern 140: insulating film pattern

142 lower electrode contact 152 strip of phase change material

154: barrier layer

The present invention relates to a phase change memory device, and more particularly, to a phase change memory device with improved endurance and a method of manufacturing the same.

Phase change random access memory (PRAM) stores data using a phase change material such as a chalcogenide alloy that is changed to a crystalline or amorphous state while being cooled after heating. That is, because the phase change material in the crystal state has low resistance and the phase change material in the amorphous state has high resistance, the crystal state is defined as set or logic level 0, and the amorphous state is reset or logic level 1 Can be defined as

The phase change memory device includes a plurality of phase change memory cells respectively formed in regions where bit lines and word lines cross each other. Here, the phase change memory cell includes a phase change material whose resistance changes according to the through current, and an access element (eg, a cell diode) that controls the through current flowing through the phase change material.

A conventional phase change memory device is formed by etching a phase change material to be independent of each phase change memory cell. However, the phase change material is very sensitive to the etching process may cause defects. The phase change material needs to have good durability to maintain its properties against repeated write and / or read operations, and defects caused by the etching process reduce this durability.

In addition, in order to manufacture a large-capacity and highly integrated phase change memory device, it is necessary to reduce the size of the phase change memory cell by reducing design rules. However, it is difficult to process the phase change material independently for each phase change memory cell. .

An object of the present invention is to provide a phase change memory device having improved durability.

Another object of the present invention is to provide a method of manufacturing a phase change memory device having improved durability.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A phase change memory device according to an embodiment of the present invention for achieving the technical problem is located between a bit line and a word line, and a bit line and a word line disposed to cross each other on the semiconductor substrate, the word line, And a substantially parallel phase change material strip.

According to another aspect of the present invention, there is provided a phase change memory device including a semiconductor substrate, a plurality of bit lines extending in a first direction on the semiconductor substrate, and a separate arrangement along the first direction on each bit line. A plurality of cell diodes, a plurality of phase change material strips extending in a second direction to intersect a plurality of bit lines on the plurality of cell diodes, each phase change material strip being a plurality of phases electrically connected to the plurality of cell diodes A change material strip, and a plurality of word lines formed on the plurality of phase change material strips, each word line comprising a plurality of word lines substantially parallel to each phase change material strip.

According to another aspect of the present invention, there is provided a method of manufacturing a phase change memory device, wherein a plurality of bit lines extending in a first direction are formed on a semiconductor substrate, and a first direction is formed on each bit line. Forming a plurality of cell diodes arranged separately along the plurality of cell diodes, and forming a plurality of phase change material strips and a plurality of word lines extending in a second direction to intersect the bit lines on the plurality of cell diodes; And each word line is formed to be substantially parallel.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

As used herein “and / or” includes each and all combinations of one or more of the items mentioned.

1 and 2 are block diagrams and circuit diagrams for describing a phase change memory device according to example embodiments. In the embodiments of the present invention, four memory banks are exemplified for convenience of description, but the present invention is not limited thereto. In addition, in FIG. 2, only an area associated with the first memory block BLK0 is illustrated for convenience of description.

Referring to FIG. 1, the phase change memory device 1 may include memory banks 100_1, 100_2, 100_3, and 100_4, row decoders 10_1 and 10_2, column decoders 20_1 and 20_2, and input / output circuits 30_1 and 30_2. 30_3, 30_4).

The memory banks 100_1, 100_2, 100_3, and 100_4 each include a plurality of phase change memory cells arranged in a matrix form. In addition, each memory bank 100_1, 100_2, 100_3, and 100_4 includes a plurality of memory blocks BLKi (i = 0 to 7). In an embodiment of the present invention, a case in which eight memory blocks BLKi (i = 0 to 7) is included as an example is not limited thereto.

The row decoders 10_1 and 10_2 are disposed corresponding to the two memory banks 100_1, 100_2 or 100_3 and 100_4 to designate row addresses in the memory banks 100_1, 100_2, 100_3 and 100_4. For example, the row decoder 10_1 may select row addresses of the first and second memory banks 100_1 and 100_2.

In addition, the column decoders 20_1 and 20_2 are disposed corresponding to the two memory banks 100_1, 100_3 or 100_2 and 100_4 to designate column addresses in the memory banks 100_1, 100_2, 100_3 and 100_4. For example, the column decoder 20_1 may select column addresses of the first and third memory banks 100_1 and 100_3.

The input / output circuits 30_1, 30_2, 30_3, 30_4 are disposed corresponding to the memory banks 100_1, 100_2, 100_3, 100_4, and write and / or read operations in each memory bank 100_1, 100_2, 100_3, 100_4. Do it. That is, although not shown in the drawing, the input / output circuits 30_1, 30_2, 30_3, and 30_4 may include a write circuit and / or a read circuit.

Referring to FIG. 2, a phase change memory device 1 according to an embodiment of the present invention may include a memory block BLK0, a plurality of global bit lines GBLj (j = 0 to n), and a plurality of bit lines BL0, BL1, BL2, BL3, column select transistors YSELk (k = 0 to 3), and discharge transistors DCHk (k = 0 to 3).

The memory block BLK0 includes a plurality of phase change memory cells Cp. The plurality of phase change memory cells Cp are positioned in areas where word lines WL00 and WL0n and bit lines BL0, BL1, BL2, and BL3 cross each other, and in particular, the plurality of bit lines BL0, BL1, BL2, and BL3. ) May be branched by being connected to each global bit line (GBLj; j = 0 to n) to have a hierarchical bit line structure. In detail, the plurality of global bit lines GBLj (j = 0 to n) may be formed to extend in one direction to be common to the plurality of memory blocks (BLKi; i = 0 to 7 of FIG. 1). The plurality of bit lines BL0, BL1, BL2, and BL3 are selectively connected to the global bit lines GBLj; j = 0 to n through column select transistors YSELk; k = 0 to 3, respectively. A plurality of phase change memory cells Cp are connected to BL0, BL1, BL2, and BL3.

The phase change memory cell Cp changes to a crystalline state or an amorphous state according to the through current, and controls the through current flowing through the phase change material Rp and the phase change material Rp having different resistances in each state. An access element D is included. The phase change material Rp is connected between the word lines WL00 and WL0n and the access device D, and the anode is connected to the bit lines BL0, BL1, BL2, and BL3 as the access device D. The cathode may use a cell diode connected to the phase change material Rp.

The column select transistors YSELk (k = 0 to 3) may operate on the global bit lines GBLj (j = 0 to n) and the bit lines BL0, BL1, BL2, in response to the column select signals YSi (i = 0 to 3). Selectively connect BL3). Here, the column select signal YSi (i = 0 to 3) is turned on by a signal obtained by decoding the column address and block information.

The discharge transistor DCHi i = 0 to 3 discharges the voltages of the bit lines BL0, BL1, BL2, and BL3 before and after the write operation or the read operation. The discharge transistor DCHk (k = 0 to 3) is formed between the bit lines BL0, BL1, BL2, and BL3 and the ground voltage, in response to the complementary signal YSBi (i = 0 to 3) of the column select signal. Since it discharges, it turns on when the column select transistor YSELk (k = 0-3) is turned off.

Hereinafter, the operation of the phase change memory device 1 will be described with reference to FIG. 2.

First, the write operation of the phase change memory device 1 heats the phase change material Rp to a melting temperature (Tm) or higher and then rapidly cools it to an amorphous state of logic level 1, or the crystallization temperature ( After crystallization (Tx) or more, it is heated to a temperature below the melting point (Tm), and then maintained at a temperature for a predetermined time, followed by cooling to a crystal state of logic level 0. Here, in order to phase change the phase change material Rp, a fairly high level of write current penetrates the phase change material Rp. For example, a write current for resetting is provided with a magnitude of about 1 mA. It is provided with a magnitude of about 0.6 to 0.7 mA of the write current for setting. This write current is provided from a write circuit (not shown) to provide global bit lines GBLj (j = 0 to n), bit lines (BL0, BL1, BL2, BL3), cell diodes (D), and phase change materials (Rp). After that, the word lines WL00 and WL0n exit.

On the other hand, the read operation of the phase change memory device 1 reads the stored data by providing the phase change material Rp with a read current having a level at which the phase change material Rp does not phase change. This read current is provided from a read circuit (not shown) to provide global bit lines GBLj (j = 0 to n), bit lines BL0, BL1, BL2, BL3, cell diodes (D), and phase change materials (Rp). After that, the word lines WL00 and WL0n exit.

FIG. 3A is a layout diagram illustrating a phase change memory device according to an exemplary embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line BB ′ of FIG. 3A, and FIG. 3D is a perspective view illustrating a phase change memory device according to an embodiment of the present invention. In FIG. 3D, an interlayer insulating film, an intermetallic insulating film, and the like are omitted for convenience of description. In addition, one embodiment of the present invention has a bit line over word line structure.

3A to 3D, a plurality of openings 121 exposing an upper surface of a predetermined region of the semiconductor substrate 110 are formed on the semiconductor substrate 110 of the first conductivity type (eg, P-type). The lower mold layer pattern 120 is disposed. The semiconductor substrate 110 may be a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display.

In addition, the lower mold layer pattern 120 may be formed of a silicon oxide layer (SiOx), for example, a flexible OXide (FOX), a Tonen SilaZene (TOSZ), an undoped Silicate Glass (USG), a Boro Silicate Glass (BSG), and a Phospho Silicate (PSG). Glass (BPSG), BoroPhospho Silicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS), Fluoride Silicate Glass (FSG), and high density plasma (HDP).

The plurality of openings 121 of the lower mold layer pattern 120 may be filled with a plurality of bit lines BL0, BL1, BL2, and BL3. Since the plurality of openings 121 extend in the first direction, the filled bit lines BL0, BL1, BL2, and BL3 also extend in the first direction to be formed. In addition, the plurality of bit lines BL0, BL1, BL2, and BL3 may be the same conductive type (eg, P-type) as the semiconductor substrate 110. Here, the impurity concentration of the bit lines BL0, BL1, BL2, and BL3 may be higher than 1 * 10 ¹⁹ atoms / cm ³ , but is not limited thereto. Meanwhile, the plurality of bit lines BL0, BL1, BL2, and BL3 may be epitaxial layers. In this case, when the single crystal semiconductor substrate 110 is used, the plurality of bit lines BL0, BL1, BL2, and BL3 also become single crystals.

A plurality of openings 131 exposing upper surfaces of predetermined regions of the plurality of bit lines BL0, BL1, BL2, and BL3 on the plurality of bit lines BL0, BL1, BL2, BL3, and the lower mold layer pattern 120. The upper mold layer pattern 130 having the) is disposed. The upper mold layer pattern 130 may be a silicon oxide layer (SiOx) in the same manner as the lower mold layer pattern 120, but is not limited thereto. For example, the upper mold layer pattern 130 may be a silicon nitride layer such as SiN or SiON.

The plurality of openings 131 of the upper mold layer pattern 130 are formed on the plurality of first semiconductor patterns 132 having the first conductivity type (eg, P-type) and on each of the first semiconductor patterns 132. A plurality of second semiconductor patterns 134 stacked and having a second conductivity type (eg, N type) are filled. In detail, each of the first and second semiconductor patterns 132 and 134 may have a first direction (bit line BL0, on each bit line BL0, BL1, BL2, BL3) along the positions of the plurality of openings 131. Along the extension direction of BL1, BL2, BL3).

The first and second semiconductor patterns 132 and 134 constitute a cell diode D. Here, the plurality of first semiconductor patterns 132 may have a lower impurity concentration than the plurality of bit lines BL0, BL1, BL2, and BL3. In addition, an impurity concentration of the second semiconductor pattern 134 may be higher than that of the first semiconductor pattern 132. This is to reduce the leakage current flowing through the reverse biased cell diode when the cell diode D is subjected to reverse bias. The reverse bias may be applied to the cell diode D of the unselected phase change memory cell upon writing or reading.

Meanwhile, the first and second semiconductor patterns 132 and 134 may be epitaxial layers. In this case, the first and second semiconductor patterns 132 and 134 may be single crystals like the bit lines BL0, BL1, BL2, and BL3.

In the drawing, only the case where the first and second semiconductor patterns 132 and 134 are filled in the plurality of openings 131 of the upper mold layer pattern 130 is described as an example, but the second semiconductor pattern 134 in the plurality of openings 131 is illustrated. The conductive plug may optionally be further filled on). Such conductive plugs may be metal plugs with ohmic contacts. For example, the conductive plug may be a tungsten plug.

An insulating layer pattern 140 including a plurality of contact holes 141 is disposed on the plurality of cell diodes D and the upper mold layer pattern 130. The insulating layer pattern 140 may be an oxide layer SiOx. The contact hole 141 is filled with a bottom electrode contact (BEC) 142. The lower electrode contact 142 may use TiN, for example.

A plurality of phase change material strips 152 connected to the plurality of contact holes 141 are disposed on the lower electrode contact 142. The plurality of phase change material strips 152 extend in a second direction to intersect the plurality of bit lines BL0, BL1, BL2, BL3. That is, the phase change material strips 152 are not arranged in units of phase change memory cells but correspond to the plurality of phase change memory cells arranged in the second direction.

As the phase change material constituting the phase change material strip 152, GaSb, InSb, InSe. _{Sb 2 Te 3, GeTe, AgInSbTe} , (GeSn) a compound the three compounds a GeSbTe _{elements, GaSeTe, InSbTe, SnSb 2 Te} 4, InSbGe, 4 -element SbTe, GeSb (SeTe), Te 81 Ge 15 Sb 2 Various kinds of materials such as S ₂ can be used. Of these, GeSbTe made of germanium (Ge), antimony (Sb), and tellurium (Te) can be mainly used.

The barrier layer 154 may be disposed on the phase change material strip 152. The barrier layer 154 prevents the phase change material constituting the phase change material strip 152 and the material of the word lines WL00 and WL0n from diffusing with each other. The barrier layer 154 may be configured by, for example, stacking Ti / TiN.

Word lines WL00 and WL0n are disposed on the barrier layer 154 to extend in parallel with the phase change material strip 152 and intersect the bit lines BL0, BL1, BL2, and BL3. In the exemplary embodiment of the present invention, only the case where the phase change material strip 152 extends completely parallel to the word lines WL00 and WL0n is described. However, a part of the phase change material strip 152 may be the word lines WL00 and WL0n. It is apparent to those skilled in the art that the case of extending in parallel with is possible. In addition, the word lines WL00 and WL0n may use, for example, aluminum (Al) or tungsten (W).

In particular, when the phase change material strip 152 is parallel to the word lines WL00 and WL0n as shown in FIGS. 3A to 3D, the following advantages are provided.

Since the phase change material strip 152 of the phase change memory device 1 is disposed to correspond to a plurality of phase change memory cells, the phase change material may be patterned in a line type. The etching process is simpler and more accurate than when the phase change material is disposed in units of phase change memory cells (that is, when patterning in a dot type). Therefore, the stress on the phase change material is reduced, so that the endurance of maintaining the characteristics against repeated writing and / or reading operations is excellent.

In particular, in the write operation of the phase change memory device 1, as described above, a significantly high level of write current is provided to the phase change material in order to phase change the phase change material. However, in the exemplary embodiment of the present invention, when the phase change material strips 152 are arranged in parallel with the word lines WL00 and WL0n, specifically, bits of the first conductivity type (P type) as shown in FIG. 3D. When the cell diode D is disposed on the lines BL0, BL1, BL2, and BL3, and the phase change material and the word lines WL00 and WL0n are disposed on the cell diode D, the bit lines BL0 and BL1 are disposed. Since a fairly high level of write current provided through BL2 and BL3 reaches the phase change material through the cell diode D, the stress applied to the phase change material can be reduced.

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4 is a perspective view illustrating a phase change memory device according to another exemplary embodiment of the present invention. Like reference numerals denote components that are substantially the same as FIG. 3D, and detailed descriptions of the corresponding components will be omitted.

Referring to FIG. 4, a phase change memory device 2 according to another embodiment of the present invention is located on a plurality of word lines WL00 and WL0n, and electrically connected to each of the bit lines BL0, BL1, BL2, and BL3. It further comprises a plurality of metal lines (ML0, ML1, ML2, ML3) each connected. The plurality of metal lines ML0, ML1, ML2, and ML3 may be substantially parallel to the plurality of bit lines BL0, BL1, BL2, and BL3, respectively.

The metal lines ML0, ML1, ML2, and ML3 may improve signal characteristics transmitted along the bit lines BL0, BL1, BL2, and BL3. Since the phase change memory device 2 according to the embodiment of the present invention uses the epitaxial layer of the first conductivity type as the bit lines BL0, BL1, BL2, and BL3, the phase change memory device 2 is highly integrated. Accordingly, signal characteristics transmitted along the bit lines BL0, BL1, BL2, and BL3 may be deteriorated. However, in another embodiment, the metal lines ML0, ML1, ML2, and ML3 that are electrically connected to the bit lines BL0, BL1, BL2, and BL3 and have a lower resistance than the bit lines BL0, BL1, BL2, and BL3. Since the signal is simultaneously transmitted through the signal characteristic can be improved.

5 is a perspective view illustrating a phase change memory device according to still another embodiment of the present invention.

Referring to FIG. 5, a phase change memory device 3 according to another embodiment of the present invention has a word line over bit line structure.

In detail, the plurality of word lines WL00 and WL0n may extend in the second direction, and the barrier layer 254 may be disposed on the word lines WL00 and WL0n. A phase change material strip 252 is disposed on the barrier layer 254 extending in parallel with the plurality of word lines WL00 and WL0n. That is, the phase change material strip 252 is not disposed in each phase change memory cell unit but is disposed to correspond to the plurality of phase change memory cells arranged in the second direction. Meanwhile, a plurality of electrode contacts 242 are arranged along the extending direction of each phase change material strip 252. The cell diodes D are separately disposed on the electrode contacts 242, and the cell diodes D are formed of semiconductor patterns 232 and 234 of different conductivity types. A plurality of bit lines BL0, BL1, BL2, and BL3 are formed on the plurality of cell diodes D and extend in the first direction to intersect the plurality of word lines WL00 and WL0n.

Hereinafter, a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 6A to 8C and 2A to 2D. 6A to 8C are layout diagrams and cross-sectional views of intermediate manufacturing processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

First, referring to FIGS. 6A to 6C, an upper surface of a predetermined region of the semiconductor substrate 110 is exposed on the first conductivity type (eg, P-type) semiconductor substrate 110 and extends in the first direction. The lower mold layer pattern 120 having the plurality of openings 121 formed thereon is formed.

7A through 7C, a plurality of bit lines BL0, BL1, BL2, and BL3 are formed to fill the plurality of openings 121 of the lower mold layer pattern 120.

In detail, the plurality of bit lines BL0, BL1, BL2, and BL3 have a selective epitaxial growth (SEG) using the semiconductor substrate 110 exposed by the lower mold layer pattern 120 as a seed layer. It can be grown using the method. Here, in the case of the single crystal semiconductor substrate 110, the grown epitaxial layer also becomes a single crystal.

Alternatively, the plurality of bit lines BL0, BL1, BL2, and BL3 may be formed using a solid phase epitaxial growth (SPE) method. Specifically, a polycrystalline semiconductor layer or an amorphous semiconductor layer is formed to fill a plurality of openings of the lower mold layer pattern 120, and the formed semiconductor layer is formed on the lower mold layer pattern 120. Flatten so that the top surface is exposed. Thereafter, the grown polycrystalline or amorphous semiconductor layer is changed into a single crystal by injecting an ion beam at a temperature of about 400 ° C.

As such, when a plurality of bit lines BL0, BL1, BL2, and BL3 are formed using selective epitaxial growth or solid state epitaxial growth, the plurality of openings 121 of the lower mold layer pattern 120 may be formed. By essentially preventing any voids or seams from being formed, the resistance of the bit lines BL0, BL1, BL2, BL3 can be reduced.

Subsequently, a plurality of bit lines BL0, BL1, BL2, and BL3 are completed by ion implanting impurities of the first conductivity type into the entire surface of the semiconductor substrate 110 on which the epitaxial layer is grown. Here, the impurity concentration of the plurality of bit lines BL0, BL1, BL2, and BL3 may be formed to be higher than 1 * 10 ¹⁹ atoms / cm ³ , but is not limited thereto. However, when impurities are doped in situ during selective epitaxial growth or solid state epitaxial growth, the ion implantation process may be omitted.

Next, a plurality of openings exposing upper surfaces of predetermined regions of the plurality of bit lines BL0, BL1, BL2, and BL3 on the plurality of bit lines BL0, BL1, BL2, BL3, and the lower mold layer pattern 120. An upper mold layer pattern 130 including the 131 is formed. A plurality of openings 131 of the upper mold layer pattern 130 are arranged along the extending direction of each bit line BL0, BL1, BL2, and BL3. In addition, the opening 131 may be formed to have a width smaller than that of the bit lines BL0, BL1, BL2, and BL3 in order to prevent misalignment with the lower bit lines BL0, BL1, BL2, and BL3.

8A through 8C, the first and second semiconductor patterns 132 and 134 are formed to fill the plurality of openings 131 of the upper mold layer pattern 130, thereby forming the plurality of cell diodes D. Complete

In detail, the first and second semiconductor patterns 132 and 134 may be grown using a selective epitaxial growth method, and the first semiconductor pattern 132 may be exposed by the upper mold layer pattern 130. The lines BL0, BL1, BL2, and BL3 may be grown as seed layers, and the second semiconductor pattern 134 may be grown using the first semiconductor patterns 132 as seed layers. Here, when the bit lines BL0, BL1, BL2, and BL3 are single crystals, the grown first and second semiconductor patterns 132 and 134 also become single crystals.

Alternatively, the first and second semiconductor patterns 132 and 134 may be formed using a solid phase epitaxial growth (SPE) method.

Subsequently, the first semiconductor pattern 132 is ion implanted with impurities of the first conductivity type, and the second semiconductor pattern 134 is ion implanted with impurities. Here, the first semiconductor pattern 132 may have a lower impurity concentration than the bit lines BL0, BL1, BL2, and BL3, and the impurity concentration of the second semiconductor pattern 134 may be higher than that of the first semiconductor pattern 132. have. However, when impurities are doped in situ during selective epitaxial growth or solid state epitaxial growth, the ion implantation process may be omitted.

Although not illustrated, a conductive plug may be further formed on the second semiconductor pattern 134 to fill the plurality of openings 131 of the upper mold layer pattern 130. In this case, the first and second semiconductor patterns 134 fill only the lower regions of the plurality of openings 131 of the upper mold layer pattern 130, and the conductive plugs are filled in the upper regions.

Next, an insulating layer pattern 140 including a plurality of contact holes 141 is formed on the plurality of cell diodes D and the upper mold layer pattern 130.

Thereafter, a bottom electrode contact (BEC) 142 filling the plurality of contact holes 141 is formed.

Referring again to FIGS. 2A through 2D, a phase change material layer, a barrier material layer, and a conductive layer for a word line are sequentially stacked on the lower electrode contact 142 and the insulating layer pattern 140, and patterned to form a word line WL00. , WL0n), barrier layer 154, and phase change material strip 152. The plurality of phase change material strips 152 and the plurality of word lines WL00 and WL0n extend parallel to each other and intersect with the bit lines BL0, BL1, BL2, BL3.

As such, since the phase change material of the phase change memory device 1 is patterned in a line type, the etching process is simple and the accuracy is increased. Thus, the stress of the phase change material is reduced, and the durability to maintain its properties against repeated writing and / or reading operations is excellent.

In the manufacturing method of the exemplary embodiment of the present invention, only the case where the phase change material strip 152 extends completely parallel to the word lines WL00 and WL0n is described. It is apparent to those skilled in the art that the case of extending parallel to WL0n) is possible.

In addition, from the manufacturing method of the phase change memory device according to an embodiment of the present invention, those skilled in the art to which the present invention pertains to the manufacturing method of another embodiment and another embodiment can be sufficiently technically inferred, the description thereof is omitted. do.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the phase change memory device as described above, there are one or more of the following effects. Since the phase change material is disposed parallel to the word line, the phase change material may be patterned in a line type. Accordingly, the etching process is simpler and more accurate than when the phase change material is disposed in units of phase change memory cells (that is, when patterning in a dot type). Therefore, the stress on the phase change material is reduced, so that the endurance of maintaining the characteristics against repeated writing and / or reading operations is excellent.

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Claims (23)

Semiconductor substrates; Bit lines and word lines disposed on the semiconductor substrate to cross each other; And And a phase change material strip positioned between the bit line and the word line and substantially parallel to the word line. The method of claim 1, And the phase change material strip is substantially parallel to at least a portion of the word line. The method of claim 1, And the phase change material strip has at least two resistance values in response to a through current passing through the phase change material. The method of claim 3, wherein The phase change material includes germanium (Ge), antimony (Sb), and tellurium (Te). The method of claim 3, wherein And an access element disposed between the phase change material strip and the bit line to control the through current. The method of claim 1, And the word line is disposed on the bit line. The method of claim 1, And the bit line is disposed on the word line. Semiconductor substrates; A plurality of bit lines extending in a first direction on the semiconductor substrate; A plurality of cell diodes arranged separately on the bit lines in the first direction; A plurality of phase change material strips extending in a second direction to intersect the plurality of bit lines on the plurality of cell diodes, each of the plurality of phase change material strips electrically connected to the plurality of cell diodes. strip; And A plurality of word lines formed on the plurality of phase change material strips, each word line including a plurality of word lines substantially parallel to each of the phase change material strips. The method of claim 8, Each phase change material strip is substantially parallel to at least a portion of each word line. The method of claim 8, And the plurality of bit lines are epitaxial layers of a first conductivity type. The method of claim 10, Each cell diode includes a first semiconductor pattern having a first conductivity type, and a second semiconductor pattern stacked on the first semiconductor pattern and having a second conductivity type. The method of claim 11, Wherein the first conductivity type is P type and the second conductivity type is N type. The method of claim 8, And a plurality of lower electrode contacts positioned on the cell diodes to electrically connect the cell diodes to the phase change material strips. The method of claim 8, And a plurality of metal lines positioned on the plurality of word lines and electrically connected to the respective bit lines. The method of claim 14, And each metal line is substantially parallel to each of the bit lines. Forming a plurality of bit lines extending in a first direction on the semiconductor substrate, Forming a plurality of cell diodes separately arranged along the first direction on each bit line, Forming a plurality of phase change material strips and a plurality of word lines extending in a second direction to intersect the bit lines on the plurality of cell diodes, wherein each of the phase change material strips and each word line are substantially parallel A method of manufacturing a phase change memory device comprising the step of. The method of claim 16, And wherein each phase change material strip is substantially parallel to at least a portion of each word line. 17. The method of claim 16, wherein forming the plurality of bit lines Forming a lower mold layer pattern having a plurality of openings on the semiconductor substrate, And forming an epitaxial layer of a first conductivity type in the opening of the lower mold layer pattern. 19. The method of claim 18, wherein forming the plurality of cell diodes is Forming an upper mold layer pattern having a plurality of openings on the lower mold layer and the bit line; Manufacturing a phase change memory device including forming a first semiconductor pattern having a first conductivity type and a second semiconductor pattern having a second conductivity type stacked on the first semiconductor pattern in an opening of the upper mold layer pattern; Way. The method of claim 19, Wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of claim 16, Forming a plurality of cell diodes, and forming a plurality of lower electrode contacts on the cell diodes to electrically connect the cell diodes and the phase change material strips to each other; Method of preparation. The method of claim 16, Forming a plurality of phase change material strips and word lines, and then forming a plurality of metal lines positioned on the plurality of word lines and electrically connected to the respective bit lines, respectively. Way. The method of claim 22, Wherein each metal line is substantially parallel to each of the bit lines.

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