KR101573270B1 - Pillar devices and methods of making thereof - Google Patents

Pillar devices and methods of making thereof Download PDF

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KR101573270B1
KR101573270B1 KR1020107017757A KR20107017757A KR101573270B1 KR 101573270 B1 KR101573270 B1 KR 101573270B1 KR 1020107017757 A KR1020107017757 A KR 1020107017757A KR 20107017757 A KR20107017757 A KR 20107017757A KR 101573270 B1 KR101573270 B1 KR 101573270B1
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plurality
insulating layer
forming
semiconductor
layer
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KR1020107017757A
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KR20100129272A (en
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반스 던톤
브래드 에스. 허너
폴 와이 키에 푼
추안빈 판
마이클 찬
마이클 코네섹키
우샤 라구람
크리스토퍼 제이. 페티
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쌘디스크 3디 엘엘씨
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Priority to US12/007,781 priority Critical patent/US7906392B2/en
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Priority to US12/007,780 priority
Priority to US12/007,780 priority patent/US7745312B2/en
Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

Abstract

A method of manufacturing a semiconductor device, comprising: providing an insulating layer comprising a plurality of openings; forming a first semiconductor layer over the insulating layer and a plurality of openings in the insulating layer; And removing the first portion of the first semiconductor layer such that the second portion of the first conductivity type remains at the lower portion of the plurality of openings in the insulating layer and the upper portion of the plurality of openings in the insulating layer remains unfilled. The method also includes forming a second semiconductor layer over the insulating layer and over the plurality of openings in the insulating layer and removing the first portion of the second semiconductor layer overlying the insulating layer. The second conductive type second portion of the second semiconductor layer is left on top of the plurality of openings in the insulating layer to form a plurality of pillar type diodes in the plurality of openings.

Description

PILLAR DEVICES AND METHODS OF MAKING THEREOF FIELD OF THE INVENTION [0001]

Cross-reference to related patent application

This application claims priority to U.S. Serial Nos. 12 / 007,780 and 12 / 007,781, filed January 15, 2008, both of which are incorporated herein by reference in their entirety .

Technical field

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of semiconductor device processing, and more particularly to a pillar device and a method of manufacturing the device.

U.S. Patent Application No. 10 / 955,549 (corresponding to U.S. Patent Application Publication No. 2005/0052915 A1), Herner et al., Filed September 29, 2004, which is incorporated herein by reference, discloses a three-dimensional memory array Wherein the data state of the memory cell is stored in the resistive state of the polycrystalline semiconductor material of the pillar type semiconductor junction diode in this three dimensional memory array. A subtractive method is used to fabricate such a filament diode device. The method includes depositing one or more layers of silicon, germanium, or other semiconductor material. The deposited semiconductor layers or layers are then etched to obtain a semiconductor pillar. An SiO 2 layer can be used as a hardmask for pillar etching and then removed. Next, SiO 2 or other gap-filling dielectric material is deposited between the pillars and on top of the pillars. A chemical mechanical polishing (CMP) or etchback step is then performed to planarize the gap filling dielectric with the top surface of the pillar.

A further description of a subtractive pillar manufacturing process is provided in U.S. Patent Application No. 11 / 015,824, entitled " Nonvolatile Memory Cell Containing a Vertical Diode of Reduced Height ", filed December 17, 2004 by Herner et al. See U.S. Patent Application No. 11 / 819,078, filed on June 25, 2006.

However, in the subtractive method, care must be taken to avoid undercutting the pillars at the base of the pillars during the etching step, for small diameter and width pillars. The undercut pillar device tends to fall during subsequent processing. Further, for smaller pillared devices, the height of the semiconductor pillar may be limited by the thin and soft photoresist used as the etch mask, and the oxide gap filling step may be used to reduce the processing challenges when the aspect ratio of the openings between the pillars increases And the CMP process or etch-back of the gap filling layer can remove a considerable thickness of the deposited semiconductor material.

One embodiment of the present invention provides a method of fabricating a semiconductor device comprising the steps of providing an insulating layer comprising a plurality of openings, forming a plurality of openings in a plurality of openings of the insulating layer, To form a layer. The method further includes forming a first semiconductor layer so that the first conductive type second portion of the first semiconductor layer remains on the lower portion of the plurality of openings of the insulating layer and the upper portion of the plurality of openings in the insulating layer remains uncharged. And removing the first portion of the layer. The method also includes forming a second semiconductor layer over the plurality of openings over the insulating layer and the insulating layer, and removing the first portion of the second semiconductor layer overlying the insulating layer. The second conductive type second portion of the second semiconductor layer remains on the upper portion of the plurality of openings in the insulating layer to form a plurality of pillar type diodes in the plurality of openings.

Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of tungsten electrodes, nitriding the tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes, Forming a plurality of semiconductor devices on the tungsten nitride barrier in the plurality of openings in the insulating layer; forming an insulating layer including a plurality of openings so that the insulating layer is exposed in the plurality of openings in the insulating layer;

Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of tungsten electrodes, selectively forming a plurality of conductive barriers on an exposed upper surface of the tungsten electrode, Forming an insulating layer including a plurality of openings so that the barrier is exposed in the plurality of openings in the insulating layer; and forming a plurality of semiconductor devices on the conductive barrier in the plurality of openings.

Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of lower electrodes on a substrate, forming a plurality of first openings having a first width to expose the lower electrode in the first openings, Forming a first semiconductor region of a first conductivity type in the first opening; forming a sacrificial material in the plurality of first openings on the first semiconductor region; Forming a plurality of second openings in the insulating layer having a second width greater than the first width to expose the first openings, removing the sacrificial material from the first openings through the second openings, Forming an upper electrode in the second opening in the insulating layer such that the upper electrode contacts the second semiconductor region, and forming an upper electrode in the second opening in the insulating layer, First to form a pillar shaped diodes in the first opening.

Another embodiment provides a method of fabricating a pillar device comprising providing an insulating layer having an opening and selectively depositing a germanium or germanium rich silicon germanium semiconductor material into the opening to form a pillar device.

The present invention has the effect of providing a pillar device and a method of manufacturing the device.

Figs. 1A, 1C, and 1E are side cross-sectional views illustrating the steps of forming a pillar apparatus according to the first embodiment of the present invention. Figs. 1B and 1D are cross- FIG.
2A to 2C are side cross-sectional views illustrating steps of forming a pillar apparatus according to a second embodiment of the present invention.
3A to 3E are side cross-sectional views illustrating steps of forming a pillar apparatus according to a third embodiment of the present invention;
Figures 3f-3g are photomicrographs of an exemplary device made according to the third embodiment;
4 is a three-dimensional view of a completed pillar apparatus in accordance with one or more embodiments of the invention.
5A is a plot of etch rate versus polysilicon doping in accordance with the prior art, and FIGS. 5B through 5E are side cross-sectional views illustrating steps of forming a pillar apparatus according to a fourth embodiment of the present invention.
6A to 6G are side cross-sectional views illustrating steps of forming a pillar apparatus according to a fifth embodiment of the present invention.
7A and 7B are side cross-sectional views of an apparatus feature made in accordance with an embodiment of the present invention.
8A to 8D are side cross-sectional views illustrating steps of forming a pillar apparatus according to an embodiment of the present invention.
Figure 8e is a three-dimensional view of a completed pillar apparatus in accordance with one embodiment of the present invention.
9A is a cross-sectional SEM image of a 40 nm thick Ge film deposited by GeH 4 for 10 minutes at 380 ° C and 1 torr on a silicon seed film deposited on TiN by SiH 4 decomposition at 380 ° C and 1 torr for 60 minutes. It is a video. FIG. 9B is a cross-sectional SEM image of the SiO 2 surface after the two-step SiH 4 and GeH 4 CVD processes, which are identical to each other, and no Ge deposition was observed on SiO 2 .

The present inventors have found that for semiconductor pillar devices having at least two regions of different conductivity types, such as diodes, including both p-type and n-type semiconductor regions, when such devices are formed in openings in an insulating layer, It should be noted that special steps have to be carried out to avoid short circuits.

For example, if the conductive barrier layer is simply deposited on the opening and then planarized, then the conductive barrier layer will extend along the side walls of the opening from the bottom of the opening to the top. Thereafter, when a semiconductor diode is deposited in the opening, the conductive barrier layer located along the sidewall of the opening shorts the p-type region of the diode to the n-type region of the diode.

Also, if the semiconductor layer of the diode is formed by a method such as low pressure chemical vapor deposition (LPCVD), then conformal deposition fills the opening from the bottom as well as the bottom. Thus, if the n-type semiconductor is deposited first in the opening, then it is also located along the entire sidewall of the opening or fills the entire opening. When the n-type region is located along the sidewall of the opening and the p-type region is located at the center of the opening, the upper electrode contacts both the p-type and n-type regions. When the n-type region fills the entire opening, there is no place to form a p-type region in the opening to form the diode thereafter.

Embodiments of the present invention provide a way to overcome these problems. In the first embodiment, a barrier layer is selectively formed so as not to short-circuit the diode formed in the opening in the insulating layer on the barrier. In the first embodiment of the first embodiment, the barrier layer may be formed by nitriding the lower tungsten electrode to form a tungsten nitride barrier layer before or after forming the insulating layer. If a tungsten nitride barrier is formed after the formation of the insulating layer, then the barrier layer is formed by nitriding a portion of the tungsten electrode exposed in the opening of the insulating layer. This nitridation step through the opening in the insulating layer is used to selectively form a tungsten nitride barrier layer on the bottom of the opening. In an alternative embodiment of the first embodiment, the barrier layer is formed by nitridation on the electrode prior to formation of the insulating layer.

In the second embodiment, the barrier layer is formed by selective deposition on the lower electrode. In the third embodiment, before forming the opposite conductivity type silicon layer in the space at the opening created by the recess etching, an optional silicon that can be precisely controlled to concave the one conductive type silicon layer at the opening A recess etch is used.

Figures 1 and 2 illustrate a method of fabricating a nitrided barrier layer according to an alternative embodiment of the first embodiment. Figs. 1A and 1B respectively show a side sectional view and a three-dimensional view of a plurality of conductive electrodes 1 separated from each other by an insulating material or a layer 3. Fig. The electrode may have any suitable thickness, such as from about 200 nm to about 400 nm. Electrode 1 may comprise tungsten or other conductive material that may be nitrided. The insulating material may comprise any suitable insulating material such as silicon oxide, silicon nitride, high dielectric constant insulating materials such as aluminum oxide, tantalum pentoxide or organic insulating material. The electrodes may be formed by depositing a tungsten layer over any suitable substrate, photolithographically patterning the tungsten layer with the electrode 1, depositing an insulating layer on and between the electrodes 1, and chemically mechanically polishing (CMP) Or by planarization by etch-back to form an insulating material region 3 that isolates the electrodes 1 from each other. Alternatively, the electrode 1 may be formed by the damascene method. In this damascene method, a groove is formed in the insulating layer 3, and a tungsten layer is formed in the groove and on the upper surface of the insulating layer 3 , Followed by planarization of the tungsten layer by CMP or etch-back to leave the electrode 1 in the trench in the insulating layer 3. The electrode 1 may be a rail-shaped electrode, as shown in Fig. 1B. Other electrode (1) shapes may also be used.

Figures 1C and 1D illustrate the step of nitriding the tungsten electrode 1 to form the tungsten nitride barrier 5 on the plurality of tungsten electrodes before the damascene-type insulating layer is deposited on the electrode 1. [ Barrier 5 may have any suitable thickness, such as, for example, from about 1 nm to about 30 nm. Any nitriding method can be used. For example, a plasma nitridation method can be used, wherein a nitrogen containing plasma such as ammonia or a nitrogen plasma is provided on the surface of the tungsten 1 and the insulator 3 exposed together. The specific content of exemplary plasma nitridation of tungsten to form tungsten nitride is described in U.S. Patent No. 5,780,908, which is incorporated herein by reference in its entirety. The method of U.S. Patent No. 5,780,908 is used to form a nitrided tungsten surface to provide a barrier between tungsten and the aluminum layer thereon for the purpose of forming a metal gate, instead of forming a barrier layer below the semiconductor device.

Although tungsten is described as being used as the electrode (1) material, other materials such as titanium, tungsten silicide or aluminum may also be used. For example, the stability of a tungsten nitride layer formed by nitridation of a tungsten silicide surface is described in U.S. Patent No. 6,133,149, which is incorporated herein by reference in its entirety.

Plasma nitriding nitrides the entire exposed surface of the insulating layer 3 and the electrode 1. This leaves a surface which is part of the tungsten nitride barrier 5 and part of which is part of the nitrogen-containing insulating material 7. For example, if the insulating material 3 is silicon oxide, then the upper portion is converted to silicon oxynitride 7 after nitridation. Of course, if the original insulating material 3 is silicon nitride, then nitridation can form a nitrogen-enriched silicon nitride region 7 on the surface or top of the insulating material 3. [ Therefore, the insulating layer or the top of the material 3 separating adjacent tungsten electrodes 1 from each other is also nitrided during the nitridation step.

As shown in FIG. 1E, a second insulating layer 9 is deposited over the nitrided insulating material 7 and the tungsten nitride barrier 5. The insulating layer 9 may have better adhesion to the tungsten nitride surface than to the non-nitrided tungsten surface. The insulating layer 9 may comprise any suitable insulating material such as silicon oxide, silicon nitride, high dielectric constant insulating materials such as aluminum oxide, tantalum pentoxide or organic insulating material. The material of the layer 9 may be the same as or different from the material of the insulating layer 3.

A plurality of openings 11 are formed in the insulating layer 9 such that the tungsten nitride barrier 5 is exposed in the plurality of openings 11. [ The opening 11 is formed by forming a photoresist layer on the insulating layer 9, exposing and developing the photoresist layer (i.e., patterning) and forming the opening 11 in the layer 9 by using a photoresist pattern as a mask Etched, and removed by photolithography, such as by removing the photoresist pattern.

Therefore, in the method of Figs. 1A to 1D, a nitriding step for forming the barrier 5 is performed prior to the step of forming the insulating layer 9. An insulating layer 9 is formed on the tungsten nitride barrier 5 and subsequently a plurality of openings 11 are formed in the insulating layer 9 to expose the upper surface of the tungsten nitride barrier 5.

Then, a plurality of semiconductor devices are formed on the tungsten nitride barrier 5 in the plurality of openings 11 in the insulating layer 9. For example, a silicon layer 13, such as a doped polysilicon or amorphous silicon layer, is deposited on the barrier 5 in the opening 11. The formation of a semiconductor device such as a pillar-shaped diode will be described in more detail with respect to the third to fifth embodiments below.

2A to 2C show an alternative embodiment of the first embodiment in which the insulating layer 9 is formed on a plurality of tungsten electrodes 1 (and on the insulating material or layer 3) before the formation of the barrier 5 ≪ / RTI > Then, a plurality of openings 11 are formed in the insulating layer 9 to expose the upper surface of the plurality of tungsten electrodes 1 as shown in Fig. 2A. A nitriding step is performed after forming the plurality of openings 11 in the insulating layer 9 such that the upper surface of the plurality of tungsten electrodes 1 is nitrided through the plurality of openings 11 as shown in FIG. . For example, as shown in Fig. 2B, a nitrogen-containing plasma 15 is provided in the opening 11 to nitride the tungsten electrode 1. Nitridation forms a tungsten barrier 5 on the tungsten electrode 1 in the opening 11. [

Thus, the nitridation step is performed after forming the plurality of openings 11 in the insulating layer 9 to form the tungsten nitride barrier. Optionally, the nitridation step also nitrifies at least one side wall 12 of the plurality of openings 11 in the insulating layer 9. If the insulating layer 9 is silicon oxide, then the sidewalls 12 are converted to the silicon oxynitride regions 14. As used herein, the term "sidewall " refers to both side walls of an opening having a polygonal cross section for convenience, or both side walls of an opening having a circular or oval cross section. Thus, the use of the term "sidewall" should not be construed as being limited to the side wall of the opening having a polygonal cross-section. If the insulating layer 9 is a material other than silicon oxide, then it can also be nitrided. For example, the metal oxide may also be converted to a metal oxynitride, the silicon nitride may be converted to a nitrogen-enriched silicon nitride, and the organic material may include a nitrogen-enriched region 14.

Fig. 2C shows the formation of the silicon layer 13 in the opening 11. Details of layer 13 deposition will be provided in connection with the third to fifth embodiments described below.

The advantage of performing nitridation after planarization of the electrode 1 as shown in Figures 1C and 1D is that the subsequent insulating layer 9 is not deposited on the tungsten surface. If the insulating layer is silicon oxide, then it may not provide an ideal bonding force for tungsten. However, silicon oxide is better adhered to the metal nitride barrier such as the tungsten nitride barrier 5.

When the gas required for the plasma deposition reactor is supplied through the piping, plasma nitridation can be performed in the same chamber as the deposition of the insulating layer 9, without adding any process steps at this time. In this process, a nitrogen plasma such as a nitrogen or ammonia plasma is turned on for a predetermined time to nitride the tungsten electrode 1 surface. A nitrogen containing plasma is then pumped from the deposition chamber and an insulating layer 9 deposition process is initiated by providing the deposition chamber with a desired precursor, such as silicon and an oxygen-containing precursor (e.g., silane in combination with oxygen or nitrogen oxides) Layer 9 is deposited. Preferably layer 9 is silicon oxide deposited by PECVD.

The advantage of performing the nitriding after forming the openings 11 is that the tungsten electrode sidewalls 2 are exposed in the over etched openings 11 then the sidewalls 2 are also nitrided as shown in Figure 2b will be. This may occur if the over etched insulating layer 9 opening 11 removes the TIN junction layer, which may be located below the tungsten electrode 1. [ In other words, the plurality of openings 11 in the insulating layer 9 may be partially misaligned with the plurality of tungsten electrodes 1, and the etching step used to form the plurality of openings 11 may be misaligned and overetched Thereby exposing at least parts of the side wall 2 of the tungsten electrode 1 as shown in Fig. 2A. At this time, the nitriding step is performed by forming a tungsten nitride barrier 6 on the exposed portion of the sidewall 2 of the tungsten electrode 1 and a tungsten nitride barrier 5 on the upper surface of the electrode 1 as shown in Fig. .

The silicon layer 13 can extend into the over-etched portion of the opening 11 when misalignment occurs during formation of the opening 11. However, the silicon layer 13 is only in contact with the tungsten nitride barriers 5, 6, as shown in FIG. 2C, and does not directly contact the tungsten electrode 1. When the final device, such as a pillar-shaped diode, is completed, it is partially misaligned with the tungsten electrode 1, and the tungsten nitride barriers 5, 6 are located on at least a portion of the upper surface of the tungsten electrode and the sidewall of the tungsten electrode. The oxide insulating layer 9 is located around the diode as will be described in more detail below, so that the portion 14 of the oxide insulating layer 9 located adjacent to at least one side wall of the pillar-shaped diode is nitrided.

Both the non-limiting advantages of the nitriding described above (adhesion of the improved insulating layer 9 to tungsten nitride and formation of the sidewall barrier 6 of the electrode 1) can be achieved prior to deposition of the layer 9, This will be achieved when nitriding is performed after forming the openings 11. Therefore, if necessary, nitridation of the electrode 1 can be performed both after the bottom electrode flattening as shown in Figs. 1C and 1D, and after the formation of the opening 11 as shown in Fig. 2B.

In the second embodiment, the conductive barrier 5 is formed by selective deposition on the exposed upper surface of the tungsten electrode 1. For example, in one aspect of the second embodiment, a metal or metal alloy barrier 5 is formed by selective atomic layer deposition on a plurality of tungsten electrodes. Barrier (5) The metal or metal alloy may comprise tantalum, niobium or an alloy thereof. Selective atomic layer deposition of barrier metals such as tantalum or niobium is described in U.S. Patent Application Publication No. 2004/0137721, which is incorporated herein by reference in its entirety. The atomic layer deposition of the barrier 5 is preferably performed prior to the deposition of the insulating layer 9 as shown in Figures 1C and 1D. Selective deposition selectively forms the barrier 5 only on the electrode 1, except for the portion adjacent to the insulating layer or material 3. Thus, metal connection from the barrier 5 of the electrode to the upper surface of the insulating layer 9 is prevented.

In an alternative method of the second embodiment, the conductive barrier is formed by selectively plating a barrier metal or a metal alloy on a plurality of tungsten electrodes. The plating may include electroless plating or electrolytic plating, which selectively plated the barrier 5 only on the electrode 1 except for the adjacent insulating layer 3 or 9. The barrier metal or metal alloy may comprise any conductive barrier material that can be selectively plated only on the electrode, not the insulating layer, from the plating solution, such as cobalt or cobalt tungsten alloy, including CoWP. Selective deposition of barrier metal alloys such as CoWP by plating is described in detail in Jeff Gamindo < RTI ID = 0.0 > et < / RTI > of MRS Green No. F5.9, April 17-21, 2006, San Francisco, Quot; thermal oxidation of Ni and Co alloys formed by electroless plating "by co-authors. Selective plating may be carried out prior to the deposition of the insulating layer 9 and / or through the openings 11 in the insulating layer 9. In other words, the plating of the conductive barrier is performed by forming an insulating layer 9 on the plurality of conductive barriers 5 and subsequently forming a plurality of conductive barriers 5 in the insulating layer 9 to expose the upper surface of the plurality of conductive barriers 5. [ It may be performed before the step of forming the insulating layer 9 so that the opening 11 is formed. Alternatively, the plating of the conductive barrier may be carried out after the step of forming the plurality of openings 11 in the insulating layer 9, so that the plurality of conductive barriers may have a plurality of openings 11 in the insulating layer 9 (Not shown) on the upper surface of the plurality of tungsten electrodes 1.

The opening 11 in the insulating layer 9 may be partially misaligned with the plurality of tungsten electrodes 1 so that the step of forming the plurality of openings 11 Exposes at least a part of the side wall 2 of the tungsten electrode 1. Selective deposition of the conductive barrier 5, such as selective plating, forms the conductive barrier 6 on the exposed portion of the sidewalls 2 of the plurality of tungsten electrodes 1 and the conductive barrier 5 on the top surface.

The method according to the third embodiment of the present invention forms a pillar-like device such as a pillar diode in the opening 11 in the insulating layer 9 by a modified process as shown in Figs. 3A to 3E. This device can be formed on the barrier layers 5, 6 of the first or second embodiment. Alternatively, the barrier layers 5, 6 may be omitted, or the barrier 5 may be formed by a non-selective layer deposition and subsequent photolithographic patterning instead of the method of the first or second embodiment.

As shown in Fig. 3A, an insulating layer 9 including a plurality of openings 11 is provided on a substrate. The substrate can be any semiconductor substrate known in the art, such as IV-IV compounds, such as monocrystalline silicon, silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VI compounds, epitaxial layers or glass , A plastic, a metal, or a ceramic substrate. The substrate may comprise an integrated circuit fabricated thereon such as a drive circuit for a memory device. As described above with respect to the first and second embodiments, a lower electrode such as a rail-type tungsten electrode 1 covered with a barrier 5 is formed on a substrate as a first step of manufacturing a nonvolatile memory array. Other conductive materials such as aluminum, tantalum, titanium, copper, cobalt or alloys thereof may also be used. An adhesive layer, such as a TiN adhesive layer, may be included under the electrode 1 to aid adhesion of the electrode to the insulating layer 3 or other material under the electrode 1.

The insulating layer 9 may be any electrically insulating material such as silicon oxide, silicon nitride or silicon oxynitride, or an organic or inorganic high dielectric constant material. If desired, the insulating layer 9 may be deposited as two or more separate sub-layers. Layer 9 may be deposited by PECVD or any other suitable deposition method. Layer 9 may have any suitable thickness, such as, for example, from about 200 nm to about 500 nm.

Next, the insulating layer 9 is photolithographically patterned to extend to the top surface of the barrier 5 of the electrode 1 and form an opening 11 to expose it. The openings 11 should have approximately the same pitch and approximately the same width as the underlying electrodes 1 so that each subsequently formed semiconductor pillar is formed on top of each electrode 1. [ Slight misalignment may be tolerated as described above. Preferably, the opening 11 in the insulating layer 9 has a half pitch of 45 nm or less, such as 10 nm to 32 nm. The opening 11 having a small pitch is formed by forming a positive photoresist on the insulating layer 9, exposing the photoresist to radiation such as 193 nm radiation while using an attenuated phase shift mask, patterning the exposed photoresist, May be formed by etching the openings 11 in the insulating layer 9 using patterned photoresist. Next, the photoresist pattern is removed. Any other suitable lithography or patterning may also be used. For example, other radiation wavelengths, such as 248 nm, may be used with or without a phase shift mask. For example, openings of 120-150 nm width, such as about 130 nm, may be formed by 248 nm lithography, and openings of 45-100 nm width, such as about 80 nm, may be formed by 193 nm lithography. Various hard masks and antireflective layers such as BARC or DARC in combination with an insulating hard mask for 248 nm lithography and BARC or DARC in combination with a dual W / insulating hard mask for 193 nm lithography can also be used in lithography.

The first semiconductor layer 13 is formed in the plurality of openings 11 in the insulating layer 9 and on the insulating layer 9. The semiconductor layer 13 may comprise a compound semiconductor material such as silicon, germanium, silicon-germanium or III-V or II-VI materials. The semiconductor layer 13 may be a polycrystalline material such as polysilicon or an amorphous material. The amorphous semiconductor material can be crystallized in a subsequent step. Layer 13 is preferably heavily doped with a first conductivity type dopant such as a p-type or n-type dopant, such as doping using a dopant concentration of 10 18 to 10 21 cm -3 . For example, it is assumed that layer 13 is conformally deposited n-type doped polysilicon. Polysilicon can be deposited and then doped, but preferably doped with a dopant-containing gas (i. E., Added to the silane gas) that provides an n-type dopant atom, for example phosphorus or arsenic, during LPCVD deposition of the polysilicon layer In the form of arsenic gas or phosphine gas). The resulting structure is shown in Fig.

As shown in FIG. 3B, the top of the semiconductor layer 13, such as a polysilicon layer, is removed. The lower n-type portion 17 of the polysilicon layer 13 remains in the lower portion of the opening 11 in the insulating layer 9 and forms the upper portion 19 of the plurality of openings 11 in the insulating layer 9. [ Remains uncharged. The N-type portion 17 may be about 5 nm to about 80 nm thick, such as about 10 nm to about 50 nm thick. Other suitable thicknesses may be used instead.

Any suitable method can be used to remove the layer 13 from the top portion 19 of the opening 11. For example, a two step process can be used. First, the polysilicon layer 13 is planarized with the top surface of the insulating layer 9. Planarization may be performed by CMP or etchback (such as isotropic etching) using optical termination point detection. After the polysilicon layer 13 is planarized with the top surface of the insulating layer 9 (i.e., the polysilicon layer 13 is filled in the opening 11 but not over the top surface of the insulating layer 9) A second recess etch step is performed to concave the layer 13 in the opening 11 so that only the portions 17 of the layer 13 remain in the opening 11. Any optional etching step may be used, such as a wet or dry isotropic or anisotropic etching step, which selectively or preferentially etches the polysilicon remaining on top of the opening 11 above the insulating material (such as silicon oxide) of the layer 9 have. A dry etching step is preferably used which provides a controllable etch end point.

For example, as shown in the micrograph of FIG. 3f, the recess etch step is an optional dry anisotropic etch step. In this step, the first semiconductor layer 13 remaining on the upper portions of the plurality of openings 11 is etched in a planar etching etch front to concave the first semiconductor layer 13. The planar etch front provides that the portions 17 of the first semiconductor layer 13 remaining in the plurality of openings 11 have a substantially planar upper surface as shown in Figure 3F. This allows the formation of a "parfait" type diode with a substantially planar boundary between regions of different conductivity type.

Alternatively, as shown in FIG. 3G, a selective isotropic etch may be used to recess layer 13. In this case, the portions of the first semiconductor layer 13 remaining in the plurality of openings 11 have an annular (i.e., hollow ring) shape having a central groove as shown in Fig. 3G.

A second semiconductor layer 21 is then formed on the insulating layer 9 and on the upper portion 19 of the plurality of openings 11 in the insulating layer 9, The second semiconductor layer 21 may include the same or different semiconductor material as the material of the first semiconductor layer 13. [ For example, layer 21 may also comprise polysilicon. (13) as disclosed in U.S. Patent No. 7,224,013 to Herner and Walker, entitled " a junction diode comprising various semiconductor compositions ", the title of which is incorporated herein by reference in its entirety. It may be desirable to deposit a layer 21 having a semiconductor composition different from that of the composition. For example, layer 13 may comprise a silicon-germanium alloy or silicon with a relatively low proportion of germanium and layer 21 may comprise silicon-germanium alloy or silicon with a relatively high proportion of germanium relative to layer 13. For example, Or germanium, and vice versa. When a p-n type diode is formed in the opening 11, then the layer 21 can be highly doped from the conductivity type of the layer 13, such as a p-type dopant, to the opposite conductivity type dopant. If necessary, the second semiconductor layer 21 has the same conductivity type as the first layer 13, but has a lower doping concentration than the layer 13.

When a p-i-n type diode is formed in the opening 11, the second semiconductor layer 21 may be an intrinsic semiconductor material such as intrinsic polysilicon. In this description, the region of the semiconductor material that is not intentionally doped is described as an intrinsic region. However, those skilled in the art will appreciate that the intrinsic region may in fact comprise a low concentration of p-type or n-type dopant. The dopant may diffuse into the intrinsic region from the adjacent region or may be present in the deposition chamber during the deposition step due to contamination from previous deposition. It will also be appreciated that the deposited intrinsic semiconductor material (such as silicon) may contain defects and such defects may cause the intrinsic semiconductor material to behave as if it were slightly doped n-type. Using the term "intrinsic" to describe silicon, germanium, silicon-germanium alloys or any other semiconductor material means that this region does not include any doping system at all or that this region is completely electrically neutral It does not. The second semiconductor layer 21 is then removed from the first semiconductor layer 21 located above the insulating layer 9 leaving the portion 23 of the layer 21 in the upper portion 19 of the opening 11 Is planarized with at least the upper surface of the insulating layer 9 using chemical mechanical polishing to remove the portions. Alternatively, an etch back may be used. The intrinsic region or portion 23 may be between about 110 and about 330 nm, such as about 200 nm thick. The resulting apparatus is shown in Figure 3d.

A dopant of the opposite conductivity type to the conductivity type of the region 17 is then injected into the upper section of the second portion 23 of the second semiconductor layer 21 to form a pin-pillar type diode. For example, a p-type dopant is implanted into the upper section of the intrinsic portion 23 to form the p-type region 25. The p-type dopant is preferably boron which is implanted as boron or BF 2 ions. Alternatively, the region 25 may be selectively deposited on the region 23 (after the region 23 is recessed in the opening 11) and then implanted into the region 23, do. For example, the region 25 can be formed by depositing an on-site p-type doped semiconductor layer by CVD, and then planarizing this layer. Region 25 may be, for example, from about 10 nm to about 50 nm thick. The pillar-shaped pin diode 27 located in the opening 11 includes an n-type region 17, an intrinsic region 23 and a p-type region 25 as shown in FIG. 3E. In general, the filament diode 27 preferably has a substantially cylindrical shape with a circular or substantially circular cross section with a diameter of 250 nm or less. Alternatively, a pillar diode having a polygonal cross-sectional shape such as a rectangular or square shape can be formed by forming the opening 11 having a polygonal cross-sectional shape instead of a circular or oval cross-sectional shape.

Alternatively, by the method described in U.S. Application Publication No. 2006/0087005, entitled " Evaporated Semiconductor Structure Minimizing Diffusion of N-type Doping Agent and Method of Making It, " the title of which is hereby incorporated by reference in its entirety Dopant diffusion during subsequent intrinsic silicon deposition is prevented. In this method, an n-type semiconductor layer such as an n-type polysilicon or amorphous silicon layer is covered by a silicon-germanium cover layer having at least 10 atomic percent germanium. The cover layer may be from about 10 to about 20 nm thick, preferably less than about 50 nm thick, with little or no n-type dopant (i.e., the cover layer is preferably a thin intrinsic silicon-germanium layer Do). An intrinsic layer of a diode such as a silicon-germanium layer or a silicon layer with less than 10 atomic percent of germanium is deposited on the cover layer. Alternatively, a selective silicon rich oxide (SRO) layer is formed between the intrinsic region 23 and the n-type region 17 of each diode 27. The SRO region forms a barrier that prevents or reduces phosphorus diffusion from the bottom n-type region 17 of the diode into the undoped region 23.

In an exemplary embodiment, the bottom region 17 of the diode 27 is N + (heavily doped n-type) and the top region 25 is P + . However, the vertical pillars may also include other structures. For example, bottom region 17 is P + and top region 25 is N + . Additionally, the intermediate region may be intentionally lightly doped, intrinsic, or intentionally undoped. The undoped regions can never be completely electrically neutral and always have defects or contaminants, which make the non-doped regions behave as if they are slightly n-doped or p-doped. These diodes can be regarded as pin diodes. Thus, P + / N - / N + , P + / P - / N + , N + / N - / P + or N + / P - / P + diodes may be formed.

4, the upper electrode 29 may be formed in the same manner as the bottom electrode 1, for example, by depositing a conductive layer, preferably an additional layer of titanium nitride, preferably of tungsten have. The conductive and additional layers are patterned and etched using any suitable masking and etching technique to form a substantially parallel, substantially planar area conductor rail 29 extending perpendicularly to the conductor rail 1. In a preferred embodiment, the photoresist is deposited, patterned by photolithography, the conductive layer is etched, and then the photoresist is removed using standard processing techniques. Alternatively, a selective insulating oxide, nitride, or oxynitride layer may be formed on the highly doped region 25, and the conductor 29 may be formed as described in < RTI ID = 0.0 > The claimed invention is formed by a damascene process as described in U.S. Patent Application No. 11 / 444,936 to Radigan et al., Which is "a conductive hard mask for protecting patterned features during trench etching" . The rails 29 may be between about 200 nm and about 400 nm thick.

Next, another insulating layer (not shown for the sake of clarity) is deposited between and above the conductor rails 29. The insulating material may be any known electrically insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this insulating material. This insulating layer can be planarized together with the upper surface of the conductor rail 29 by CMP or etchback. A three dimensional view of the resulting device is shown in FIG.

A pillar device, such as a diode device, may include a one time programmable (OTP) or rewritable nonvolatile memory device. For example, each diode pillar 27 may serve as a steering element of a memory cell, and another material or layer 31 acting as a resistance switching material (i.e., storing data) And is provided in series with the diode 27 between the electrodes 1 and 29 as shown. Specifically, FIG. 4 illustrates a cross-sectional view of an embodiment of the present invention, which is a cross-sectional view of an embodiment of an anti-fuse (i.e., anti-fuse dielectric), fuse, polysilicon memory effect material, metal oxide (such as nickel oxide, perovskite material, Volatile memory cell comprising a pillar diode 27 in series with a resistive switching material 31, such as a metal oxide, a conductive bridge element, or a switchable polymer. A resistive switching material 31, such as a thin silicon oxide antifuse dielectric layer, is deposited over the diode pillar 27 and subsequently the top electrode 29 may be deposited on the anti-fuse dielectric layer. The anti-fuse dielectric 31 may also be formed by oxidizing the top surface of the diode 27 to form a 1 to 10 nm thick silicon oxide layer. Alternatively, the resistance switching material 31 may be located below the diode pillar 27, such as between the barrier 5 and another conductive layer, such as a TiN layer. In this embodiment, the resistance of the resistance switching material 31 is increased or decreased in response to the forward and / or reverse bias provided between the electrodes 1, 29.

In another embodiment, the filament diode 27 itself may be used as a data storage device. In this embodiment, the resistance of the filament diode is described in U. S. Patent Application Serial No. 10 / 955,549, filed September 29, 2004, both of which are herein incorporated by reference in their entirety, 29 and the forward and / or backward direction provided between the electrodes 1, 29 as described in U.S. Patent Application No. 11 / 693,845, filed March 30, 2007 (corresponding to U.S. Application Publication 2007/0164309 A1) Or by application of a reverse bias. In this embodiment, the resistance switching material 31 may be omitted if necessary. Although non-volatile memory devices have been described, other devices such as other volatile or non-volatile memory devices, logic devices, display devices, light emitting devices, detectors, etc., may also be formed by the methods described above. Also, while the pillar-type device is described as being a diode, other similar pillar-type devices such as transistors may also be formed.

The formation of the first memory level has been described. Additional memory levels may be formed over the first memory level to form a monolithic three-dimensional memory array. In some embodiments, the conductors may be shared between memory levels, i.e., the upper conductor 29 may function as a bottom conductor of the next memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level, its surface is planarized, and a configuration of a second memory level may be initiated on the planarized interlevel dielectric without any shared conductors.

A monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a wafer, without any substrate intervention. The layers forming one memory level are deposited or grown directly on top of existing levels or layers of levels. In contrast, stacked memory is constructed by forming memory levels on separate substrates, such as in Leedy, U. S. Patent No. 5,915, 167 "Three Dimensional Structure Memory ", and bonding these memory levels onto one another. Although the substrates may be thinned or removed from memory levels prior to bonding, such memories are not true monolithic three dimensional memory arrays, since memory levels are initially formed on separate substrates.

The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or virtually any number of memory levels may be formed on the substrate in such a multilevel array.

In a fourth embodiment of the present invention, alternative etching and doping steps are used to form a pillar-like device, such as diode 27. In this embodiment, the etch selectivity of the polysilicon of various conductivity types is used in the recess etch step to provide end point detection. Specifically, doped polysilicon has a faster etch rate than undoped silicon (data showing that differently doped polysilicon have different etch rates is available at http://www.clarycon.com/Resources/Slide3t. jpg and http: www.clarycon.com/Resources/Slide5i.jpg). The etch rates from the aforementioned web sites for phosphorous doped, boron doped and undoped polysilicon are shown in FIG. 5A.

The depth of the high etch rate n-type doping layer can be tailored to the implant dose and energy. One method of optical etch endpoint detection includes monitoring a change in the intensity of a wavelength that is characteristic of a particular reactant or product of an etch reaction. When the etch end point is achieved, a lower density etch reaction product will be present in the plasma, so that the end point can be triggered and the etch can be stopped. Other etch endpoint detection uses a mass spectrometer for monitoring specific species in the exhaust stream from the dry etching reaction, referred to as RGA (residual gas analysis). The mass spectrometer may be located in or near the exhaust conduit of the etch reaction chamber. In this case, the RGA monitors the phosphorus-containing species in the exhaust stream and provides an end point signal or provides a trigger for the drop in this signal.

In the method of the fourth embodiment, the first polysilicon layer 13 is undoped deposited (i.e., intrinsic) as shown in FIG. 5B. The layer 13 is then implanted with a predetermined depth before or after the layer 13 is planarized with the top surface of the insulating layer 9 to form the implant region 101 as shown in Figure 5c. do. The implant depth is selected such that the bottom portion 103 of the phosphorus implant region 101 is located at or around the top surface of the region 17 shown in Figure 3b. The intrinsic portion 105 of the first semiconductor layer 13 remains in the lower portion of the plurality of openings 11. [

The first polysilicon layer 13 is then etched using an anisotropic plasma etch to etch the layer 13 in the opening 11 (e.g., SF 6 , CF 4 , HBr / Cl 2 or HBr / O 2 plasma Or the like), or the like. The doped region 101 of the first polysilicon layer 13 is etched until the intrinsic portion 105 of the first polysilicon layer is reached, as shown in Figure 5D. In other words, when the bottom portion 103 of the implanted region 101 is reached (thus, during the etching step, the intrinsic portion 105 of the first polysilicon layer 13 is exposed during the etching step, as detected optically or by RGA) Is reached), the etching is stopped. In particular, when the bottom 103 of the phosphorous doped region 101 is reached, the intensity of the phosphorous wavelength at the optical termination point detection decreases, or the amount of phosphorus containing species detected by the RGA decreases. The residual intrinsic portion 105 of the layer 13 in the opening 11 can then be removed by a method such as implanting phosphorous or arsenic into the portion 105 to form the n-type portion 17, doped with an n-type dopant. A second semiconductor layer, such as intrinsic semiconductor layer 21, is then deposited on portion 17 as shown in Figure 3c, and the process continues as in the third embodiment. In order to form the diode 27 with the p-type bottom region, the portion 105 is implanted with boron or BF 2 after recess etching. Also, instead of using the phosphorous implant region for the end point detection, a boron or BF 2 implant region is used, and the characteristic boron wavelength or RGA signal is monitored instead.

Optical termination point detection can also be used to determine when the layer 13 is planarized with the top surface of the insulating layer 9. After the layer 13 is planarized, the upper surface of the insulating layer 9 is exposed. Thus, the optical signal on the surface changes from a polysilicon signal to a signal characteristic in which both polysilicon and an insulator (such as silicon oxide) are present.

In a fifth embodiment of the present invention, a sacrificial layer is used to form the pillar shaped device. Figures 6A-6G illustrate the steps of the method of the fifth embodiment.

First, a plurality of lower electrodes 1 are formed on the substrate as described above with respect to the previous embodiment. For example, a tungsten electrode 1 having a barrier 5 of the first and second embodiments can be provided (the electrode 1 and the barrier 5 are omitted from FIG. 6A for clarity, and FIG. 6G Lt; / RTI > shown in FIG. An insulating layer 9 comprising a plurality of openings 11 having a first width is then provided above the electrode 1 and the barrier 5 (one opening 11 is shown in Figure 6a for clarity) ). An optical hardmask layer 33 is also formed over the insulating layer 9. Thereafter, a first semiconductor region of a first conductivity type (such as an n-type polysilicon region) 17 is formed on the lower electrode. For example, the method of the third or fourth embodiment can be used to form the region 17. Thereafter, a sacrificial material 35 is formed in the plurality of first openings 11. The sacrificial material may be any suitable soluble organic material used in dual damascene via the first method. For example, a Wet Gap Fill (WGF) 200 material provided by Brewer Science, Inc. may be used as the sacrificial material 35. [ The apparatus of this stage of this process is shown in Fig. 6A.

6B, a selective antireflection layer 37, such as a BARC layer 37m, is formed on the insulating layer 9 and on the optional hard mask 33. [ A photoresist layer 39 is then exposed and patterned on the BARC layer 37. The apparatus of this stage of this process is shown in Figure 6B.

6C, the patterned photoresist is then patterned into a plurality of second openings 41 (one for clarity) in the insulating layer 9 to expose the sacrificial material 35 in the openings 11 And the opening 41 is shown in Fig. 6C). The second opening (41) is wider than the first opening (11). A portion of the sacrificial material 35 may be etched during formation of the second opening. The second opening 41 includes a trench-like opening, and the sacrificial material is exposed at a portion of the bottom of the trench.

As shown in FIG. 6D, the sacrificial material is selectively removed from the first opening 11 through the second opening 41. Any suitable liquid etch material or developer may be used to remove material 35 from opening 11 to expose n-type polysilicon region 17 in opening 11.

Then, as shown in FIG. 6E, a second conductive type second semiconductor region is formed in the first opening 11. For example, the intrinsic polysilicon layer 21 may be formed on the insulating layer 9 and in the openings 11,41.

The polysilicon layer 21 is then planarized and recessed using the method described in the third embodiment. Preferably, the remaining portion 23 of the polysilicon layer 21 is recessed so that its top surface is level with the top surface of the opening 11 (i. E., The top of the portion 23 is the bottom of the trench 41) ≪ / RTI > P-type region 25 is then formed in intrinsic region 23 as described above in the third embodiment. The device of this stage is shown in Figure 6f. The regions 17, 23 and 25 form a pillar-shaped diode 27 in the first opening 11.

6G, an upper electrode is formed in the trench 41 in the insulating layer 9 by a damascene process so that the upper electrode is connected to the p-type semiconductor region 25 of the diode 27, . The upper electrode includes a TiN bonding layer 43 and a tungsten conductor 29. Then, the upper electrode is flattened by CMP or etch-back together with the upper surface of the insulating layer 9. If necessary, the lower TiN bonding layer 45 may also be formed under the lower electrode 1. The trench may be from about 200 nm to about 400 nm deep, and the diode 27 may be about 200 nm to about 400 nm high, such as about 250 nm high.

The pillar-shaped device may be formed using any one or more of the steps described above with respect to any one or more of the first to fifth embodiments. Depending on the process steps used, the finished device may have one or more of the following features shown in Figures 7A and 7B.

7A, the n-type region 17 of the diode 27 includes a first vertical junction line 47 and the p-type region 25 (and , Intrinsic region 23) may include a second vertical seam line 49. The junction lines 47 and 49 may be formed if the deposition of the polysilicon layers 13 and 21 does not completely fill the openings 11 during the separate deposition steps. The first vertical joining line 47 and the second vertical joining line 49 do not contact each other. The junction lines are not in contact with each other because the polysilicon layers 13 and 21 are deposited in separate steps as shown in Figures 3A to 3E. Specifically, without being limited to any particular theory, the bottom portion of the layer 21 contacting the region 17 does not form a joining line because the bottom portion of the layer 21 can completely fill the opening 11 It is believed. However, the bonding line may be omitted depending on the deposition process of the polysilicon layers 13 and 21.

7A, the sidewalls 51 of the region of the first conductivity type (such as the n-type region 17) are connected to the region of the second conductivity type of the diode (the p-type region 25 and the p- / RTI > and / or the intrinsic region 23). ≪ RTI ID = 0.0 > The discontinuous portion 55 is located on the sidewall of the diode 27 where the tapered side walls 51 and 53 meet. Particularly, the first conductivity type region 17 has a narrower taper angle than the second conductivity type region 25 and the discontinuity portion 55 has the intrinsic semiconductor region 23 and the n-type conductivity type region 17 In the side wall of the diode. Without being limited to any particular theory, because the recess etch-back of the layer 13 shown in Fig. 3B is more isotropic than the step of etching the openings 11 in the insulating layer 9 shown in Fig. 3A, It is believed that an additional portion can be formed. The upper portion 19 of the opening 11 is also etched and widened relative to the lower portion of the opening 11 during the etch back of the layer 13. [ Thus, the layers 13 and 21, which respectively fill the lower and upper portions of the opening 11, take different tapers of each portion of the opening. The different tapered and discontinuous portions can be avoided if the recess etch step of the layer 13 is performed without extending the upper portion 19 of the opening.

When the barrier 5 is formed by nitriding the electrode 1 through the opening 11 in the insulating layer 9 as shown in Fig. 2B, then it is adjacent to at least one sidewall of the pillar-shaped diode 27 A part of the insulating layer 9 is nitrided. For example, if layer 9 is a silicon oxide, as shown in Figures 2b and 7a, then a nitrided oxide or nitrogen-containing silicon oxide region 14, such as silicon oxynitride, Is formed on the side wall (12) of the opening (11). In addition, if the upper portion of the insulating layer 9 adjacent to the p-type region 25 of the diode comprises a boron gradient, then it is possible to form the region 25, as shown in Figures 3e and 7a Which implies that boron is implanted into the insulating layer 9 in addition to being injected into the upper portion of the hazardous region 23.

Figure 7b shows the inset portion of Figure 7a around the barrier 5,6. If the pillar type diode is partially misaligned with the tungsten electrode as shown in Figs. 2A, 2B and 7B, then the tungsten nitride barrier 5 is located on the top surface of the tungsten electrode 1 and the tungsten nitride barrier 6 are located at least in part of the side wall of the tungsten electrode 1 as shown in Fig. 7B. In addition, when the barrier 5 is formed by nitriding the tungsten electrode 1 before forming the insulating layer 9 as shown in Figs. 1C and 1D, the 1-10 nm thick nitrogen rich region 7 ) Is formed in the upper portion of the lower insulating layer or material (3). For example, if layer 3 comprises an oxide such as silicon oxide, then upper portion 7 thereof is nitrided to form silicon oxynitride or nitrogen-containing silicon oxide.

Another embodiment of the present invention provides a method of manufacturing a pillar device by selectively depositing a germanium or germanium rich silicon germanium pillar into a previously formed opening in an insulating layer to overcome the limitations of the subtractive method used in the prior art. The selective deposition method includes providing an electrically conductive material such as titanium nitride, tungsten, or other conductor exposed to the openings in the insulating layer. A silicon seed layer is then deposited on the titanium nitride. Thereafter, germanium or germanium rich silicon germanium (i.e., SiGe containing at least 50 atomic percent Ge) is selectively deposited on the silicon seed layer in the openings, without any germanium or germanium rich silicon germanium being deposited on the top surface of the insulating layer. Lt; / RTI > This removes the oxide CMP or etchback step used in the subtractive method. Preferably, the silicon seed layer and the germanium or germanium rich silicon germanium pillar are deposited by chemical vapor deposition at low temperatures, such as at temperatures below 440 캜.

Electrically conductive materials, such as titanium nitride, may be provided in the openings by any suitable method. For example, in one embodiment, a layer of titanium nitride is formed over the substrate, and then patterned photolithographically in a pattern. Alternatively, other materials such as titanium tungsten or tungsten nitride may be used instead of titanium nitride. The pattern may include an electrode, such as a rail-shaped electrode. An insulating layer is then formed on the titanium nitride pattern, such as a titanium nitride electrode. Thereafter, an opening is formed in the insulating layer by etching to expose the titanium nitride pattern. In an alternative embodiment, the conductive nitride pattern is selectively formed in the opening in the insulating layer. For example, a titanium nitride or tungsten nitride pattern can be selectively formed in the opening in the insulating layer by nitriding the titanium or tungsten layer exposed at the bottom of the opening.

The pillar device may include a portion of any suitable semiconductor device such as a diode, a transistor, and the like. Preferably the pillar device comprises a diode such as a p-i-n diode. In this embodiment, selectively depositing a germanium or germanium rich silicon germanium semiconductor material into the opening selectively deposits a semiconductor material of a first conductivity type (such as n-type) into the opening to form a pin diode, Selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material and subsequently selectively depositing a germanium or germanium rich germanium semiconductor material of a second conductivity type (such as p-type). Thus, all three regions of the p-i-n diodes are selectively deposited into the openings. Alternatively, in a less preferred embodiment, instead of selectively depositing a second conductivity type semiconductor material, a second semiconductor material such as a p-type dopant into the upper portion of the intrinsic germanium or germanium rich silicon germanium semiconductor material to form a pin diode The diode can be completed by injecting a dopant of a conductive type. Of course, the positions of the p-type and n-type regions can be reversed if necessary. A germanium or germanium rich silicon germanium semiconductor material of the first conductivity type (such as n-type) is selectively deposited into the opening to form a pn type diode, and subsequently a germanium or germanium rich silicon germanium semiconductor material of the second conductivity type Or a germanium-enriched silicon germanium semiconductor material is selectively deposited over the semiconductor material of the first conductivity type to form a diode.

Figures 8A-8D illustrate a preferred method of forming a pillared device using selective deposition.

Referring to FIG. 8A, an apparatus is formed on a substrate 100. Substrate 100 can be any of IV-IV compounds such as monocrystalline silicon, silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VI compounds, epitaxial layers on such substrates or substrates such as glass, Or any other semiconductor substrate known in the art, such as other semiconductor or non-semiconductor materials. The substrate may comprise an integrated circuit fabricated thereon such as a drive circuit for a memory device. The insulating layer 102 is preferably formed on the substrate 100. The insulating layer 102 may be silicon oxide, silicon nitride, a high dielectric constant film, a Si-C-O-H film, or any other suitable insulating material.

The first electrically conductive layer 200 is formed on the substrate 100 and the insulating layer 102. Conductive layer 200 may comprise any conductive material known in the art, such as tungsten and / or other materials including aluminum, tantalum, titanium, copper, cobalt, or alloys thereof. An adhesive layer may be included between the insulating layer 102 and the conductive layer to help adhere the conductive layer to the insulating layer 102.

A barrier layer 202, such as a TiN layer, is deposited on top of the first conductive layer 200. When the upper surface of the first conductive layer 200 is tungsten, tungsten nitride may be formed on the conductive layer 200 instead of TiN by nitriding the upper surface of the tungsten. For example, the following combination of conductive layers can be used: Ti (bottom) / Al / TiN (top) or Ti / TiN / Al / TiN or Ti / Al / TiW or any combination of these layers. The bottom Ti or Ti / TiN layer acts as an adhesive layer and the Al layer can act as the conductive layer 200 and the top TiN or TiW layer can act as the anti-reflective coating 202 for patterning the barrier layer 202 and the electrode 204 As an optional abrasive stop material for subsequent CMP of the insulating layer 108 (when layer 108 is deposited in two stages), and as a selective silicon seed deposition substrate, as described below.

Finally, the conductive layer 200 and the barrier layer 202 are patterned using any suitable masking and etching process. In one embodiment, a photoresist layer is deposited over the barrier layer 202, patterned by photolithography, and the layers 200 and 202 are etched using a photoresist layer as a mask. The photoresist layer is then removed using standard processing techniques. The resulting structure is shown in Figure 8A. The conductive layer 200 and the barrier layer 202 are patterned into a rail-shaped bottom electrode 204 of the memory device. Alternatively, the electrode 204 may be formed instead by the Damascene method, wherein at least the conductive layer 200 is formed in the recess in the insulating layer by deposition and subsequent planarization.

Next, referring to FIG. 8B, an insulating layer 108 is deposited between, and on, the electrodes 204. Referring to FIG. The insulating layer 108 may be any electrically insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 108 is deposited in one step and then planarized by CMP for a predetermined amount of time to obtain a planarized surface. Alternatively, the insulating layer 108 may be deposited as two separate sub-layers, where a first sub-layer is formed between the electrodes 204, a second sub-layer is formed over the electrode 204, 1 sub-layer. The first CMP step can be used to planarize the first sub-layer using the barrier layer 202 as a polishing stop. The second CMP step can be used to planarize the second sub-layer for a predetermined amount of time to obtain a flat surface.

The insulating layer 108 is then photolithographically patterned to form openings 110 that extend to the top surface of the barrier 202 of the electrode 204 and expose it. The opening 110 should have substantially the same pitch and approximately the same width as the lower electrode 204 so that each semiconductor pillar 300 shown in FIG. 8C is formed on each electrode 204. Some misalignment is allowed. The resulting structure is shown in Figure 8B.

8C, a vertical semiconductor pillar 300 is selectively formed within the opening 110 over the TiN barrier 202. [ The pillar semiconductor material may be germanium or germanium rich silicon germanium. For the sake of brevity, this description describes a semiconductor material as germanium, but it will be understood that a skilled practitioner may alternatively select any suitable material.

Germanium pillar 300 may be selectively deposited by low pressure chemical vapor deposition (LPCVD) on a thin Si seed layer located over a TiN barrier as shown in Figure 8C. For example, the method disclosed in U.S. Application Serial No. 11 / 159,031, filed June 22, 2005, which is incorporated herein by reference, was disclosed in U.S. Patent Application Publication No. 2006/0292301 A1, which will be used to deposit a Ge pillar . Preferably, the entire pillar 300 is selectively deposited. However, in a less preferred embodiment, only about the first 20 nm of the pillar 300 deposited on the seed layer / TiN barrier should have a high selectivity for silicon dioxide to prevent sidewall shorting of the diode, May be selectively deposited.

For example, as illustrated in Figure 9a, the thin Si seed layer is deposited on TiN by flowing 500 sccm of SiH 4 for 60 minutes and at a pressure of 380 ℃ 1 Torr. Thereafter, the silane flow is stopped and a flow of 100 sccm GeH 4 is at the same temperature and pressure to deposit the Ge. Ge can be deposited at temperatures less than 380 [deg.] C, such as, for example, 340 [deg.] C. The SEM image of Figure 9A shows that after about 10 minutes of deposition, about 40 nm of germanium was selectively deposited on the Si seed layer located on the TiN layer. As shown in FIG. 9B, no germanium deposition is observed on the SiO 2 surface when the TiN layer is omitted. By using two-stage deposition in a state where both steps are performed at a temperature of 380 ° C or less, Ge can be selectively deposited on TiN and not on adjacent SiO 2 surfaces. An example of a two-step deposition of a flat Ge film is described in US Pat. ratio. Is described in SB Herner, " Electrochmical and Solid-State Letters (9 (5) G161-G163) (2006). Preferably, the silicon seed layer is deposited at a temperature less than 440 DEG C, and the germanium pillar is deposited at a temperature less than 400 DEG C.

In a preferred embodiment, the pillar includes a semiconductor junction diode. The term junction diode is used herein to refer to a semiconductor device having non-ohmic conduction characteristics with two terminal electrodes, which are made of a semiconductor material that is p-type at one electrode and n-type at the other electrode Is used. An example would be an n-type semiconductor material and a p-type semiconductor material, such as a pin diode and a zener diode, in which an intrinsic (undoped) semiconductor material is interposed between the p-type semiconductor material and the n- Gt; np < / RTI > diode.

The bottom highly doped region 112 of the diode 300 may be formed by selective deposition and doping. Germanium may be deposited and then doped, but by flowing a doping agent-containing gas (i. E. In the form of phosphorus gas added to the germanium gas) that provides an n-type dopant atom, for example phosphorus, during the selective CVD of germanium It is preferable to be doped in the field. The highly doped region 112 may preferably be about 10 to about 80 nm thick.

The intrinsic diode region 114 may then be formed by a selective CVD method. The intrinsic region 114 deposition may be performed during a separate CVD step or by stopping the flow of dopant gas such as phosphorus during the same CVD step as deposition of the region 112. [ The intrinsic region 114 may be about 110 to about 330 nm thick, preferably about 200 nm thick. A selective CMP process is then performed to remove any bridged intrinsic germanium on top of the insulating layer 108 and planarize the surface for preparation for subsequent lithography steps. Next, the p-type upper region 116 is formed by the selective CVD method. Deposition of the p-type top region 116 may be performed during a separate CVD step from the region 114 deposition step and during the same CVD step as the deposition of the region 114, the flow of dopant gas, such as boron trichloride, . ≪ / RTI > The p-type region 116 may be about 10 to about 80 nm thick. An optional CMP process can then be performed to remove any crosslinked p-type germanium on top of the insulating layer 108 and planarize the surface to prepare for subsequent lithography steps. Alternatively, the p-type region 116 may be formed by ion implantation into the upper region of intrinsic region 114. The p-type dopant is preferably boron or BF 2 . The formation of the p-type region 116 completes the formation of the pillar type diode 300. The resulting structure is shown in Figure 8c.

In an exemplary embodiment, the bottom region 112 is N + (heavily doped n-type) and the top region 116 is P + . However, the vertical pillar may also include other structures. For example, the bottom region 112 may be P + with the N + top region 116. Additionally, the intermediate region may be intentionally lightly doped, intrinsic, or intentionally undoped. The undoped region is absolutely not completely electrically neutral and always has defects or contaminants, which causes the undoped region to act as if it is slightly n-doped or p-doped. These diodes can be regarded as pin diodes. Thus, P + / N - / N +, P + / P - a / P + or N + / P _ / P + diode may be formed - / N +, N + / N.

The pitch and width of the pillars 300 are formed by the openings 110 and can be varied as needed. In one preferred embodiment, the pitch of the pillars (the distance from the center of one pillar to the center of the next pillar) is about 300 nm, and the width of the pillars varies between about 100 and about 150 nm. In another preferred embodiment, the pitch of the pillars is about 260 nm, and the width of the pillars varies between about 90 and about 130 nm. In general, the pillar 300 preferably has a substantially cylindrical shape having a circular or substantially circular cross section with a diameter of 250 nm or less.

8D, the upper electrode 400 may be formed by depositing Ti (bottom) / Al / TiN (top) or Ti / TiN / Al / TiN or Ti / Al / TiW or any combination of these layers So that it can be formed in the same manner as the bottom electrode 204. The TiN or TiW layer on the top may serve as an antireflective coating for patterning the conductor and as a polishing stop material for subsequent CMP of the insulating layer 500 as described below. The conductive layer described above is patterned and etched using any suitable masking and etching techniques to form a substantially planar, substantially planar area conductor rail 400 that extends perpendicular to the conductor rail 204. In a preferred embodiment, a photoresist is deposited, patterned by photolithography, the layer is etched, and then the photoresist is removed using standard processing techniques. Alternatively, a layer of selective insulation oxide, nitride, or oxynitride may be formed on the highly doped region 116, and a conductor 400 may be fabricated as described in < RTI ID = 0.0 > U.S. Patent Application No. 11 / 444,936, entitled "Conductive Hardmask for Protecting Patterned Features During Trench Etching," by Radigan et al.

Next, another insulating layer 500 is deposited over and between the conductor rails 400. The layer 500 material may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this insulating material. This insulating layer can be planarized together with the top surface of the conductor rail 400 by CMP or etchback. A three dimensional view of the resulting device is shown in Figure 8e.

In the above description, the barrier layer 202 is formed before the insulating layer 108 is deposited. Alternatively, the order of the manufacturing steps may be changed. For example, an insulating layer 108 having openings may be formed first on the conductor 204, prior to selectively forming a tungsten nitride pattern in the opening to facilitate subsequent germanium or germanium rich silicon germanium deposition .

A pillar device, such as a diode device, may include a one time programmable (OTP) or rewritable nonvolatile memory device. For example, each diode pillar 300 may act as a steering element of a memory cell and other material or layer 118 acting as a resistance switching material (i.e., storing data) Is provided in series with the diode (300) between the electrodes (204, 400). In particular, FIG. 8E illustrates an embodiment of a method of fabricating a semiconductor device in accordance with the principles of the present invention, including but not limited to an anti-fuse (i.e., an anti-fuse dielectric), a fuse, a polysilicon memory effect material, a metal oxide (such as nickel oxide, perovskite material, One nonvolatile memory cell including a pillar diode 300 in series with a resistive switching material 118, such as a metal oxide, a conductive bridge element, or a switchable polymer. A resistive switching material 118, such as a thin silicon oxide anti-fuse dielectric layer, is deposited over the diode pillar 300 and subsequently the top electrode 400 may be deposited on the anti-fuse dielectric layer. Alternatively, the resistance switching material 118 may be located under the diode pillar 300, such as between the conductive layers 200 and 202. [ In this embodiment, the resistance of the resistance switching material 118 is increased or decreased in response to the forward and / or reverse bias provided between the electrodes 204,

In another embodiment, the pillar diode 300 itself may be used as a data storage device. In this embodiment, the resistance of the filament diode 300 is described in U. S. Patent Application Serial No. 10 / 955,549, filed September 29, 2004, both of which are herein incorporated by reference in their entirety, As described in U.S. Patent Application No. 11 / 693,845 (corresponding to US Patent Application Publication No. 2007/0164309 A1), filed March 30, 2007, Forward and / or reverse bias. In this embodiment, the resistance switching material 118 may be omitted if necessary.

The formation of the first memory level has been described. Additional memory levels may be formed over the first memory level to form a monolithic three-dimensional memory array. In some embodiments, the conductors may be shared between memory levels, i.e., the upper conductor 400 may function as a bottom conductor of the next memory level. In another embodiment, an interlevel dielectric (not shown) is formed over the first memory level, its surface is planarized, and a configuration of a second memory level may be initiated on the planarized interlevel dielectric without any shared conductors.

A monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a wafer, without any substrate intervention. The layers forming one memory level are deposited or grown directly on top of existing levels or layers of levels. In contrast, a stacked memory is constructed by forming memory levels on separate substrates, such as in Lydy's U. S. Patent No. 5,915, 167 "Three Dimensional Structure Memory ", and bonding these memory levels onto one another. Although the substrates may be thinned or removed from memory levels prior to bonding, such memories are not true monolithic three dimensional memory arrays, since memory levels are initially formed on separate substrates. In contrast to the process described in Reddy, in an embodiment of the present invention, the diode shares a conductive wire or electrode between two adjacent layers. In this structure, the "bottom" diode will "orient" the opposite direction to the diode in the "top" layer (i.e., the layer of the same conductivity type in each diode is in electrical contact with the same wire or electrode located between the diodes) . In this structure, the two diodes can share the wire between them, but still have no read or write disturb problem.

The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or virtually any number of memory levels may be formed on the substrate in such a multilevel array.

In summary, a method of fabricating a germanium pillar device by selective deposition of Ge or Ge rich SiGe into an etched opening in an insulating layer has been described. By filling the semiconductor pillar openings, some difficulties of the conventional subtractive method are overcome and eight processing steps can be eliminated in a four layer device. For example, a high aspect ratio oxide gap filling between the pillars may be omitted, which allows for the deposition of a simple blanket oxide film with good uniformity. A higher germanium pillar can be made with a depth of 8 microns in the deep opening in the insulating layer. The high diode reduces reverse leakage of the vertical device. In addition, alignment of the various layers becomes easier. All layers can be aligned to the main alignment mark without intermediate open frame etching.

On the basis of the teachings of the present invention, those skilled in the art are expected to be able to easily carry out the present invention. The description of the various embodiments provided herein is believed to provide those of ordinary skill in the art with a broad overview and detailed description of the invention. Although specific support circuits and fabrication steps have not been described in detail, such circuits and protocols are well known and no particular advantage is provided by specific modifications of these steps in the practice of the invention. It is also believed that one skilled in the art can, without undue experimentation, perform the present invention based on the teachings herein.

The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended to be illustrative, not limiting. Modifications and variations of the embodiments described herein may be made without departing from the spirit and scope of the invention based on the description provided herein. Only the following claims, including all equivalents, are intended to define the scope of the invention.

Claims (66)

  1. A method of manufacturing a semiconductor device,
    Providing a substrate comprising a conductive material and including a plurality of first conductive electrodes separated from each other by a first insulating layer;
    Forming a second insulating layer including a plurality of openings,
    The second insulating layer being located on the substrate,
    Wherein a first portion of an upper surface of the plurality of first conductive electrodes is physically exposed below the plurality of openings,
    And a second portion of the upper surface of the plurality of first conductive electrodes is covered by the second insulating layer
    Forming the second insulating layer;
    Forming a first semiconductor layer in a plurality of openings on the second insulating layer and the second insulating layer;
    Removing a first portion of the first semiconductor layer,
    The first conductive type second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer,
    The upper portions of the plurality of openings in the second insulating layer remain uncharged
    Removing a first portion of the first semiconductor layer,
    Forming a second semiconductor layer on top of the plurality of openings on the second insulating layer and the second insulating layer;
    Removing the first portion of the second semiconductor layer located above the second insulating layer
    Including,
    The second conductive type second portion of the second semiconductor layer remains on the upper portion of the plurality of openings in the second insulating layer to form a plurality of pillar type diodes in the plurality of openings,
    Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the conductive material of the plurality of first conductive electrodes,
    Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of first conductive electrodes by a first conductive type second portion of the first semiconductor layer.
  2. 2. The method of claim 1, wherein the first and second semiconductor layers comprise polycrystalline silicon, germanium or silicon-germanium, or amorphous silicon, germanium or silicon-germanium crystallized in a subsequent step.
  3. 3. The method of claim 2, wherein the first and second semiconductor layers comprise a polysilicon layer, wherein the first semiconductor layer comprises an n-type doped polysilicon layer during a deposition process, The opening having a half pitch of 45 nm or less, forming a positive photoresist over the second insulating layer, exposing the photoresist to radiation using an attenuated phase shift mask, patterning the exposed photoresist And an opening is formed by etching the opening in the second insulating layer using the photoresist patterned as a mask.
  4. 4. The method of claim 3, wherein the radiation comprises radiation having a wavelength of 193 nm.
  5. 2. The method of claim 1 wherein removing the first portion of the first semiconductor layer comprises planarizing the first semiconductor layer with the top surface of the second insulating layer, And selectively etching the first semiconductor layer remaining on top of the plurality of openings.
  6. 6. The method of claim 5, wherein the forming of the first semiconductor layer comprises: forming the intrinsic semiconductor layer; and before or after the step of planarizing the first semiconductor layer, Implanting a dopant of a first conductivity type into the first semiconductor layer to a predetermined depth to remain at the bottom,
    Wherein selectively etching the first semiconductor layer comprises etching a doped portion of the first semiconductor layer until the intrinsic portion of the first semiconductor layer is reached.
  7. 7. The method of claim 6, further comprising: detecting when an intrinsic portion of the first semiconductor layer is reached during the selective etching step;
    Doping the intrinsic portion of the first semiconductor layer with the dopant of the first conductivity type after the selective etching step
    ≪ / RTI >
  8. The method of claim 1, wherein forming the second semiconductor layer comprises:
    Forming the second semiconductor layer including an intrinsic semiconductor material over the second insulating layer and over the plurality of openings;
    Planarizing the second semiconductor layer with at least the upper surface of the second insulating layer using chemical mechanical polishing or etchback;
    implanting the dopant of the second conductivity type into the upper section of the second portion of the second semiconductor layer to form a pin-
    ≪ / RTI >
  9. In the intrinsic region of each diode of the n- type silicon oxide layer or a silicon-rich compared to SiO 2 between the region to claim 8, wherein - method of manufacturing a semiconductor device including forming a germanium capping layer.
  10. 2. The method of claim 1, wherein removing the first portion of the first semiconductor layer comprises:
    Planarizing the first semiconductor layer with a top surface of the second insulating layer using chemical mechanical polishing or etchback with optical termination point detection,
    And after the planarization step, the second portion of the first semiconductor layer remaining in the plurality of openings has a substantially planar top surface, the step of recessing the first semiconductor layer in the plurality of openings in the second insulating layer Selectively anisotropically etching the first semiconductor layer remaining on top of the plurality of openings in the second insulating layer with a level etch front
    ≪ / RTI >
  11. 2. The method of claim 1, wherein removing the first portion of the first semiconductor layer comprises:
    Planarizing the first semiconductor layer with an upper portion of the second insulating layer using chemical mechanical polishing or etchback with optical termination point detection,
    After the planarization step, the second portion of the first semiconductor layer remaining in the plurality of openings has an annular shape with a groove in the center portion so that the second semiconductor layer is recessed in the plurality of openings in the second insulating layer, Selectively etching the first semiconductor layer remaining on the upper portion of the plurality of openings in the insulating layer;
    ≪ / RTI >
  12. The method according to claim 1,
    The n-type region of the diode comprising a first vertical junction,
    Wherein the p-type region of the diode comprises a second vertical junction,
    Wherein the first and second vertical joint lines are not in contact with each other.
  13. The method of claim 1, further comprising forming an anti-fuse dielectric above and below the diode.
  14. The method according to claim 1,
    Wherein the plurality of first conductive electrodes are tungsten electrodes under the second insulating layer,
    And the tungsten electrode is nitrided to form a tungsten nitride barrier exposed in the plurality of openings in the second insulating layer.
  15. A method of manufacturing a semiconductor device,
    Forming a plurality of tungsten electrodes separated from each other by a first insulating layer;
    Nitriding the tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes;
    Forming a second insulating layer including a plurality of openings,
    The tungsten nitride barrier is exposed to the plurality of openings in the second insulating layer,
    A part of the upper surface of the plurality of tungsten electrodes is covered with the second insulating layer
    Forming the second insulating layer;
    And forming a plurality of pillar-shaped diodes on the tungsten nitride barrier in the plurality of openings in the second insulating layer,
    Wherein each of the plurality of pillar type diodes includes a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
    Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of tungsten electrodes,
    Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of tungsten electrodes by respective first semiconductor regions.
  16. 16. The method of claim 15, wherein the plurality of tungsten electrodes are rail-shaped electrodes extending horizontally along the longitudinal direction.
  17. 16. The method of claim 15, wherein forming the plurality of pillar-
    Forming a first semiconductor layer of a first conductivity type on the plurality of openings on the second insulating layer and the second insulating layer;
    The second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer to form the first semiconductor region and the upper portion of the plurality of openings in the second insulating layer remains uncharged Removing a first portion of the first semiconductor layer,
    Forming a second conductive type second semiconductor layer on the plurality of openings in the second insulating layer;
    ≪ / RTI >
  18. 16. The method of claim 15,
    The forming of the second insulating layer may include forming the second insulating layer on the plurality of tungsten electrodes, and subsequently forming a plurality of openings in the second insulating layer so as to expose the upper surface of the plurality of tungsten electrodes ; And
    Wherein the nitriding step is performed after the step of forming the plurality of openings in the second insulating layer so that the upper surface of the plurality of tungsten electrodes is nitrided through the plurality of openings in the second insulating layer.
  19. 19. The method of claim 18,
    The plurality of openings in the second insulating layer are partially misaligned with the plurality of tungsten electrodes,
    The step of forming the plurality of openings exposes at least a portion of the side wall of the tungsten electrode,
    Wherein the nitriding step forms a tungsten nitride barrier on exposed portions of the sidewalls of the plurality of tungsten electrodes and on the upper surface.
  20. 16. The method of claim 15,
    The nitriding step is performed prior to the step of forming the second insulating layer,
    Wherein forming the second insulating layer comprises forming the second insulating layer on the tungsten nitride barrier and subsequently forming a plurality of openings in the second insulating layer to expose the top surface of the tungsten nitride barrier And forming a gate electrode on the semiconductor substrate.
  21. 21. The method of claim 20, further comprising: after the step of forming a plurality of openings in the second insulating layer, a second nitridation step to enhance the tungsten nitride barrier and nitridate at least one side wall of the plurality of openings in the second insulating layer The method further comprising the step of:
  22. 21. The method of claim 20, wherein the first insulating layer separates adjacent tungsten electrodes from each other, and the nitriding step nitrides the top surface of the first insulating layer.
  23. 16. The method of claim 15, wherein the nitridation step comprises a plasma nitridation step.
  24. A method of manufacturing a semiconductor device,
    Forming a plurality of tungsten electrodes separated from each other by a first insulating layer;
    Selectively forming a plurality of conductive barriers on the exposed upper surface of the tungsten electrode;
    Forming a second insulating layer including a plurality of openings,
    The plurality of conductive barriers are exposed to the plurality of openings in the second insulating layer,
    A part of the upper surface of the plurality of tungsten electrodes is covered with the second insulating layer
    Forming the second insulating layer;
    And forming a plurality of pillar-shaped diodes on the conductive barrier in the plurality of openings,
    Wherein each of the plurality of pillar type diodes includes a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
    Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of tungsten electrodes,
    Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of tungsten electrodes by respective first semiconductor regions.
  25. The method of manufacturing a semiconductor device according to claim 24, wherein the plurality of tungsten electrodes are rail-shaped electrodes extending horizontally along the longitudinal direction.
  26. 25. The method of claim 24,
    Wherein forming the plurality of pillar type diodes comprises:
    Forming a first semiconductor layer of a first conductivity type in a plurality of openings above the second insulating layer and the second insulating layer;
    The second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer and the upper portion of the plurality of openings in the second insulating layer remains unfilled. 1 < / RTI >
    Forming a second conductive type second semiconductor layer on the plurality of openings in the second insulating layer;
    ≪ / RTI >
  27. 25. The method of claim 24, wherein forming a plurality of conductive barriers comprises depositing a selective atomic layer of a barrier metal or metal alloy on the plurality of tungsten electrodes.
  28. 28. The method of claim 27, wherein the barrier metal or metal alloy comprises tantalum, niobium or an alloy thereof.
  29. 25. The method of claim 24, wherein forming the plurality of conductive barriers comprises selectively plating a barrier metal or metal alloy on the plurality of tungsten electrodes.
  30. 25. The method of claim 24,
    The forming of the second insulating layer may include forming the second insulating layer on the plurality of tungsten electrodes, and subsequently forming a plurality of tungsten electrodes on the second insulating layer to expose the upper surface of the plurality of tungsten electrodes. And forming an opening,
    The step of selectively forming a plurality of conductive barriers such that a plurality of conductive barriers are selectively formed on the upper surface of the plurality of tungsten electrodes through the plurality of openings in the second insulating layer comprises: After the step of forming the semiconductor device.
  31. 31. The method of claim 30,
    The plurality of openings in the second insulating layer are partially misaligned with the plurality of tungsten electrodes,
    Wherein forming the plurality of openings exposes at least portions of the sidewalls of the tungsten electrode,
    Wherein selectively forming the plurality of conductive barriers forms a conductive barrier on the exposed portions of the sidewalls of the plurality of tungsten electrodes and on the top surface thereof.
  32. 25. The method of claim 24,
    Wherein the step of selectively forming the plurality of conductive barriers is performed prior to the step of forming the second insulating layer,
    Wherein forming the second insulating layer comprises forming the second insulating layer on the plurality of conductive barriers, and subsequently forming the second insulating layer on the second insulating layer to expose the upper surface of the plurality of conductive barriers. And forming an opening of the semiconductor device.
  33. A method of manufacturing a semiconductor device,
    Forming a plurality of lower electrodes separated from each other by a first insulating layer on a substrate,
    Forming a second insulating layer including a plurality of first openings having a first width such that the lower electrode is exposed to the first openings;
    Forming a first semiconductor region of a first conductivity type in the first opening;
    Forming a sacrificial material in the plurality of first openings on the first semiconductor region,
    Forming a plurality of second openings in the second insulating layer to expose the sacrificial material, the second openings having a second width greater than the first width;
    Removing the sacrificial material from the first opening through the second opening;
    Forming a second conductive type second semiconductor region in the first opening,
    Wherein the first and second semiconductor regions form a plurality of pillar-shaped diodes in the first opening,
    Wherein each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of lower electrodes,
    Each pn junction in the plurality of pillar-shaped diodes is vertically separated from the plurality of lower electrodes by respective first semiconductor regions
    Forming the second semiconductor region;
    And forming an upper electrode in the second opening in the second insulating layer so that the upper electrode contacts the second semiconductor region.
  34. 34. The method of claim 33, further comprising forming an intrinsic third semiconductor region between the first and second semiconductor regions to form a p-i-n pillar-shaped diode.
  35. 35. The method of claim 34,
    Wherein the forming of the first semiconductor region comprises: forming a first semiconductor layer in the plurality of first openings above the second insulating layer and the second insulating layer; Removing a portion of the first semiconductor layer so as to remain at a lower portion of the first opening and to leave the upper portion of the plurality of first openings unfilled,
    Forming a second semiconductor region includes forming a second semiconductor layer on top of the plurality of first openings above the second insulating layer and the second insulating layer and subsequently forming a second semiconductor layer on the second semiconductor region, Removing a portion of the second semiconductor layer located above the second insulating layer so as to remain on top of the plurality of first openings in the insulating layer.
  36. A plurality of pillar type semiconductor diodes disposed on the substrate, the plurality of pillar type semiconductor diodes including a region of a first conductivity type located on a substrate and a region of a second conductivity type located above the region of the first conductivity type;
    A plurality of first conductive electrodes separated from each other by a first insulating layer;
    A second insulating layer overlying the first insulating layer and surrounding the sides of the plurality of pillar-shaped semiconductor diodes; And
    And a plurality of second electrodes in contact with the region of the second conductivity type,
    Wherein each of the plurality of pillar type semiconductor diodes is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
    Wherein each pn junction in the plurality of pillar-shaped semiconductor diodes is vertically spaced from the plurality of first conductive electrodes by a respective region of a first conductivity type,
    a) the region of the first conductivity type of the diode comprises a first vertical junction line, and the region of the second conductivity type of the diode comprises a second vertical junction line, wherein the first and second junction lines do not contact each other , or
    b) the sidewall of the region of the first conductivity type has a taper angle different from the sidewall of the region of the second conductivity type, and the discrete portion is located on the sidewall of the diode.
  37. 37. The device of claim 36, wherein the region of the first conductivity type of the diode comprises a first vertical junction line, the region of the second conductivity type of the diode comprises a second vertical junction line, Wherein the semiconductor device is not contacted.
  38. 38. The semiconductor device of claim 37, further comprising an intrinsic semiconductor region located between the region of the first conductivity type and the region of the second conductivity type.
  39. 38. The semiconductor device of claim 36, wherein the sidewalls of the region of the first conductivity type have a taper angle different from the sidewalls of the region of the second conductivity type and are located discontinuously in the sidewalls of the diode.
  40. 40. The method of claim 39,
    The region of the first conductivity type has a narrower taper angle than the region of the second conductivity type,
    An intrinsic semiconductor region is located between the first and second conductivity type regions,
    Wherein the discontinuous portion includes a step on a sidewall of the diode between the intrinsic semiconductor region and the region of the first conductivity type.
  41. 37. The method of claim 36,
    a) the region of the first conductivity type of the diode comprises a first vertical junction line, the region of the second conductivity type of the diode comprises a second vertical junction line, the first and second junction lines do not contact each other,
    b) the sidewall of the region of the first conductivity type has a taper angle different from the sidewall of the region of the second conductivity type, and the discrete portion is located on the sidewall of the diode.
  42. Board;
    Tungsten electrode;
    A tungsten nitride barrier on said tungsten electrode;
    A pillar type diode located on the tungsten nitride barrier; And
    And an upper electrode disposed on the pillar type diode,
    The pillar type diode comprising a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
    Wherein the pillar type diode is located on a horizontal plane including an upper surface of the tungsten electrode,
    Wherein the pn junction in the pillar-shaped diode is vertically spaced from the tungsten electrode by the first semiconductor region.
  43. 43. The semiconductor device of claim 42, wherein the pillar-shaped diode comprises a p-i-n diode.
  44. 45. The semiconductor device of claim 43, wherein the pillar-shaped diode is partially misaligned with the tungsten electrode, the tungsten nitride barrier being located at least a portion of a sidewall of the tungsten electrode and an upper surface of the tungsten electrode.
  45. 44. The semiconductor device of claim 43, further comprising a first oxide insulating layer located around the diode, wherein a portion of the first oxide insulating layer located adjacent at least one sidewall of the pillar-shaped diode is nitrided.
  46. 44. The semiconductor device of claim 43, further comprising a second oxide insulating layer positioned adjacent to the tungsten electrode, wherein an upper portion of the second oxide insulating layer is nitrided.
  47. A method for fabricating a pillar diode,
    Forming a titanium nitride pattern on a plurality of first conductive electrodes separated from each other by a first insulating layer on a substrate;
    Forming a second insulating layer on the titanium nitride pattern;
    Forming an opening in the second insulating layer to expose the titanium nitride pattern;
    Forming a silicon seed layer in an opening portion on the titanium nitride pattern,
    Selectively depositing a silicon germanium material containing a first conductivity type of germanium or 50 atomic percent or more germanium on the silicon seed layer at the opening,
    Selectively depositing a silicon germanium material containing intrinsic germanium or more than 50 atomic percent germanium on the silicon germanium material containing germanium of the first conductivity type or germanium of at least 50 atomic percent,
    implanting a dopant of the second conductivity type into the upper portion of the silicon germanium material containing germanium of the first conductivity type or germanium of greater than 50 atom percent to form a pin diode,
    Wherein each of the plurality of the filament diodes is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
    Wherein each intrinsic semiconductor material portion in the plurality of the pillar diodes is vertically spaced from the plurality of first conductive electrodes by a respective portion of the first conductive type germanium or silicon germanium material portion containing at least 50 atomic percent germanium , A method for manufacturing a pillar diode.
  48. 48. The method of claim 47, wherein the semiconductor material is germanium.
  49. 48. The method of claim 47, wherein the semiconductor material is a silicon germanium material containing at least 50 atomic percent germanium.
  50. 48. The method of claim 47, further comprising forming an anti-fuse dielectric layer on or under the diode.
  51. A method of manufacturing a pillar device,
    Providing a plurality of first conductive electrodes separated from each other by a first insulating layer;
    Forming a second insulating layer having an opening,
    Selectively depositing a silicon germanium material containing germanium or at least 50 atomic percent germanium into the opening to form a pillar device surrounded by the second insulating layer,
    The pillar device comprising a first semiconductor region having a doping of a first conductivity type and a second semiconductor region overlying the first semiconductor region and having a doping of a second conductivity type,
    The pillar device is selected from a pn diode and a pin diode,
    Wherein the pillar device is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
    Wherein the pn junction or intrinsic semiconductor material portion in the pillar device is vertically separated from the plurality of first conductive electrodes by the first semiconductor region.
  52. 52. The method of claim 51, wherein the semiconductor material is germanium.
  53. 52. The method of claim 51, wherein the semiconductor material is a silicon germanium material containing at least 50 atomic percent germanium.
  54. 52. The method of claim 51, wherein the opening in the insulating layer is exposed to titanium nitride, titanium tungsten, or tungsten nitride.
  55. 55. The method of claim 54, further comprising depositing a silicon seed layer on titanium nitride, titanium tungsten, or tungsten nitride.
  56. 56. The method of claim 55, wherein the silicon seed layer is deposited by chemical vapor deposition at a temperature of less than 440 占 폚.
  57. 56. The method of claim 55, wherein the semiconductor material is selectively deposited on the seed layer.
  58. 58. The method of claim 57, wherein the semiconductor material is selectively deposited by chemical vapor deposition at a temperature of less than 440 占 폚.
  59. 55. The method of claim 54,
    Forming a titanium nitride, titanium tungsten, or tungsten nitride pattern on the substrate;
    Forming a second insulating layer on the titanium nitride, titanium tungsten, or tungsten nitride pattern;
    Forming an opening in the second insulating layer to expose the titanium nitride, titanium tungsten, or tungsten nitride pattern
    ≪ / RTI >
  60. 55. The method of claim 54,
    Forming the second insulating layer on the substrate;
    Forming an opening in the second insulating layer;
    Selectively forming a pattern of titanium nitride, titanium tungsten, or tungsten nitride in the opening
    ≪ / RTI >
  61. 52. The method of claim 51, wherein the plurality of first conductive electrodes are rail-shaped electrodes extending horizontally along the longitudinal direction.
  62. 62. The method of claim 61, wherein selectively depositing a silicon germanium material containing germanium or greater than 50 atomic percent germanium in the opening comprises selectively depositing a silicon germanium material containing a germanium of the first conductivity type or greater than 50 atomic percent germanium The method comprising the steps of:
  63. 63. The method of claim 62,
    Selectively depositing a silicon germanium material containing intrinsic germanium or greater than 50 atomic percent germanium into the opening in the material of the first conductivity type,
    implanting a dopant of the second conductivity type into the upper portion of the silicon germanium material containing intrinsic germanium or greater than 50 atomic percent germanium to form a pin diode
    ≪ / RTI >
  64. 63. The method of claim 62,
    Selectively depositing a silicon germanium material containing intrinsic germanium or more than 50 atomic percent germanium into the opening on the first conductive semiconductor material,
    selectively depositing a silicon germanium material containing a germanium of the second conductivity type or greater than 50 atomic percent germanium into the opening on the silicon germanium material containing the intrinsic germanium or the germanium of greater than 50 atomic percent to form a pin diode
    ≪ / RTI >
  65. 62. The method of claim 61, further comprising forming an anti-fuse dielectric layer on or under the diode.
  66. 63. The method of claim 61, wherein the pillar device is a non-volatile memory device.
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