KR20100128724A - A fabricating method of buried contact solar cell - Google Patents

Abstract

PURPOSE: A manufacturing method is provided to simplify the entire process by simultaneously executing the surface texturing process and groove forming process of a semiconductor substrate through a single etching process. CONSTITUTION: A porous mask layer(110) is formed on a semiconductor substrate(100). A patterned porous mask layer(110') is formed by removing a part of the porous mask layer. A groove for a surface texturing and a groove for a front electrode are simultaneously formed on the semiconductor substrate by using the patterned porous mask layer. A selective emitter layer(120) is formed on the semiconductor substrate. A reflection barrier layer(130) is formed on the emitter layer.

Description

Manufacturing method of recessed electrode solar cell {A FABRICATING METHOD OF BURIED CONTACT SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a method of manufacturing a recessed electrode type solar cell in which a groove for a front electrode is formed on a surface of a semiconductor substrate and an electrode is formed in the groove.

Recently, as the prediction of depletion of existing energy sources such as oil and coal is increasing, interest in alternative energy to replace them is increasing. Among them, solar cells are particularly attracting attention because they are rich in energy resources and have no problems with environmental pollution. Solar cells include solar cells that generate steam for rotating turbines using solar heat, and solar cells that convert photons into electrical energy using the properties of semiconductors. Refers to photovoltaic cells (hereinafter referred to as "solar cells").

The solar cell uses the photovoltaic effect of the semiconductor, and is made by combining a p-type semiconductor and an n-type semiconductor. When light enters a portion (pn junction) where the p-type semiconductor and the n-type semiconductor come into contact with each other, negative charges (electrons) and positive charges (holes) are generated within the semiconductor by the light energy. The electrons and holes generated by the light energy move to the n-type semiconductor side and the p-type semiconductor side by the internal electric field, and are collected at both electrode portions. Connecting these two electrodes with wires allows the current to flow and can be used as power from the outside.

Such solar cells can be classified into screen printing solar cells (hereinafter abbreviated as 'SPSC') and buried electrode solar cells (hereinafter abbreviated as 'BCSC') according to the electrode type. Can be.

The 'SPSC' is generally easy to manufacture, but the energy conversion efficiency is low. This is due to reflection at the metal electrode, resistance due to back current flow and high recombination rates of carriers in the deeply doped emitter regions. In addition, in the SPSC, the short-circuit current density and blue response characteristics are poor.

On the other hand, although the 'BCSC' has a disadvantage in that the manufacturing cost is more expensive than the 'SPSC' and the process is complicated, the research on 'BCSC' has recently been made due to the advantage of significantly improving the conversion efficiency.

1 shows a manufacturing process diagram of a general 'BCSC'. For convenience of description, a semiconductor substrate which is a manufacturing material of 'BCSC' will be described taking a crystalline silicon (Si) substrate as an example.

Referring to FIG. 1, first, a silicon substrate is cut to a required size, and a cutting and etching process for removing surface defects or damages of the silicon substrate generated during cutting is performed (S10).

A texturing process is performed on the silicon substrate after the etching process by using a reactive ion etching (RIE) method or a wet etching method (S12). When the texturing process is performed, the entire surface of the silicon substrate is formed to reduce reflection of incident light.

A first doping process is performed to form a low concentration emitter layer by doping the texturized silicon substrate with another type of dopant (dopant) (S14). Here, if the emitter layer is formed by doping at a high concentration, a high concentration of dopants present on the surface is present in the silicon substrate to form agglomerates, thereby reducing the life of the charge to increase the operating efficiency of the solar cell Can be degraded. That is why it forms a low concentration of emitter layers.

After the low concentration emitter layer is formed, a first by-product removal process for removing by-products generated when the low concentration emitter layer is formed is performed (S16). The by-product refers to Phosphor-Silicate Glass (PSG) generated when the n-type dopant is diffused on the p-type substrate or BSG (Boro-Silicate Glass) generated when the p-type dopant is diffused on the n-type substrate. Since the PSG or BSG serves to shield the battery current, the PSG or BSG should be removed using an etching solution in order to increase battery efficiency.

When the by-products are removed, a process of forming an anti-reflection film to prevent solar reflection on the low concentration emitter layer is performed (S18). The anti-reflection film also serves as a surface passivation layer of the silicon substrate.

After the anti-reflection film is formed, a process of forming a groove for the front electrode to the inside of the front surface of the silicon substrate is performed (S20). The groove is a space where a buried electrode is to be formed, and is formed using a laser or a cutting saw.

When the groove is formed, a second doping process is performed to form a high concentration emitter layer by doping a silicon substrate with another type of impurities on the groove surface to reduce contact resistance with the recessed electrode (S22). As such, forming an emitter layer having different concentrations through the first doping process and the second doping process is called a selective emitter layer.

After the high concentration emitter layer is formed, a second byproduct removal process for removing the by-products generated when the high concentration emitter layer is formed is performed (S24). The byproduct refers to PSG or BSG, as described above.

Subsequently, a process of forming an electrode using a metal paste is performed on all portions of the groove and the rear surface formed on the front surface of the silicon substrate (S26). The metal paste may be silver (Ag), aluminum (Al), or the like. In this case, screen printing may be used. The electrode formed on the front side serves to collect electrons generated by solar absorption, and the electrode formed on the back side increases the light reflection on the back side of the silicon substrate and prevents recombination of electrons.

The heat treatment process is performed such that the electrodes formed on the front and rear surfaces are electrically connected to the silicon substrate (S28). In this case, the metal paste is diffused by a predetermined thickness on the back surface of the silicon substrate to form a back surface field (BSF). The 'BSF' forms an electric field and prevents photoexcited electrons from moving to the rear surface of the silicon substrate.

Meanwhile, the formed front electrode may perform a front electrode function by itself, but may also be used as a seed layer. In this case, a process of forming a plating layer on the formed front electrode may be further performed (S30). This may reduce the resistance of the front electrode and increase the aspect ratio of the completed 'BCSC' substrate.

However, the conventional manufacturing method of 'BCSC' has the following problems.

First, when the groove is formed using a laser or a cutting saw, physical damage may be caused to the silicon substrate. In particular, when the groove is formed using a laser, recrystallization occurs on the surface and the inside of the substrate due to the high temperature. This causes a recombination of carriers generated by absorbing light, which increases the surface recombination rate and reduces the life time of the carrier.

Next, the first and second doping processes must be performed to form the selective emitter layer. This is a complicated process when forming a selective emitter layer, and thus there is a problem that the process cost increases.

In addition, the doping process typically performs a heat treatment process to diffuse impurities into the silicon substrate, and such a high temperature heat treatment process acts as a cause of lowering the quality of the silicon substrate. However, the 'BCSC', as described above, is performing the first and second doping processes, which causes a problem of further degrading the quality of the silicon substrate.

Accordingly, an object of the present invention is to solve the above problems, and to provide a method of manufacturing a recessed electrode type solar cell which prevents a reduction in the life time of a carrier when grooves are formed in a semiconductor substrate.

Another object of the present invention is to perform the groove forming process and the surface texturing process in one etching process.

Another object of the present invention is to simplify the process of forming a selective emitter layer.

According to a feature of the present invention for achieving the object as described above, the present invention comprises a porous mask layer forming step of forming a porous mask layer (Porous Mask Layer) on top of the semiconductor substrate; A patterning step of removing a portion of the formed porous mask layer to form a patterned porous mask layer; An etching step of simultaneously performing surface texturing and forming grooves for the front electrode on the semiconductor substrate by using the patterned porous mask layer; Upon completion of the etching step, an emi doped region on the semiconductor substrate that contacts the patterned porous mask layer at low concentration, and an dome region that is not in contact with the patterned porous mask layer at high concentration to form a selective emitter layer. Forming a layer; A removing step of removing the patterned porous mask layer; Forming an anti-reflection film on the emitter layer when the patterned porous mask layer is removed; An electrode forming step of forming a front electrode on an upper portion of the formed anti-reflection film corresponding to the groove for the front electrode, and forming a rear electrode on a rear surface of the semiconductor substrate; And a heat treatment step of performing heat treatment such that the formed front and back electrodes are electrically connected to the semiconductor substrate.

The porous mask layer is formed by any one of an etching method, a sputtering method, and an anodization method.

The porous mask layer is wet etching, dry etching, reactive ion etching (RIE), electrochemical etching (Electrochemical etching) so that the mask layer formed on the semiconductor substrate has a porosity. Etched by any one of the etching method is formed.

The mask layer is subjected to any one of chemical vapor deposition (CVD), evaporation, sputtering, spin coating, inkjet, screen printing, and thermal oxidation. By forming.

The sputtering method and the anodization method form a porous mask layer by forming a mask layer having a porosity on the semiconductor substrate.

The porous mask layer is formed of an oxide-based or nitride-based dielectric material having a high etching selectivity with respect to the semiconductor substrate.

The patterned porous mask layer is formed by any one of a photo-lithography method, an inkjet or screen printing method using an etching paste, and a laser ablation method using a laser. .

The surface texturing by the etching step is formed in a region of the semiconductor substrate that contacts the patterned porous mask layer, and the groove for the front electrode is formed in a region where the patterned porous mask layer is not in contact.

The etching step is performed by any one of reactive ion etching (RIE), plasma etching, and wet etching (Alkaline Wet Etching) methods.

When the etching step is performed by the reactive ion etching (RIE) method or the plasma etching method, the etching step is performed using a reaction gas of F series or Cl series, and the wet etching process. When carried out by Wet Etching, Alkaline Wet Etching), it is carried out using acid based chemicals or alkaline based chemicals or mixtures of the respective series.

According to the method of manufacturing a recessed electrode type solar cell of the present invention having such a configuration, reactive ion etching (RIE) is performed in a state in which a porous mask layer patterned in a predetermined shape is formed on a semiconductor substrate. ), The etching process is performed using a general etching method such as plasma etching, wet wet etching, and alkaline wet etching. Then, in one etching process, a surface texturing process is performed on the semiconductor substrate to which the patterned porous mask layer is in contact, and a groove forming process is simultaneously performed to the semiconductor substrate to which the patterned porous mask layer is not in contact. As described above, since the etching process is performed using a general etching method, there is an effect of preventing a decrease in the life time of a carrier, which occurs when a groove is formed using a laser as in the related art. .

Furthermore, since the surface texturing process and the groove forming process of the semiconductor substrate are simultaneously performed in one etching process, the process is simplified.

In addition, the patterned porous mask layer may be used as a diffusion barrier to form a selective emitter layer in a single doping process.

Therefore, in manufacturing the recessed electrode type solar cell, the entire process can be simplified, thereby reducing the process cost, and eventually, lowering the production cost can be expected.

In addition, since only one doping process is performed when the selective emitter layer is formed, the diffusion process, that is, the heat treatment process is performed only once, thereby preventing the quality of the semiconductor substrate from being degraded.

Hereinafter, a method of manufacturing a depressed electrode solar cell according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings. In the embodiment of the present invention, a crystalline silicon (Si) substrate as a semiconductor substrate as a material for manufacturing a solar cell will be described as an example.

2 is a manufacturing process diagram of the recessed electrode solar cell according to a preferred embodiment of the present invention, Figure 3 is a process diagram of the manufacturing method of the recessed electrode solar cell of Figure 2 is shown in cross-sectional view.

Referring to FIG. 2, a saw damage etching process of first cutting a silicon substrate into a required size and removing bonding and damage of a surface is performed (S100).

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등의 Oxide 계열 또는 Nitride 계열의 유전체 물질뿐만 아니라, 확산저지막(Diffusion Barrier)으로 사용가능한 페이스트(Paste)와, 유기물 등이 사용되는 것이 좋다. 상기 식각 선택비는 식각 작업시 두 물질이 식각되는 식각율의 비를 말한다.A process of forming a porous mask layer on the front surface of the etched silicon substrate is performed (S102). In this case, the porous mask layer should be formed to have a thickness and porosity such that plasma, gas, chemical, and the like can pass therethrough. In addition, the porous mask layer should be formed as a diffusion barrier in the doping process described below while having a high etching selectivity with the silicon substrate. Therefore, the porous mask layer,

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Oxide-based or Nitride-based dielectric materials as well as pastes and organic materials that can be used as diffusion barriers may be used. The etching selectivity refers to a ratio of etching rates at which two materials are etched during an etching operation.

In the present embodiment, the porous mask layer may be formed by three methods.

The first method is to form a low density porous mask layer by changing the deposition conditions. For example, when using a sputtering method, the sputtering gas collides very quickly with the surface of the target material, thereby forming a mask layer as atoms or molecules generated from the target material are irregularly deposited on the silicon substrate. Since the inside of the mask layer formed as described above includes bubbles or voids, a mask layer having a low density, that is, a porous mask layer is formed.

The second method is to oxidize the entire surface of the semiconductor substrate using an anodization method to form a porous mask layer. Since the anodization method is a known technique, description thereof will be omitted.

Lastly, first, a mask layer is deposited on the front surface of the semiconductor substrate, and then a predetermined etching operation is performed to form the porous mask layer so that the deposited mask layer has a porosity. In this case, the mask layer may be any one of chemical vapor deposition (CVD), evaporation, sputtering, spin coating, inkjet, screen printing, and thermal oxidation. Is deposited by one. The predetermined etching process may be performed by wet etching, dry etching, reactive ion etching (RIE), electrochemical etching, or the like.

When the porous mask layer is formed by any one of the above methods, a patterning process of removing a portion of the porous mask layer corresponding to a portion of the front surface of the silicon substrate in which a groove for a front electrode is to be formed. This is performed (S104). The patterning process is etched by a photo-lithography method, an inkjet or screen printing method using an etching paste, a laser ablation method, or the like.

After the patterned porous mask layer is formed, an etching process using the patterned porous mask layer is performed to simultaneously perform surface texturing and groove formation of a silicon substrate (S106). That is, when the etching process is performed, a groove for the front electrode is formed by directly acting an etching material (Plazma, Gas, Chemical, etc.) in the region where the porous mask layer is removed from the entire surface of the silicon substrate. During the formation, the region in which the porous mask layer is present is textured by an etching material (Plazma, Gas, Chemical, etc.) transmitted through the porous mask layer. At this time, the surface texturing means that the structure is formed to reduce the reflection of light incident on the surface of the silicon substrate.

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또는 상기 산 계열의 화학물질의 혼합물이 이용된다. 그리고, 상기 알카라인 계열의 화학물질은

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또는 상기 알카라인 계열의 화학물질의 혼합물이 이용된다. 그러나, 상기 산 계열의 화학물질과 알카라인 계열의 화학물질은 이에 한정되는 것은 아니고, 상기 마스크 층과 실리콘 기판 간의 식각 선택비가 좋은 화학물질이면 이용가능하다.Here, the etching process is carried out by a method such as reactive ion etching (RIE), plasma etching, wet etching (Alkaline Wet Etching). Among these, in the case of using the reactive ion etching and the plasma etching method, the etching gas (Gas) uses a reaction gas such as F series or Cl series. However, the etching gas is not limited thereto and may be used as long as the etching selectivity between the mask layer and the silicon substrate is high. In addition, when the wet etching method is used, an acid-based chemical or an alkaline-based chemical is used. The acid-based chemicals

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Or mixtures of these acid based chemicals are used. And, the alkaline chemicals are

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Or mixtures of the above alkaline chemicals are used. However, the acid-based chemicals and the alkaline-based chemicals are not limited thereto and may be used as long as the chemical selectivity between the mask layer and the silicon substrate is good.

When the etching process is completed, a doping process is performed using the patterned porous mask layer as it is but forming a selective emitter layer using a silicon substrate and other types of impurities (dopants) (S108). That is, when the doping process is performed, a region where the porous mask layer is removed, that is, around the groove for the front electrode, is doped at a high concentration by diffusing the dopant directly onto the silicon substrate, while the region where the porous mask layer is present is Since the dopant has to be diffused into the porous mask layer and then diffused into the silicon substrate, the diffusion rate is slowed to be relatively low doped. In this case, the patterned porous mask layer serves as a diffusion barrier.

The high concentration and low concentration doped to form a selective emitter layer, wherein the high concentration doped region is doped to have a surface resistance of more than 90 ohm / squar, the low doped region is 40 ohm / squa It is better to be doped to have the following surface resistance. In addition, the selective emitter layer may include diffusion using a tube furnace, diffusion using a belt furnace, spray, spin on dopant, plasma doping, and plasma doping. Doping) and the like.

As such, in the state in which the patterned porous mask layer is formed on the silicon substrate, the surface texturing and groove formation may be simultaneously performed on the silicon substrate by one etching process, and the selective emitter layer may be formed by one doping process. As a result, the entire process can be simplified when manufacturing the depressed electrode solar cell, thereby reducing the process cost.

When the selective emitter layer is formed, a process of removing the by-products generated when the selective emitter layer is formed and the porous mask layer is performed (S110). Since the by-product and the porous mask layer is a dielectric material of the same series (Oxide), it can be removed using the same etching solution. The by-product refers to Phosphor-Silicate Glass (PSG) generated when the n-type dopant is diffused on the p-type substrate, or BSG (Boro-Silicate Glass) generated when the p-type dopant is diffused on the n-type substrate. Since the PSG or BSG serves to shield the current of the battery, it must be removed to increase battery efficiency.

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등과 같이 1.1 ~ 2.5 사이의 굴절율을 가지는 유전체 물질로 형성하고, 이는 화학증착(CVD),스퍼터링(sputtering), 열 산화(thermal oxidation), 스프레이 등의 방법에 의해 형성된다. 이러한 반사방지막은 실리콘 기판의 표면 보호막(Passivation) 역할도 한다.After the by-products and the porous mask layer are removed, a process of forming an anti-reflection film to prevent solar reflection on the selective emitter layer is performed (S112). The anti-reflection film

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It is formed of a dielectric material having a refractive index between 1.1 and 2.5, and the like, and is formed by a method such as chemical vapor deposition (CVD), sputtering, thermal oxidation, spraying, or the like. The anti-reflection film also serves as a surface passivation layer of the silicon substrate.

Subsequently, a process of forming an electrode using a metal paste is performed on all portions of the front electrode groove and the rear surface of the silicon substrate (S114). Nickel (Ni), silver (Ag), chromium (Cr), aluminum (Al), and the like may be used as the metal paste. In this case, methods such as screen printing, stencil, inkjet, aerosol jet, sputtering, and evaporation may be applied. An electrode (hereinafter referred to as "front electrode") formed inside the groove for the front electrode serves to collect electrons generated by solar absorption, and an electrode formed on the rear surface (hereinafter referred to as "back electrode") is silicon. It serves to increase light reflection on the back of the substrate and to prevent recombination of electrons.

Then, the heat treatment process is performed at a high temperature of 700 degrees or more so that the front electrode and the rear electrode are electrically connected to the silicon substrate (S116). Then, the metal atoms in the front electrode penetrate into the antireflection film formed inside the front electrode groove, and thus the antireflection film formed inside the front electrode groove becomes the front electrode. Therefore, the front electrode is bonded to the silicon substrate to form a ohmic contact. In the back electrode, a metal paste of the back electrode is diffused on the silicon substrate by a predetermined thickness to form a back surface field (BSF). The rear electric field layer forms an electric field to prevent photoexcited electrons from moving to the rear surface of the silicon substrate.

Meanwhile, the front electrode on which the ohmic contact is formed may perform a function of the front electrode by itself, but may also be used as a seed layer. In this case, in order to lower the resistance of the front electrode and increase the aspect ratio, a plating process of forming a plating layer on the formed front electrode may be additionally performed (S118). In this case, the plating layer may be formed in plural. The plating layer may be a plating material such as copper (Cu), tin (Sn), chromium (Cr), silver (Ag), nickel (Ni), or a mixture of the plating materials.

Next, the process described with reference to FIG. 2 will be described again with reference to FIG. 3.

First, as illustrated in FIG. 3B, a porous mask layer 110 is formed on an upper surface of a silicon substrate 100 on which a saw damage etching process is performed as shown in FIG. 3A. In this case, the porous mask layer 110 has a thin thickness such that an etching material (Plazma, Gas, Chemical, etc.) is permeable while the etching selectivity with the silicon substrate is high, and a diffusion barrier film (Diffusion Barrier) It is good to be formed so that it can be used).

When the porous mask layer 110 is formed, a patterned porous mask layer is removed by removing a portion of the porous mask layer 110 corresponding to a portion where a groove for a front electrode is formed in the front surface of the silicon substrate 100. A patterning process for forming 110 'is performed. This is shown in Figure 3 (c).

Then, when the etching process is performed using the patterned porous mask layer 110 ′, an area that is not in contact with the patterned porous mask layer 110 ′ in the front surface of the silicon substrate as shown in FIG. 3 (d). The groove G for the front electrode is formed by directly acting an etching material (Plazma, Gas, Chemical, etc.) used in the etching process. In the region where the patterned porous mask layer 110 ′ is in contact with the patterned porous mask layer 110 ′ on the front surface of the silicon substrate, the etching material (Plazma, Gas, Chemical, etc.) is patterned. Through the porous mask layer 110 ′, surface texturing is performed by the transmitted etching materials (Plazma, Gas, Chemical, etc.). That is, the silicon substrate 100 ′ having the surface texturing is formed at the same time as the groove G for the front electrode is formed on the entire surface of the silicon substrate 100 by one etching process.

In this state, when a dopant of a different type from the silicon substrate 100 'is doped in the entire area of the front surface of the silicon substrate 100', a selective emi is formed on the top surface of the silicon substrate 100 '. A selective emitter layer 120 is formed. As shown in FIG. 3E, the selective emitter layer 120 has a region in contact with the patterned porous mask layer 110 ′ in the silicon substrate 100 ′. 110 ') acts as a diffusion barrier to form a low concentration emitter layer 122, while a relatively high concentration around the front electrode groove G formed in the silicon substrate 100'. The emitter layer 124 is to be formed. As such, the selective emitter layer 120 may be formed in a single doping process.

After the selective emitter layer 120 is formed on the front surface of the silicon substrate 100 ', the patterned porous mask layer 110' and the selective emitter layer 120 are formed as shown in FIG. 3 (f). After removal of by-products (PSG or BSG) generated during the formation, as shown in FIG. 3 (g), an anti-reflection film 130 is formed on the selective emitter layer 120 to prevent solar reflection.

Subsequently, as shown in FIG. 3 (h), the front electrode 142 is formed inside the front electrode groove G formed in the silicon substrate 100 ′, and the rear electrode 144 is formed on the entire area of the rear surface. To form.

In addition, a heat treatment process is performed such that the front electrode 142 and the rear electrode 144 are electrically connected to the silicon substrate 100 ′. Then, as shown in (i) of FIG. 3, metal atoms in the front electrode 142 penetrate into the anti-reflection film 130 formed in the front electrode groove G and are formed in the front electrode groove G. The anti-reflection film 130 becomes a front electrode. The front electrode 142 ′ thus formed is bonded to the silicon substrate to form a ohmic contact. The back electrode 144 is diffused to the silicon substrate 100 ′ by a predetermined thickness to form a back surface field (BSF) 146.

Meanwhile, the front electrode 142 'formed on the entire surface of the silicon substrate 100' may perform an electrode function by itself, but may also be used as a seed layer. In this case, as shown in FIG. 3 (j), the plating layer 148 is formed on the front electrode 142 '. In this embodiment, it is described that one plating layer 148 is formed. However, this is not necessarily the case, and two or more plating layers may be formed. The plating layer 148 is to lower the resistance of the front electrode 142 ′ and increase the aspect ratio.

As described above, the present invention described in the above embodiment uses the patterned porous mask layer 110 ′ formed on the silicon substrate, and thus the front electrode groove G and the surface of the front electrode in the silicon substrate 100 by one etching process. Simultaneous texturing can be performed and the selective emitter layer 120 can be formed by one doping process, which can simplify the process and thereby reduce the process cost.

Although described with reference to the illustrated embodiment of the present invention as described above, this is merely exemplary, those skilled in the art to which the present invention pertains various modifications without departing from the spirit and scope of the present invention. It will be apparent that other embodiments may be modified and equivalent. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

That is, as shown in this embodiment, the porous mask layer is formed on the silicon substrate, and the patterned mask layer is formed by patterning the formed porous mask layer. However, this is not necessarily the case, and in a state where a mask layer is formed on the silicon substrate, the mask layer may be patterned first, and then the patterned mask layer may be porous.

In addition, the patterned mask layer may be patterned in a state in which the mask layer is formed on all regions of the front surface of the silicon substrate, but by selectively depositing the mask layer using an inkjet or screen printing method, The patterned mask layer may be formed at one time without a separate patterning process.

1 is a process chart of the manufacturing method of a typical recessed electrode solar cell.

Figure 2 is a process chart of the manufacturing method of the recessed electrode solar cell according to a preferred embodiment of the present invention.

3 is a cross-sectional view illustrating a process diagram of a method of manufacturing the recessed electrode solar cell of FIG. 2.

* Description of the symbols for the main parts of the drawings *

100: silicon substrate 100 ': silicon substrate

110: porous mask layer 110 ': patterned porous mask layer

G: groove for front electrode 120: selective emitter layer

122: low concentration emitter layer 124: high concentration emitter layer

130: antireflection film 142: front electrode

144: rear electrode 146: rear electric layer

148: plating layer

Claims (10)

A porous mask layer forming step of forming a porous mask layer on the semiconductor substrate; A patterning step of removing a portion of the formed porous mask layer to form a patterned porous mask layer; An etching step of simultaneously performing surface texturing and forming grooves for the front electrode on the semiconductor substrate by using the patterned porous mask layer; Upon completion of the etching step, an emi doped region on the semiconductor substrate that contacts the patterned porous mask layer at low concentration, and an dome region that is not in contact with the patterned porous mask layer at high concentration to form a selective emitter layer. Forming a layer; A removing step of removing the patterned porous mask layer; Forming an anti-reflection film on the emitter layer when the patterned porous mask layer is removed; An electrode forming step of forming a front electrode on an upper portion of the formed anti-reflection film corresponding to the groove for the front electrode, and forming a rear electrode on a rear surface of the semiconductor substrate; And And a heat treatment step of performing heat treatment such that the formed front electrode and the rear electrode are electrically connected to the semiconductor substrate. The method of claim 1, The porous mask layer is a method of manufacturing a recessed electrode type solar cell, characterized in that formed by any one of an etching method, sputtering method, anodization method. 3. The method of claim 2, The porous mask layer is wet etching, dry etching, reactive ion etching (RIE), electrochemical etching (Electrochemical etching) so that the mask layer formed on the semiconductor substrate has a porosity. Method of manufacturing a recessed electrode type solar cell, characterized in that formed by etching by any one of the etching method. The method of claim 3, wherein The mask layer is subjected to any one of chemical vapor deposition (CVD), evaporation, sputtering, spin coating, inkjet, screen printing, and thermal oxidation. Method for producing a recessed electrode type solar cell, characterized in that formed by. 3. The method of claim 2, The sputtering method and the anodization method is a method of manufacturing a recessed electrode type solar cell, characterized in that to form the porous mask layer by forming a mask layer having a porous on the semiconductor substrate. The method of claim 1, The porous mask layer is a method of manufacturing a recessed electrode type solar cell, characterized in that formed of a dielectric material of oxide (Oxide) or nitride (Nidtride) series having a high etching selectivity with the semiconductor substrate. According to claim 1, The patterned porous mask layer is formed by any one of a photo-lithography method, an inkjet or screen printing method using an etching paste, and a laser ablation method. Method for producing a depressed electrode solar cell, characterized in that .. The method of claim 1, The surface texturing by the etching step is formed in a region of the semiconductor substrate in contact with the patterned porous mask layer, the groove for the front electrode is formed in a region in which the patterned porous mask layer is not in contact. Method of manufacturing an electrode type solar cell. The method of claim 8, The etching step is a recessed electrode type solar cell, characterized in that carried out by any one of reactive ion etching (RIE), plasma etching (Plasma Etching), wet etching (Acid Wet Etching, Alkaline Wet Etching) method Manufacturing method. The method of claim 9, wherein the etching step, When carried out by the reactive ion etching (RIE) method or the plasma etching method (Plasma Etching), it is carried out using a reaction gas of F series or Cl series, When the wet etching (Acid Wet Etching, Alkaline Wet Etching) method, characterized in that it is carried out using an acid-based chemicals or alkaline-based chemicals or a mixture of each series Method of manufacturing a recessed electrode solar cell.

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