KR20100128591A - Plasma display panel device - Google Patents

Abstract

PURPOSE: A plasma display panel device is provided to charge a panel capacitor with an opposite polarity through a resonance current. CONSTITUTION: A panel capacitor is formed between a scan electrode and a sustain electrode. First and second driving part supply first and second sustain signals to the scan electrode and the sustain electrode. A driver circuit(200) is connected between the first and second driving part and the panel capacitor and includes an inductor. The driver circuit generates a first current path during first falling period and generates a second current path during second rising period. The driver circuit generates a third current path during a second falling period and generates a four current path during the first rising period.

Description

Plasma display panel device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device which is easy to improve driving efficiency during sustain discharge and waveform freedom of a sustain signal.

In general, a plasma display panel is a partition wall formed between an upper substrate and a lower substrate to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because a thin and light configuration is possible.

In order to drive the plasma display panel, a driving circuit for supplying a driving signal to the scan electrode, the sustain electrode and the address electrode formed in the plasma display panel is required.

Recently, research is being conducted to simplify the driving circuit of the plasma display device and to improve the waveform freedom and driving efficiency for the sustain signal supplied to each of the scan electrode and the sustain electrode during the sustain discharge.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display device which is easy to improve driving efficiency during sustain discharge and waveform freedom of a sustain signal.

The plasma display device according to the present invention includes a panel capacitor formed between a scan electrode and a sustain electrode of a plasma display panel, and first and second drivers for supplying first and second sustain signals to the scan electrode and the sustain electrode for sustain discharge. And first and second resonant currents alternately connected to the scan electrode and the sustain electrode, respectively, connected between the first and second driving units and the panel capacitor and resonating in parallel with the panel capacitor to charge the panel capacitor with the opposite polarity. And a driving circuit including an inductor for supplying the first and second sustain signals, wherein the first and second sustain signals increase from a ground voltage to a sustain voltage, the first and second rising sections, the first and second sustain sections maintaining the sustain voltage, and Divided into first and second falling sections falling from the sustain voltage to the ground voltage And the driving circuit forms a first current path for the inductor to generate the first resonant current during the first falling section, and the first rising section after the end of the first falling section. A second current path is formed to supply a resonant current; a third current path is formed at the second falling section to generate the second resonant current; and after the end of the second falling section, the second current path is formed. The fourth current path is formed so that the first resonance current is supplied in one rising section.

In the plasma display device of the present invention, the panel capacitor is charged with the opposite polarity through the resonance current generated by the resonance between the panel capacitor and the inductor between the scan electrode and the sustain electrode, and the falling period of the sustain signal supplied to the scan electrode. The resonance current generated in the inductor is supplied to the sustain electrode in the rising period of the sustain signal supplied to the sustain electrode to be charged to the panel capacitor, and the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode are alternately supplied. This has the advantage of improving the waveform freedom of the sustain signal.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating a structure of a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. ) May be formed of a metal such as silver (Ag), chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the first embodiment of the present invention, the sustain electrode pairs 11 and 12 have not only a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also without the transparent electrodes 11a and 12a. Only the bus electrodes 11b and 12b may be constituted. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the first embodiment of the present invention is formed on the upper substrate 10. The first black matrix 15 and the transparent electrodes 11a and 12a are formed at positions overlapping the partition wall 21. ) And second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, and may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are physically separated.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, magnesium oxide (MgO) may be generally used for the protective film 14, and Si-MgO to which silicon (Si) is added may be used.

Here, the content of silicon (Si) added to the protective film 14 may be 60PPM to 200PPM based on the weight percent.

On the other hand, the address electrode 22 is formed in the direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In the first embodiment of the present invention, not only the structure of the partition wall 21 shown in FIG. 1 but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in the first embodiment of the present invention, although each of the R, G, and B discharge cells is shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

2 is a simplified diagram illustrating an electrode arrangement of a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 2, the plurality of discharge cells constituting the plasma display panel is preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only a first embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down or left and right in the center portion of the panel.

3 is a timing diagram of a method of time-division driving by dividing one frame into a plurality of subfields according to the first embodiment of the present invention.

The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to the first embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating a driving signal for driving a plasma display panel according to a first embodiment of the present invention.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. It may include a reset section for initializing the discharge cells of the entire screen by using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells. have.

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), thereby eliminating discharge discharge in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a scan signal having a negative scan voltage Vsc is sequentially applied to the scan electrode, and at the same time, a positive data signal is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. On the other hand, in order to increase the efficiency of the address discharge, a sustain bias voltage Vzb is applied to the sustain electrode during the address period.

During the address period, the plurality of scan electrodes Y may be divided into two or more groups, and scan signals may be sequentially supplied to each group, and each of the divided groups may be further divided into two or more subgroups and sequentially by the subgroups. Scan signals can be supplied. For example, the plurality of scan electrodes Y is divided into a first group and a second group, and scan signals are sequentially supplied to scan electrodes belonging to the first group, and then scan electrodes belonging to the second group Scan signals may be supplied sequentially.

According to the first embodiment of the present invention, the plurality of scan electrodes Y is divided into a first group located at an even number and a second group located at an odd number according to a position formed on a panel. In another embodiment, the display panel may be divided into a first group located above and a second group located below the center of the panel.

The scan electrodes belonging to the first group divided by the above method are further divided into a first subgroup located at an even number and a second subgroup located at an odd number, or the first group. The first subgroup positioned above and the second group positioned below may be divided based on the center of the.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The width of the first sustain signal or the last sustain signal among the plurality of sustain signals alternately supplied to the scan electrode and the sustain electrode in the sustain period may be greater than the width of the remaining sustain pulses.

After the sustain discharge occurs, an erase period for erasing the wall charge remaining in the scan electrode or the sustain electrode of the selected ON cell in the address period by generating a weak discharge may be further included after the sustain period.

The erase period may be included in all or some of the plurality of subfields, and the erase signal for the weak discharge is preferably applied to the electrode to which the last sustain pulse is not applied in the sustain period.

The cancellation signal is a ramp-type signal that gradually increases, a low-voltage wide pulse, a high-voltage narrow pulse, an exponential signal, or half Sinusoidal pulses can be used.

In addition, a plurality of pulses may be sequentially applied to the scan electrode or the sustain electrode to generate the weak discharge.

The driving waveforms shown in FIG. 4 are first examples of signals for driving the plasma display panel according to the present invention. The present invention is not limited to the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

The driving section of the plasma display panel may be divided into a power-on sequence section and a normal operation section. The waveforms of the driving signals supplied from the power-on sequence section and the normal operation section may be the same or different as necessary.

That is, when power is supplied to the plasma display device (Power ON), a power-on for preparing a normal operation of the device without displaying an image on the panel for a predetermined time or until the driving voltage to be supplied to the panel reaches a normal level. A power on sequence is performed. Thereafter, the image is displayed by the driving signals supplied to the panel in the normal operation section.

In addition, even before the power supply to the plasma display device is cut off, a power on sequence similar to the power on sequence exists to smoothly terminate the power supply to the driving circuit or the panel.

For example, during a predetermined time after power is supplied to the plasma display device, the data signal is not applied to the panel because the display enable signal has a value of "0" which is a low level. , No image is displayed on the panel. After the predetermined time has elapsed, if the disabling enable signal has a value of "1" which is a high level, the data signal is applied to the panel, and the image is displayed on the panel. In addition, during a predetermined time before the power supply to the plasma display device is terminated, the disabling enable signal again has a low level of "0", and thus no image is displayed on the panel.

5 is a block diagram illustrating a driving module for driving a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 5, the plasma display apparatus is installed on a rear surface of a plasma display panel (not shown) to support the plasma display panel and to absorb and emit heat from the heat dissipation frame 30 and the heat dissipation frame 30. A printed circuit board (PCB) is installed on a rear surface of the plasma display panel to supply a driving voltage to the plasma display panel.

The plasma display panel includes a plurality of scan electrodes (not shown), a sustain electrode (not shown), and an address electrode (not shown).

On the PCB, an address driver 50 for supplying a driving voltage to the plurality of address electrodes, a scan driver 60 for supplying a driving voltage to the plurality of scan electrodes, and a driving voltage for the plurality of sustain electrodes. The drive controller 80 and the address driver 50 and the scan driver 60 and the sustain hole that control the sustain driver 70, the address driver 50 and the scan driver 60, and the sustain driver 70 to supply A power supply unit (PSU) 90 for supplying power to the 70 and the control driver 80 is disposed.

The address driver 50 supplies a driving voltage to the plurality of address electrodes to select only discharge cells that are discharged among the plurality of discharge cells formed in the plasma display panel.

The address driver 50 may be installed on any one or both of the upper side and the lower side of the plasma display panel according to a single scan method or a dual scan method.

In the address driver 50, a data IC (not shown) is installed to control currents applied to the plurality of address electrodes, and in the data IC, switching is generated to control an applied current so that a large amount of heat may be generated. have. Therefore, a heat sink (not shown) may be installed in the address driver 50 to eliminate heat generated in the control process.

The scan driver 60 may include a scan sustain board 62 connected to the driving controller 80, and a scan driver board 64 connecting the scan sustain board 62 to the plasma display panel.

The scan driver board 64 may be divided into two parts, an upper side and a lower side. Unlike the scan driver board 64, the scan driver board 64 may be installed as a single piece or a plurality of scan driver boards.

The scan driver board 64 is provided with a scan IC 65 for supplying a driving voltage to the plurality of scan electrodes, and the scan IC 65 continuously applies reset, scan and sustain signals to the plurality of scan electrodes. can do.

The sustain driver 70 supplies a driving voltage to the plurality of sustain electrodes.

The control driver 80 converts the input image signal into data to be supplied to the address electrodes by performing predetermined signal processing on the input image signal using the signal processing information stored in the memory, and sorts the converted data according to a scanning order. have. In addition, the driving controller 80 supplies a timing control signal to the address driver 50, the scan driver 60, and the sustain driver 70, thereby providing the address driver 50, the scan driver 60, and the sustain. The driving signal supply timing of the driving unit 70 may be controlled.

In the case of the plasma display device according to the present invention, the driving voltage output from the sustain driver 70 may be supplied to the plurality of sustain electrodes through the connection member 66.

Here, one end of the connection member 66 is connected to a printed circuit board formed on the sustain driver 70, and the other end is connected to a pad electrode (not shown) connected to the plurality of sustain electrodes to supply a driving voltage.

In order to connect the printed circuit board (PCB) and the plurality of sustain electrodes formed on both surfaces of the heat dissipation frame 30 in opposite directions, the connection member 66 is preferably configured of a flexible printed circuit (FPC).

6 is a circuit diagram illustrating a driving circuit of a plasma display device according to a first embodiment of the present invention.

Referring to FIG. 6, the driving circuit 200 includes a sustain voltage source Vs for supplying a sustain voltage Vs, a first sustain driver 210 for supplying a first sustain signal to the scan electrode Y, and a sustain electrode. 9Z) in parallel with the second sustain driver 220 for supplying the second sustain signal to the panel capacitor Cp formed between the scan electrode Y and the sustain electrode Z, and the panel capacitor Cp has the opposite polarity. It includes an inductor (L) for supplying the first and second resonant current to be charged.

Here, the first sustain driver 210 is connected to the first sustain switch Ysus_up supplying the sustain voltage Vs, the first sustain switch Ysus_dn connected to the ground GND, and the scan electrode. And a first switch (Yer_up) for causing the potential of (Y) to drop from the sustain voltage (Vs) to the ground voltage.

That is, the first sustain switch Ysus_up has a drain connected to the sustain voltage source Vs and a source connected to the drain, scan electrode Y, and one end of the inductor L of the first susdown switch Ysus_dn. .

The source of the first susdown switch Ysus_dn is connected to the ground GND.

The first switch Yer_up has a drain connected to the other end of the inductor L and a source connected to the second sustain driver 220.

In addition, the second sustain driver 220 is connected to the second sustain switch Zsus_up for supplying the sustain voltage Vs, the second sustain switch Zsus_dn for supplying the ground voltage, and sustain. And a second switch Zr_up for causing the potential of the electrode Z to fall from the sustain voltage Vs to the ground voltage.

That is, the drain of the second sustain switch Zsus_up is connected to the sustain voltage source Vs, and the source of the second sustain switch Zsus_up is connected to the drain and the sustain electrode Z of the second sustain switch Zsus_dn.

The source of the second susdown switch Zsus_dn is connected to the ground GND.

The second switch Zer_up has a drain connected to the source of the second suspend switch Zsus_up, and a source connected to the other end of the inductor L.

FIG. 7 is a timing diagram illustrating turn on and turn off timings of the switches illustrated in FIG. 6, currents of first and second sustain signals and inductors, and FIGS. 8 to 13 are diagrams illustrating the first to sixth sections of FIG. A circuit diagram showing a current path according to switch on / off.

7 shows the turn-on and turn-off timings of the switches for supplying the first and second sustain signals and the first and second sustain signals supplied to the scan electrode Y and the sustain electrode Z, respectively, and the current of the inductor.

Here, the first and second sustain signals rise from the ground voltage GND to the sustain voltage Vs, a sustain period maintained at the sustain voltage Vs, and fall from the sustain voltage Vs to the ground voltage GND. It is divided into descending sections.

Referring to FIGS. 7 and 8, the first sustain signal is maintained at the ground voltage in the first period T1, and the second sustain signal is a falling section in which the second sustain signal falls from the sustain voltage to the ground voltage.

In this case, the scan electrode Y is turned on to maintain the ground voltage by forming a current path with the ground when the first susdown switch Ysus_dn is turned on.

The sustain electrode Z forms a current path in which the second switch Zer_up is turned on to drop from the sustain voltage Vs to the ground voltage through the first suspend switch Ysus_dn.

That is, in the first section T1, the scan electrode Y is maintained at the ground voltage, and the sustain electrode Z falls from the sustain voltage to the ground voltage, where the inductor L is in parallel with the panel capacitor Cp. The resonance causes the first resonance current I_1 to be generated.

Referring to FIGS. 7 and 9, the second section T2 is a rising section in which the first sustain signal rises from the ground voltage to the sustain voltage, and indicates that the second sustain signal is maintained at the ground voltage.

The scan electrode Y is supplied with the first resonance current I_1 generated by the inductor L_1 while the first susdown switch Ysus_dn is turned off, and the second switch Zer_up is turned on. Rises to the sustain voltage (Vs).

That is, the panel capacitor Cp increases the potential difference between the scan electrode Y and the sustain electrode Z to the sustain voltage Vs by the first resonant current I_1 supplied to the scan electrode Y.

In addition, the sustain electrode Z is maintained at the ground voltage by turning on the second suspend switch Zsus_dn.

Referring to FIGS. 7 and 10, the third section T3 is a sustain period in which the first sustain signal is maintained at the sustain voltage Vs, and indicates that the second sustain signal is maintained at the ground voltage.

In the scan electrode Y, the second switch Zer_up is turned off, and the first sustain switch Ysus_up is turned on to supply the sustain voltage Vs from the sustain voltage source Vs.

At this time, the sustain electrode Z maintains a state in which the second suspend switch Zsus_dn is turned on in the same state as that of the second section T3.

Referring to FIGS. 7 and 11, the fourth section T4 is a falling section in which the first sustain signal falls from the sustain voltage Vs to the ground voltage, and indicates that the second sustain signal is maintained at the ground voltage.

The scan electrode Y is turned down from the sustain voltage Vs to the ground voltage by turning on the first switch Yer_up.

At this time, the inductor L resonates in parallel with the panel capacitor Cp to generate the second resonant current I_2.

Here, the first and second resonant currents I_1 and I_2 represent currents having different polarities.

The sustain electrode Z maintains a state in which the second suspend switch Zsus_dn is turned on in the same state as that of the second section T3.

Referring to FIGS. 7 and 12, the fifth section T5 represents a rising section in which the first sustain signal is maintained at the ground voltage and the second sustain signal rises from the ground voltage to the sustain voltage Vs.

The scan electrode Y is maintained at the ground voltage by turning on the first susdown switch Ysus_dn.

The sustain electrode Z is maintained in a state where the first switch Yer_up is turned on and the second suspend switch Zsus_dn is turned off to supply the second resonance current I_2 generated by the inductor L.

That is, the potential difference between the scan electrode Y and the sustain electrode Z increases to the sustain voltage Vs by the second resonance current I_2 supplied to the sustain electrode Z.

Referring to FIGS. 7 and 13, the sixth period T6 represents a sustain period in which the first sustain signal is maintained at the ground voltage and the second sustain signal is maintained at the sustain voltage.

The scan electrode Y is maintained at the ground voltage by turning on the first susdown switch Ysus_dn.

In the sustain electrode Z, the first switch Yer_up is turned off, and the second sustain switch Zsus_up is turned on to supply the sustain voltage Vs from the sustain voltage source Vs.

Here, the portions of the first and second sustain signals do not overlap each other, and the first and second sustain signals rise from the ground voltage to the sustain voltage through the first and second resonant currents generated in the inductor, thereby increasing waveform freedom. Can be.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a perspective view illustrating a structure of a plasma display panel according to a first embodiment of the present invention.

2 is a simplified diagram illustrating an electrode arrangement of a plasma display panel according to a first embodiment of the present invention.

3 is a timing diagram of a method of time-division driving by dividing one frame into a plurality of subfields according to the first embodiment of the present invention.

4 is a timing diagram illustrating a driving signal for driving a plasma display panel according to a first embodiment of the present invention.

5 is a block diagram illustrating a driving module for driving a plasma display panel according to a first embodiment of the present invention.

6 is a circuit diagram illustrating a driving circuit of a plasma display device according to a first embodiment of the present invention.

FIG. 7 is a timing diagram showing the turn-on and turn-off timings of the switches shown in FIG. 6 and the currents of the first and second sustain signals and the inductor.

8 to 13 are circuit diagrams illustrating current paths according to switch on / off in the first to sixth sections shown in FIG. 7.

Claims (7)

First and second drivers for supplying first and second sustain signals to the scan electrodes and the sustain electrodes, respectively, for the panel capacitor and the sustain discharge formed between the scan electrodes and the sustain electrodes of the plasma display panel; And an inductor connected between the panel capacitor and the first and second resonant currents alternately supplied to the scan electrode and the sustain electrode so that the panel capacitor is charged with the opposite polarity by resonating in parallel with the panel capacitor. Including furnace, The first and second sustain signals may include first and second rising periods that rise from the ground voltage to the sustain voltage, first and second sustain periods maintained by the sustain voltage, and first and second falling to the ground voltage at the sustain voltage. Divided into 2 descending sections, The drive circuit, Forming a first current path for the inductor to generate the first resonance current during the first falling section, and supplying the first resonance current to the second rising section after the end of the first falling section; To form a current path, A third current path is formed by the inductor to generate the second resonance current in the second falling section, and then the first resonance current is supplied to the first rising section after an end point of the second falling section; And a four current paths. The method of claim 1, The first driving unit may include a first sustain switch that is turned on in the first holding section, a first suspension switch that is turned on when the second falling section and the second sustain signal are supplied, and the first rising section and the second rising section. It includes a first switch to turn on the falling section, The second driving unit may include a second sustain switch that is turned on in the second holding section, a second sustain switch that is turned on when the first falling section and the first sustain signal are supplied, and the second rising section and the first rising section. And a second switch for turning on a falling section. The method of claim 2, wherein each of the first and second susdown switches, And turn off the first and second rising sections and the first and second falling sections. The method of claim 2, wherein the first current path, And a ground formed between the scan electrode, the inductor, the second switch, the second suspend switch, and the ground to supply the ground voltage during the first falling section. The method of claim 2, wherein the second current path, And the scan electrode, the inductor, the second switch, and the sustain electrode are formed during the second rising period. The method of claim 2, wherein the third current path, And the sustain electrode, the first switch, the inductor, the first susdown switch, and a ground for supplying the ground voltage during the second falling section. The method of claim 2, wherein the fourth current path, And the sustain electrode, the first switch, the inductor, and the scan electrode are formed during the first rising period.

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