KR20080057983A - Plasma display apparatus - Google Patents

Abstract

A plasma display apparatus is provided to enhance the operation efficiency of a panel by implementing scan and sustain driving energy recovery circuits using one inductor. A plasma display apparatus includes scan and sustain drivers, an inductor, and first and second switches(ER1,ER2). The scan and sustain drivers supply driving signals to scan and sustain electrodes, respectively. The inductor is connected in parallel with the capacitance of panel(Cp) between the scan and sustain drivers so as to form a resonance circuit with the capacitance of panel. The first switch is connected between the scan driver and the inductor. The second switch is connected between the sustain driver and the inductor.

Description

Plasma display apparatus

1 is a perspective view showing an embodiment of a structure of a plasma display panel according to the present invention.

2 is a cross-sectional view illustrating an embodiment of an electrode arrangement of a plasma display panel.

FIG. 3 is a timing diagram illustrating an embodiment of a method of time-divisionally driving a plasma display panel by dividing one frame into a plurality of subfields.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel.

FIG. 5 is a diagram illustrating an embodiment of a configuration of a driving board for driving a plasma display panel.

6 is a circuit diagram illustrating an embodiment of a configuration of a scan driving circuit and a sustain driving circuit.

Fig. 7 is a circuit diagram showing a first embodiment of the structure of the scan / sustain driving circuit according to the present invention.

FIG. 8 is a timing diagram illustrating an embodiment of a switching operation of the driving circuit of FIG. 7.

9 is a circuit diagram showing a second embodiment of the configuration of the energy recovery circuit according to the present invention.

The present invention relates to a plasma display device, and more particularly, to a structure of a plasma display panel used in the device.

In general, a plasma display panel is a partition wall formed between an upper substrate and a lower substrate to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because a thin and light configuration is possible.

In order to drive the plasma display panel, driving for supplying a driving signal to each electrode formed in the panel is required. If a peaking current occurs due to voltage instability in the panel driving circuit, it may cause problems such as malfunction of the panel and damage to the circuit.

An object of the present invention is to provide a plasma display apparatus which is reliable by improving the stability of a panel driving circuit in a plasma display apparatus.

According to another aspect of the present invention, there is provided a plasma display apparatus including: a scan driving circuit configured to supply a driving signal to a scan electrode of a plasma display panel; A sustain driving circuit which supplies a driving signal to the sustain electrode; An inductor connected in parallel with the capacitance of the panel between the scan driving circuit and the sustain driving circuit to form a resonance circuit together with the capacitance of the panel; A first switch connected between the scan driving circuit and the inductor; And a second switch connected between the sustain driving circuit and the inductor.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a lamination of chromium / copper / chromium (Cr / Cu / Cr) or a lamination of chromium / aluminum / chromium (Cr / Al / Cr). have. The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, phosphor layers are formed on the surfaces of the lower dielectric layer 23 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), thereby eliminating discharge discharge in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a negative scan signal scan is sequentially applied to the scan electrode, and at the same time, a positive data signal data is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are exemplary embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited to the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

FIG. 5 illustrates an embodiment of a configuration of a driving board for driving a plasma display panel.

Referring to FIG. 5, the heat dissipation frame 30 is installed on the rear surface of the panel to support the panel and to absorb and release heat generated from the panel. In addition, the back surface of the heat dissipation frame 30 is provided with a printed circuit board 40 for applying driving signals to the panel.

The printed circuit board 40 includes an address driving circuit (X / BD, 50) for supplying a driving signal to an address electrode (not shown) of the panel, and a scan driving circuit for supplying a driving signal to a scan electrode (not shown) of the panel Y / BD, 60, a sustain drive circuit (Z / BD, 70) for supplying a drive signal to a sustain electrode (not shown) of the panel, a main controller (Ctrl / BD, 80) for controlling the drive circuits, and It may include a power supply unit (PSU) 90 for supplying power to the drive circuit.

The address driving circuit 50 supplies a driving signal to an address electrode (not shown) formed in the panel and selects only the discharge cells discharged among the plurality of discharge cells (not shown) formed in the panel 10.

The address driving circuit 50 may be installed on any one or both of the upper side and the lower side of the panel according to a single scan method or a dual scan method.

In the address driving circuit 50, a data IC (not shown) is installed to control a current applied to the address electrode. In the data IC, switching is generated to control a current applied thereto, and a large amount of heat may be generated. . Therefore, the heat sink 100 may be installed in the address driving circuit 50 to solve the heat generated in the control process.

As shown in FIG. 5, the scan driving circuit 60 includes a scan sustain board 62 connected to the main controller 80, and a scan driver board 64 connecting the scan sustain board 62 and the panel 10. ) May be included.

The scan driver board 64 may be installed divided into two parts of the upper and lower parts in this embodiment. Unlike the embodiment shown in FIG. 5, the scan driver board 64 may be provided in a single number or a plurality of more.

The scan driver board 64 is provided with a scan IC 65 for supplying a drive signal to the scan electrodes of the panel, and the scan IC 65 can continuously apply reset, scan and sustain signals to the scan electrodes.

The sustain drive circuit 70 supplies a drive signal to the sustain electrode of the panel.

6 is a circuit diagram showing an embodiment of the configuration of the scan driving circuit and the sustain driving circuit.

The scan driving circuit according to the present invention may include a sustain driver, a reset driver and a scan IC. Referring to FIG. 6, the sustain driver lowers the voltage applied to the Y_sus_up switch Q3 and the scan electrode to the ground voltage to apply the sustain voltage Vs to the scan electrode of the panel Cp. Y-sus_down switch Q4 which is turned on.

The reset driver is connected to the set-up switch (Q8) and the negative voltage (-Vy), which are turned on to supply a gradually rising set-up signal to the scan electrode, and then gradually decreases to the negative voltage (-Vy). The set_down switch Q9 is turned on to supply a scan electrode to the scan electrode, and a pass switch Q6 forming a current path path with the scan electrode.

The scan IC is connected to the scan voltage source Vsc and the scan_up switch Q10 is turned on to apply the scan voltage Vsc to the scan electrode, and the scan_down switch Q11 is turned on to apply the ground voltage to the scan electrode. ).

The sustain driving circuit is turned on to apply the sustain voltage Vs to the sustain electrode of the panel Cp and the Z_up switch Q1 and Z_ turned on to lower the voltage supplied to the sustain electrode to the ground voltage. It is configured to include a sus_down switch Q2.

As shown in FIG. 6, the inductor L is connected between the sustain driving circuit and the scan driving circuit, and the inductor L supplies or removes the sustain voltage Vs to the scan electrode or the sustain electrode of the panel. The capacitance Cp and the resonance circuit of the panel are formed.

In addition, an ER switch Q5 is connected between the inductor and the sustain driving circuit, and a diode is connected between the sustain voltage source Vs and one end of the inductor. As shown in FIG. 6, the diode has a cathode terminal connected to the sustain voltage source Vs and an anode terminal connected to the contact between the ER switch Q5 and the inductor L. As shown in FIG. .

FIG. 7 is a circuit diagram showing a first embodiment of the configuration of the scan / sustain driving circuit according to the present invention, and shows only a driving circuit for supplying a sustain voltage to the scan electrode and the sustain electrode of the panel Cp. .

Referring to FIG. 7, the scan / sustain driving circuit includes a Y_sus_up switch turned on to apply the sustain voltage Vs to the scan electrode of the panel Cp, and Y_sus_dn turned on to lower the voltage applied to the scan electrode to the ground voltage. And a Z_sus_up switch which is turned on to apply the sustain voltage Vs to the sustain electrode of the panel Cp, and a Z_sus_dn switch which is turned on to lower the voltage supplied to the sustain electrode to the ground voltage.

As shown in FIG. 7, the scan / sustain driving circuit according to the present invention includes an inductor L and an ER switch connected in parallel with the panel Cp, and the contact and the sustain voltage source Vs of the inductor L and the ER switch. ) Includes a diode (D1) connected between.

FIG. 8 is a timing diagram illustrating an embodiment of the switching operation of the driving circuit illustrated in FIG. 7, and illustrates an embodiment of the switching operation in the sustain period.

Referring to FIG. 8, the Y_sus_up switch, the Y_sus_dn switch, the Z_sus_up switch, and the Z_sus_dn switch are turned on or off in accordance with the sustain pulse supply to the scan electrode and the sustain electrode. In addition, the ER switch is turned on during the sustain period.

In the driving circuit shown in FIG. 7, a body diode of the ER switch even if the ER switch is turned off when a high level voltage, for example, the sustain voltage Vs is supplied to the sustain electrode Z continuously. The current flows through) and the value of I _L becomes very large. That is, when the voltage supplied to the sustain electrode maintains a high voltage level for a long time, an overcurrent flows through the second current path where the inductor is formed, and thus the output voltage may become unstable.

For example, when a sustain voltage is supplied to the sustain electrode due to the z-bias voltage applied to the sustain electrode, overcurrent flows through the second current path in which the inductor is formed, and thus the driving signal of the address period may become unstable.

FIG. 9 is a circuit diagram illustrating a second embodiment of the configuration of the energy recovery circuit according to the present invention. In order to prevent the formation of overcurrent as described above, switches ER1 and ER2 having body diodes in different directions. Are connected to both ends of the inductor (L).

9, an ER1 switch is connected between one end of an inductor L and a scan driving circuit, and an ER2 switch is connected between the other end of the inductor L and a sustain driving circuit.

The ER1 switch and the ER2 switch are turned on only in the sustain period, and remain turned off in the other periods.

Both the body diode of the ER1 switch and the body diode of the ER2 switch have a cathode end connected to the inductor L and to the switch in opposite directions, so that no current can flow through the two body diodes. Except for the sustain period in which the ER2 switch is turned on, current cannot flow through the second current path in which the inductor L is formed.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

According to the plasma display device according to the present invention configured as described above, by configuring a scan and sustain drive energy recovery circuit using one inductor, it is possible to improve the panel drive efficiency, and to stabilize the output voltage of the drive circuit. Discharge can be prevented.

Claims (6)

Upper substrate; A plurality of scan electrodes and sustain electrodes formed on the upper substrate; A lower substrate disposed to face the upper substrate; And a plasma display panel including a plurality of address electrodes formed on the lower substrate. A scan driving circuit which supplies a driving signal to the scan electrode; A sustain driving circuit for supplying a driving signal to the sustain electrode; An inductor connected in parallel with the capacitance of the panel between the scan driving circuit and the sustain driving circuit to form a resonance circuit together with the capacitance of the panel; A first switch connected between the scan driving circuit and the inductor; And And a second switch connected between the sustain driving circuit and the inductor. The method of claim 1, wherein the first and second switches The plasma display device is turned on only in the sustain period. The method of claim 1, And a body diode of the first switch and a body diode of the second switch are connected in opposite directions. The method of claim 1, wherein the body diode of the first switch And an anode terminal is connected to the scan driving circuit and a cathode terminal is connected to the inductor. The method of claim 1, wherein the body diode of the first switch And an anode terminal is connected to the sustain driving circuit, and a cathode terminal is connected to the inductor. The method of claim 1, And a diode having a cathode terminal connected to the sustain voltage source and an anode terminal connected to the contact point of the inductor and the second switch.

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