KR20100123233A - Differential amplifier and circuit for receiving data of semiconductor memory apparatus using the same - Google Patents

Differential amplifier and circuit for receiving data of semiconductor memory apparatus using the same Download PDF

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Publication number
KR20100123233A
KR20100123233A KR1020090042340A KR20090042340A KR20100123233A KR 20100123233 A KR20100123233 A KR 20100123233A KR 1020090042340 A KR1020090042340 A KR 1020090042340A KR 20090042340 A KR20090042340 A KR 20090042340A KR 20100123233 A KR20100123233 A KR 20100123233A
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KR
South Korea
Prior art keywords
voltage
data
external
reference voltage
level
Prior art date
Application number
KR1020090042340A
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Korean (ko)
Inventor
강신덕
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090042340A priority Critical patent/KR20100123233A/en
Publication of KR20100123233A publication Critical patent/KR20100123233A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit

Abstract

The present invention operates by receiving a driving voltage, the differential amplifier for generating an output signal in accordance with the voltage difference between the input signal and the reference voltage, and controls the level of the driving voltage and the reference voltage in accordance with the potential level of the input signal And a voltage controller for maintaining a constant voltage difference between the driving voltage and the reference voltage.

Description

Differential Amplifier and Circuit for Receiving Data of Semiconductor Memory Apparatus using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a data receiving circuit using a differential amplifier circuit.

As shown in FIG. 1, a data receiving circuit of a semiconductor memory device according to the related art receives a reference voltage Vref and external data data_ext from an external data transmission circuit 10.

The data receiving circuit 20 provided in the semiconductor memory device receives the reference voltage Vref and the external data data_ext and outputs internal data data_int.

In general, the data receiving circuit 20 determines the value of the external data data_ext based on the voltage level of the reference voltage Vref and generates the internal data data_int.

When the noise component is increased in any one of the external voltage VDD applied to drive the semiconductor memory device, the reference voltage Vref applied to determine the external data data_ext, and the external data data_ext, the internal data is increased. The jitter component increases in (data_int), which is a problem that reduces the reliability of the data.

Disclosure of Invention The present invention has been made to solve the above-described problem, and provides a differential amplifier circuit capable of reducing the jitter component of an output signal and a data receiving circuit of a semiconductor memory device capable of reducing the jitter component of internal data using the same. For that purpose.

A differential amplifier circuit of a semiconductor memory device according to an embodiment of the present invention operates by applying a driving voltage, and generates a differential amplifier according to a voltage difference between an input signal and a reference voltage, and a potential level of the input signal. And a voltage controller configured to control the levels of the driving voltage and the reference voltage to maintain a constant voltage difference between the driving voltage and the reference voltage.

A data receiving circuit of a semiconductor memory device using a differential amplifier circuit according to the present invention includes a differential amplifier which receives an external voltage, a reference voltage, and external data to generate internal data, and the external voltage according to a potential level of the external data. And a voltage controller configured to control the reference voltage level to maintain a constant voltage level difference between the external voltage and the reference voltage.

The differential amplifier circuit according to the present invention has the effect of reducing the jitter component of the output signal generated by determining the input signal based on the reference voltage. The data receiving circuit of the semiconductor memory device using the differential amplifier circuit of the present invention can reduce the jitter component of the internal data generated by determining external data based on the reference voltage, thereby increasing the data reliability of the semiconductor memory device.

As illustrated in FIG. 2, the data receiving circuit 100 of the semiconductor memory device according to an exemplary embodiment of the present invention includes a differential amplifier 110 and first and second voltage controllers 120 and 130.

The differential amplifier 110 receives the reference voltage Vref and the external voltage VDD and receives the external data data_ext to generate the internal data data_int.

For example, the differential amplifier 110 receives the external voltage VDD as a driving voltage, determines the value of the external data data_ext based on the reference voltage Vref, and determines the internal data data_int. ) In this case, the reference voltage Vref and the external data data_ext are provided by a data transmission circuit 10 external to the semiconductor memory device.

The first voltage controller 120 maintains a constant voltage level difference between the external voltage VDD and the reference voltage Vref.

For example, when the voltage level of any one of the external voltage VDD and the reference voltage Vref is increased or decreased due to noise, the other voltage is also controlled to be raised or lowered.

The second voltage controller 130 controls the external voltage VDD level according to the potential level of the external data data_ext.

For example, when the potential level of the external data data_ext is high, the level of the external voltage VDD is increased. When the potential level of the external data data_ext is low, the external voltage VDD level is decreased.

As shown in FIG. 3, the differential amplifier 110 includes first to fifth transistors P11, P12, and N11 to N13.

The first transistor P11 receives an external voltage VDD from a source. The second transistor P12 receives an external voltage VDD from a source. In this case, the gate, the drain, and the gate of the second transistor P12 of the first transistor P11 are commonly connected to one node. The third transistor N11 receives a reference voltage Vref at a gate thereof and is connected to a node to which the first and second transistors P11 and P12 are connected to a drain thereof. A source of the second transistor P12 is connected to a drain of the fourth transistor N12 and an external data data_ext is input to a gate. The fifth transistor N13 receives a bias voltage at a gate thereof, a node connected to a source of the third and fourth transistors N11 and N12 is connected to a drain, and a ground terminal VSS is connected to the source. Connected.

The internal data data_int is output at a node to which the drain of the second transistor P12 and the fourth transistor N12 is connected.

As shown in FIG. 3, the first voltage controller 120 includes a capacitor C11.

The capacitor C11 is connected between a terminal to which the external voltage VDD is applied and a terminal to which the reference voltage Vref is applied.

As illustrated in FIG. 3, the second voltage controller 130 includes a resistor R11.

The resistance element R11 is connected between a terminal receiving an external voltage VDD and a terminal receiving the external data data_ext.

The operation of the data receiving circuit 100 of the semiconductor memory device according to the embodiment configured as described above is as follows.

The external data data_ext and the reference voltage Vref are output from the data transmission circuit 10 outside the semiconductor memory device.

As illustrated in FIG. 3, the differential amplifier 110 generates the internal data data_int by a voltage difference between the external data data_ext and the reference voltage Vref.

If the potential level of the external data data_ext input to the differential amplifier 110 is higher than the potential level set due to noise, it is assumed.

The second voltage controller 130 increases the external voltage VDD level as the external data data_ext becomes higher than the set potential level.

The first voltage controller 120 increases the level of the reference voltage Vref as the level of the external voltage VDD increases.

When the level of the reference voltage Vref is increased, the turn on degree of the third transistor N11 is increased, thereby increasing the turn on degree of the second transistor P12.

When the potential level of the external data data_ext is higher than the set potential level, the turn-on degree of the fourth transistor N12 is increased, and the fourth transistor N12 flows a larger amount of current. However, when the potential level of the external data data_ext is higher than the set potential level, the turn-on degree of the second transistor P12 is increased, so that the second transistor P12 is larger in the fourth transistor N12. By supplying current, the internal data data_int maintains the normal transition rate.

It is assumed that a potential level of the external data data_ext input to the differential amplifier 110 is lower than a potential level set due to noise.

The second voltage controller 130 lowers the external voltage VDD level as the external data data_ext is lower than the set potential level.

The first voltage controller 120 lowers the level of the reference voltage Vref as the external voltage VDD is lowered.

When the level of the reference voltage Vref is lowered, the degree of turn-on of the third transistor N11 is reduced, and as a result, the degree of turn-on of the second transistor P12 is also reduced.

When the potential level of the external data data_ext is lower than the set potential level, the turn-on degree of the fourth transistor N12 is reduced, so that the fourth transistor N12 flows a smaller amount of current. However, when the potential level of the external data data_ext is lower than the set potential level, the turn-on degree of the second transistor P12 is reduced, so that the second transistor P12 is smaller in the fourth transistor N12. By supplying the current of the internal data (data_int) maintains the normal transition speed.

The data receiving circuit of the semiconductor memory device according to the present invention includes a differential amplifier configured to generate external data by determining external data as a reference voltage, and a voltage controller configured to maintain a constant level difference between a driving voltage and the reference voltage of the differential amplifier. In addition, the jitter component of the internal data is reduced by maintaining the voltage level and the level transition slope of the internal data at a set value, thereby improving data reliability of the semiconductor memory device.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a configuration diagram of a general semiconductor memory device;

2 is a configuration of a semiconductor memory device according to an embodiment of the present invention;

FIG. 3 is a detailed configuration diagram of the semiconductor memory device shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: data transmission circuit 100: data receiving circuit

110: differential amplifier 120, 130: first and second voltage controller

Claims (10)

A differential amplifier configured to operate by receiving a driving voltage and generate an output signal according to a voltage difference between an input signal and a reference voltage; And And a voltage controller configured to control the level of the driving voltage and the reference voltage according to the potential level of the input signal to maintain a constant voltage difference between the driving voltage and the reference voltage. Circuit. The method of claim 1, The voltage controller The driving voltage and the reference voltage level are increased when the potential level of the input signal is increased, and the reference voltage and the driving voltage level are decreased when the potential level of the input signal is decreased. . The method of claim 2, The voltage controller And a capacitor connected between the terminal receiving the driving voltage and the terminal receiving the reference voltage. The method of claim 3, wherein The voltage controller And a resistance element connected between the terminal receiving the input signal and the terminal receiving the driving voltage. A differential amplifier configured to receive an external voltage, a reference voltage, and external data to generate internal data; And And a voltage controller configured to control the external voltage and the reference voltage level according to a potential level of the external data to maintain a constant voltage level difference between the external voltage and the reference voltage. The method of claim 5, The voltage controller And controlling one of the external voltage and the reference voltage to increase or decrease the other voltage level in proportion to the increase or decrease of the voltage level. The method of claim 6, The voltage controller And controlling the external voltage and the reference voltage to be electrically separated from each other. The method of claim 7, wherein The voltage controller A capacitor, a resistance element, The capacitor is configured to receive the external voltage and the reference voltage at both ends, The resistance element is a semiconductor memory device, characterized in that configured to receive the external voltage and the external data at both ends. The method of claim 5, The differential amplifier is The external voltage is applied as a driving voltage, And determine the value of the external data based on the reference voltage to generate the internal data. The method of claim 7, wherein The reference voltage and the external data A semiconductor memory device, characterized in that it is provided outside the semiconductor memory device.
KR1020090042340A 2009-05-15 2009-05-15 Differential amplifier and circuit for receiving data of semiconductor memory apparatus using the same KR20100123233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090042340A KR20100123233A (en) 2009-05-15 2009-05-15 Differential amplifier and circuit for receiving data of semiconductor memory apparatus using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090042340A KR20100123233A (en) 2009-05-15 2009-05-15 Differential amplifier and circuit for receiving data of semiconductor memory apparatus using the same

Publications (1)

Publication Number Publication Date
KR20100123233A true KR20100123233A (en) 2010-11-24

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