TW202243392A

TW202243392A - Amplifier and lpddr3 input buffer

Info

Publication number: TW202243392A
Application number: TW110115245A
Authority: TW
Inventors: 粘書瀚
Original assignee: 晶豪科技股份有限公司
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2022-11-01
Also published as: TWI781598B

Abstract

An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

Description

amplifier and LPDDR3 input buffer

本發明有關於放大器以及LPDDR3輸入緩衝器，特別有關於可降低參考電壓的變動所造成影響的放大器以及LPDDR3輸入緩衝器。The present invention relates to amplifiers and LPDDR3 input buffers, in particular to amplifiers and LPDDR3 input buffers capable of reducing the impact of reference voltage fluctuations.

低功耗DDR (雙倍資料率同步動態隨機存取記憶，Double Data Rate Synchronous Dynamic Random Access Memory)中的LPDDR3的輸入緩衝器會接收一參考電壓，而輸入緩衝器會根據此參考電壓產生輸出電壓給之後的電路使用。然而，輸出電壓可能會對應參考電壓的變動而漂動。The input buffer of LPDDR3 in low-power DDR (Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate Synchronous Dynamic Random Access Memory) will receive a reference voltage, and the input buffer will generate an output voltage based on this reference voltage for subsequent circuits. However, the output voltage may fluctuate corresponding to the variation of the reference voltage.

因此，需要一種補償機制來改善這樣的問題。Therefore, a compensation mechanism is needed to improve such problems.

因此，本發明一目的為提供一種放大器，其可補償由參考電壓的變動所引起的輸出電壓漂移。Therefore, an object of the present invention is to provide an amplifier capable of compensating the output voltage drift caused by the variation of the reference voltage.

本發明另一目的為提供一種LPDDR3輸入緩衝器，其可補償由參考電壓的變動所引起的輸出電壓漂移。Another object of the present invention is to provide an LPDDR3 input buffer which can compensate the output voltage drift caused by the variation of the reference voltage.

本發明一實施例揭露了一種放大器，具有一輸入級，該輸入級包含：一第一電流鏡，耦接一預定電壓源；一第一輸入差動對，耦接該第一電流鏡；一第一電流源，耦接該第一輸入差動對；一第二電流源；一第二輸入差動對，耦接該第二電流鏡，其中該第一輸入差動對以及該第二輸入差動對用以接收一參考電壓；一第二電流鏡，耦接該第二輸入差動對以及一地電位；以及一壓控傳輸電路，被一參考電壓控制。其中當預定電壓高於一第一預定值，該第一電流鏡中形成一額外電流路徑且流過該第一電流鏡中的該額外電流路徑的電流流經該第二電流鏡到該地電位。其中當該預定電壓低於一第二預定值，該第二電流鏡中形成一額外電流路徑且流過該第二電流鏡中的該額外電流路徑的電流流經該第一電流鏡到該預定電壓源。An embodiment of the present invention discloses an amplifier, which has an input stage, and the input stage includes: a first current mirror coupled to a predetermined voltage source; a first input differential pair coupled to the first current mirror; a A first current source, coupled to the first input differential pair; a second current source; a second input differential pair, coupled to the second current mirror, wherein the first input differential pair and the second input The differential pair is used to receive a reference voltage; a second current mirror is coupled to the second input differential pair and a ground potential; and a voltage-controlled transmission circuit is controlled by a reference voltage. Wherein when the predetermined voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground potential . Wherein when the predetermined voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined power source.

在一實施例中，前述放大器使用在LPDDR3緩衝器且參考電壓對應ODT（on die termination，片內終結）電阻而變動。In one embodiment, the aforementioned amplifier is used in an LPDDR3 buffer and the reference voltage varies corresponding to an ODT (on die termination, on-chip termination) resistor.

根據上述實施例，可以補償由參考電壓的變動所引起的放大器的輸出電壓的漂移。因此，可以改善現有技術中的問題。According to the above-described embodiments, the drift of the output voltage of the amplifier caused by the variation of the reference voltage can be compensated. Therefore, problems in the prior art can be improved.

以下描述中以多個實施例做為例子來說明本發明的概念。還請留意，以下描述中的”第一”、”第二”以及類似描述僅用來定義不同的元件、參數、資料、訊號或步驟。並非用以限定其次序。舉例來說，第一裝置以及第二裝置僅代表這些裝置可具有相同的結構但為不同的裝置。In the following description, several embodiments are taken as examples to illustrate the concepts of the present invention. Please also note that "first", "second" and similar descriptions in the following descriptions are only used to define different elements, parameters, data, signals or steps. It is not intended to limit the order. For example, the first device and the second device only represent that these devices may have the same structure but are different devices.

第1圖為繪示了根據本發明一實施例的放大器的方塊圖，這放大器包含了具寬輸入範圍的輸入級。運算放大器通常可以分為輸入級100和輸出級（未示出）。如第1圖所示，輸入級100包含：耦接到預定電壓源VDD的第一電流鏡CM1，第一輸入差動對DI1，第一電流源CS1，耦接到地電位的第二電流鏡CM2，第二輸入差動對DI2，第二電流源CS2以及壓控傳輸電路101。第一輸入差動對DI1耦接到第一電流鏡CM1，且第一電流源CS1耦接到第一輸入差動對DI1。第二輸入差動對DI2耦接到第二電流鏡CM2，且第二電流源CS2耦接到第二輸入差動對DI2。第一輸入差動對DI1和第二輸入差動對DI2用以接收輸入信號IN和參考電壓REF。壓控傳輸電路101由參考電壓REF控制。FIG. 1 is a block diagram illustrating an amplifier including an input stage with a wide input range according to an embodiment of the present invention. An operational amplifier can generally be divided into an input stage 100 and an output stage (not shown). As shown in FIG. 1, the input stage 100 includes: a first current mirror CM1 coupled to a predetermined voltage source VDD, a first input differential pair DI1, a first current source CS1, and a second current mirror coupled to ground potential CM2 , a second input differential pair DI2 , a second current source CS2 and a voltage-controlled transmission circuit 101 . The first input differential pair DI1 is coupled to the first current mirror CM1 , and the first current source CS1 is coupled to the first input differential pair DI1 . The second input differential pair DI2 is coupled to the second current mirror CM2, and the second current source CS2 is coupled to the second input differential pair DI2. The first differential input pair DI1 and the second differential input pair DI2 are used for receiving the input signal IN and the reference voltage REF. The voltage-controlled transmission circuit 101 is controlled by a reference voltage REF.

在實施運作中，當參考電壓REF高於第一預定值時，在第一電流鏡CM1中會形成額外電流路徑，且流過此額外電流路徑的電流會通過第二電流鏡CM2流向地電位。另外，當參考電壓REF低於第二預定值時，在第二電流鏡CM2中會形成額外的電流路徑，且流過第二電流鏡CM2中的額外電流路徑的電流會通過第一電流鏡CM1並流到預定電壓源VDD。In operation, when the reference voltage REF is higher than the first predetermined value, an additional current path is formed in the first current mirror CM1 , and the current flowing through the additional current path flows to the ground potential through the second current mirror CM2 . In addition, when the reference voltage REF is lower than the second predetermined value, an additional current path will be formed in the second current mirror CM2, and the current flowing through the additional current path in the second current mirror CM2 will pass through the first current mirror CM1 And flow to the predetermined voltage source VDD.

於一實施例中，額外電流路徑是指第一電流鏡CM1以及第二電流鏡CM2原先已具有電流路徑。但當參考電壓REF高於第一預定值或低於第二預定值時，會在第一電流鏡CM1或第二電流鏡CM2中再形成電流路徑。In one embodiment, the additional current path means that the first current mirror CM1 and the second current mirror CM2 already have current paths. But when the reference voltage REF is higher than the first predetermined value or lower than the second predetermined value, a current path will be formed again in the first current mirror CM1 or the second current mirror CM2 .

在一實施例中，第一預定值和第二預定值是壓控傳輸電路101中的電晶體的開啟/關閉電壓。稍後將更詳細描述壓控傳輸電路101的細節。In one embodiment, the first predetermined value and the second predetermined value are on/off voltages of transistors in the voltage-controlled transmission circuit 101 . Details of the voltage-controlled transmission circuit 101 will be described in more detail later.

在一實施例中，輸入級100包含在LPDDR3輸入緩衝器中。在這種情況下，參考電壓REF是DQ，DM輸入的參考電壓，其電壓位準隨ODT（on die termination，片內終結）電阻而變化。 ODT電阻可以遵循LPDDR3規範並以不同的模式運行，且在不同的模式中具有不同的電阻值。參考電壓REF對應於ODT電阻的不同電阻值而變化。如上所述，參考電壓REF的變化可能導致輸出電壓Vo的漂移。在一實施例中，輸出電壓Vo也被作為反相器（未示出）的輸入，因此輸出電壓Vo的漂移會影響反相器的輸出。經由第1圖所示的輸入級100，可以補償輸出電壓Vo以改善上述問題。In one embodiment, the input stage 100 is included in an LPDDR3 input buffer. In this case, the reference voltage REF is the reference voltage input by DQ and DM, and its voltage level varies with the ODT (on die termination, on-chip termination) resistance. ODT resistors can follow the LPDDR3 specification and operate in different modes, and have different resistance values in different modes. The reference voltage REF varies corresponding to different resistance values of the ODT resistor. As mentioned above, the variation of the reference voltage REF may cause the output voltage Vo to drift. In one embodiment, the output voltage Vo is also used as the input of an inverter (not shown), so the drift of the output voltage Vo will affect the output of the inverter. Through the input stage 100 shown in FIG. 1, the output voltage Vo can be compensated to improve the above problems.

第2圖為繪示了根據本發明一實施例的第1圖中的放大器100的電路圖。請注意，第2圖僅為範例，能夠執行相同功能的電路也應落入本發明的範圍內。如第2圖所示，第一電流鏡CM1包含PMOS MPa，MPb，第二電流鏡CM2包含NMOS MNc，MNd。運算放大器包含具有寬輸入範圍的輸入級100，其包含具有NNOS MNa和MNb的差動電晶體對以及包含具有PMOS MPc和MPd形成的差動電晶體對組成。這些差動電晶體對並聯連接以接收並聯傳輸的輸入信號IN和REF。FIG. 2 is a circuit diagram illustrating the amplifier 100 in FIG. 1 according to an embodiment of the present invention. Please note that Figure 2 is just an example, and circuits capable of performing the same function should also fall within the scope of the present invention. As shown in FIG. 2, the first current mirror CM1 includes PMOS MPa, MPb, and the second current mirror CM2 includes NMOS MNc, MNd. The operational amplifier includes an input stage 100 with a wide input range, which includes a differential transistor pair formed with NNOS MNa and MNb and a differential transistor pair formed with PMOS MPc and MPd. These differential transistor pairs are connected in parallel to receive input signals IN and REF transmitted in parallel.

在第2圖的實施例中，PMOS MPa，MPb的閘極耦接至第1圖所示的壓控傳輸電路101的端點Tl，且NMOS MNc，MNd的閘極耦接至壓控傳輸電路101的端點T2。PMOSMPa，MPb，NMOS MNc，MNd可以用其他種類的電晶體代替。因此，這樣的連接可以描述為：第一電流鏡CM1包含多個電晶體，且壓控傳輸電路101耦接到電晶體的控制端（例如，閘極端）。此外，這樣的連接可以描述為：第二電流鏡CM2包含多個電晶體，並且壓控傳輸電路101耦接到電晶體的控制端點。In the embodiment of FIG. 2, the gates of PMOS MPa, MPb are coupled to the terminal T1 of the voltage-controlled transmission circuit 101 shown in FIG. 1, and the gates of NMOS MNc, MNd are coupled to the voltage-controlled transmission circuit. 101's endpoint T2. PMOSMPa, MPb, NMOS MNc, MNd can be replaced by other types of transistors. Therefore, such a connection can be described as: the first current mirror CM1 includes a plurality of transistors, and the voltage-controlled transmission circuit 101 is coupled to the control terminal (eg, the gate terminal) of the transistors. In addition, such connection can be described as: the second current mirror CM2 includes a plurality of transistors, and the voltage-controlled transmission circuit 101 is coupled to the control terminals of the transistors.

壓控傳輸電路101用以控制端點T1，T2之間的短路程度，且可具有各種不同結構。第3圖和第5圖是根據本發明不同實施例的第1圖所示的壓控傳輸電路的電路圖。第3圖是壓控傳輸電路101的電路圖，當參考電壓REF在VDD / 2和VDD之間時，壓控傳輸電路101形成傳輸路徑，此傳輸路徑用作上述的額外電流路徑，以降低輸出電壓Vo。如第3圖所示，壓控傳輸電路101包含PMOS P1，NMOS N1和NMOS N2。 NMOS N1由參考電壓REF控制而開啟 (導通)或關閉(不導通)。具體來說，當參考電壓REF高於第一預定值時，NMOS N1開啟。The voltage-controlled transmission circuit 101 is used to control the degree of short-circuit between the terminals T1, T2, and may have various structures. 3 and 5 are circuit diagrams of the voltage-controlled transmission circuit shown in FIG. 1 according to different embodiments of the present invention. Figure 3 is a circuit diagram of the voltage-controlled transmission circuit 101. When the reference voltage REF is between VDD/2 and VDD, the voltage-controlled transmission circuit 101 forms a transmission path, and this transmission path is used as the above-mentioned additional current path to reduce the output voltage Vo. As shown in FIG. 3 , the voltage-controlled transmission circuit 101 includes PMOS P1 , NMOS N1 and NMOS N2 . The NMOS N1 is turned on (conducting) or off (non-conducting) controlled by the reference voltage REF. Specifically, when the reference voltage REF is higher than a first predetermined value, the NMOS N1 is turned on.

PMOS P1耦接在第一電流鏡CM_1和NMOS N1之間，且耦接到地電位。具體來說，PMOS P1的源極端作為第1圖所示的端點T1，且PMOS P1的閘極耦接到地電位。 NMOS N2耦接於NMOS N1和第二電流鏡CM2之間且被第一偏壓電壓B1所偏壓。另外，在第3圖的實施例中，NMOS N2的源極用作第1圖所示的端點T2。The PMOS P1 is coupled between the first current mirror CM_1 and the NMOS N1, and is coupled to the ground potential. Specifically, the source terminal of the PMOS P1 serves as the terminal T1 shown in FIG. 1 , and the gate of the PMOS P1 is coupled to the ground potential. The NMOS N2 is coupled between the NMOS N1 and the second current mirror CM2 and is biased by the first bias voltage B1. In addition, in the embodiment of FIG. 3, the source of the NMOS N2 is used as the terminal T2 shown in FIG. 1.

在一實施例中，於實際操作中，當參考電壓REF增加到0.5 * VDD和VDD之間時，第一偏壓電壓B1降低到較低的電壓，例如0.75 * VDD，以減少端點T1，T2之間的短路程度。更詳細來說，由於較低的第一偏壓電壓B1，NMOS N2的導通電阻增加，且端點T1，T2之間的短路程度相應地受到限制。在這樣的設計中，如果參考電壓REF增加到0.5 * VDD至0.75 * VDD之間，則端點T1，T2之間的短路程度由參考電壓REF控制。另外，如果參考電壓REF進一步增加到0.75 * VDD與VDD之間，則端點T1，T2之間的短路程度被0.75 * VDD的第一偏壓電壓B1箝位。In one embodiment, in actual operation, when the reference voltage REF increases between 0.5*VDD and VDD, the first bias voltage B1 is reduced to a lower voltage, such as 0.75*VDD, to reduce the terminal T1, The degree of short circuit between T2. In more detail, due to the lower first bias voltage B1, the on-resistance of the NMOS N2 increases, and the degree of the short circuit between the terminals T1, T2 is correspondingly limited. In such a design, if the reference voltage REF increases to between 0.5*VDD and 0.75*VDD, the degree of short circuit between the terminals T1, T2 is controlled by the reference voltage REF. In addition, if the reference voltage REF is further increased to between 0.75*VDD and VDD, the short circuit between the terminals T1 and T2 is clamped by the first bias voltage B1 of 0.75*VDD.

此外，為了避免製程漂移的影響，壓控傳輸電路101可包含PMOS P1，以在NMOS開啟過多且PMOS開啟得太少而使端點T1，T2短路時補償端點T1，T2的短路。In addition, in order to avoid the influence of process drift, the voltage control transmission circuit 101 may include a PMOS P1 to compensate for the short circuit of the terminals T1 and T2 when the NMOS is turned on too much and the PMOS is turned on too little so that the terminals T1 and T2 are shorted.

PMOS P1，NMOS N1和NMOS N2可以由其他種類的電晶體代替。因此，第3圖所示的實施例可以描述為包含：一第一類一電晶體（例如，NMOS N1），由參考電壓REF控制以開啟或關閉，其中，當參考電壓REF高於第一預定值時，第一類電晶體導通。並包含一第一類二電晶體（例如，PMOS P1），耦接在第一電流鏡CM1和第一類一電晶體之間，且耦接到地電位。且可進一步包含一第二類一電晶體（NMOS N2）。此第二類一電晶體被第一偏壓電壓B1偏壓，並耦接在第一類一電晶體和第二電流鏡CM2之間。PMOS P1, NMOS N1 and NMOS N2 can be replaced by other types of transistors. Therefore, the embodiment shown in FIG. 3 can be described as comprising: a transistor of a first type (for example, NMOS N1 ), controlled to be turned on or off by a reference voltage REF, wherein, when the reference voltage REF is higher than a first predetermined value, the first type of transistor conducts. It also includes a first type 2 transistor (for example, PMOS P1 ), coupled between the first current mirror CM1 and the first type 1 transistor, and coupled to the ground potential. And may further include a second type-one transistor (NMOS N2). The second type-1 transistor is biased by the first bias voltage B1, and is coupled between the first type-1 transistor and the second current mirror CM2.

第4圖繪示了根據本發明一實施例的第2圖中的放大器100的動作的波形圖，其對應於第3圖中繪示的實施例。 GN是第2圖中的NMOS MNa，MNb的源極上的電壓，V_T1是端點T1上的電壓，Cur是流過NMOS MNa，MNb的電流，且Vo是前述的輸出電壓Vo。此外，上波形是當壓控傳輸電路101不形成傳輸路徑（即，端點T1和T2不導通）時的波形。例如，第3圖中的NMOS N1或第4圖中的PMOS P1關閉時的波形。相反的，下波形是當壓控傳輸電路101形成傳輸路徑時（即，端點T1和T2短路）的波形。例如，第3圖中的NMOS N1或第4圖中的PMOS P1導通時的波形。FIG. 4 shows a waveform diagram of the operation of the amplifier 100 in FIG. 2 according to an embodiment of the present invention, which corresponds to the embodiment shown in FIG. 3 . GN is the voltage on the source of the NMOS MNa, MNb in Fig. 2, V_T1 is the voltage on the terminal T1, Cur is the current flowing through the NMOS MNa, MNb, and Vo is the aforementioned output voltage Vo. In addition, the upper waveform is a waveform when the voltage-controlled transmission circuit 101 does not form a transmission path (ie, terminals T1 and T2 are not conducted). For example, the waveform when NMOS N1 in Figure 3 or PMOS P1 in Figure 4 is turned off. On the contrary, the lower waveform is a waveform when the voltage-controlled transmission circuit 101 forms a transmission path (ie, terminals T1 and T2 are short-circuited). For example, the waveform when NMOS N1 in Figure 3 or PMOS P1 in Figure 4 is turned on.

如第4圖所示，當參考電壓REF增加時，GN，V_T1，Cur上升。當參考電壓REF升高且端點T1和T2不導通時，輸出電壓Vo也升高。然而，當端點T1和T2短路時，輸出電壓Vo被下拉。根據第2圖的描述，當參考電壓高於第一預定值時，由於端點T1和T2短路，所以在第一電流鏡CM1中形成了額外電流路徑。流過第一電流鏡CM1中的額外電流路徑的電流流過第二電流鏡CM2到地電位。因此，流過PMOS MPa的電流會增加，使得PMOS MPa的電壓VSG增加。PMOS MPa的大電壓VSG抑制了NMOS MNa的電壓VDS，因此流過NMOS MNa的電流減少，且電壓GN降低。因此，輸出電壓Vo被下拉。此外，如果端點T2處的電壓增加，則輸出電壓Vo會被直接下拉。As shown in Figure 4, when the reference voltage REF increases, GN, V_T1, Cur rise. When the reference voltage REF rises and the terminals T1 and T2 are non-conductive, the output voltage Vo also rises. However, when the terminals T1 and T2 are short-circuited, the output voltage Vo is pulled down. According to the description of FIG. 2, when the reference voltage is higher than the first predetermined value, an additional current path is formed in the first current mirror CM1 due to the short circuit of the terminals T1 and T2. The current flowing through the additional current path in the first current mirror CM1 flows through the second current mirror CM2 to ground potential. Therefore, the current flowing through the PMOS MPa increases, so that the voltage VSG of the PMOS MPa increases. The large voltage VSG of the PMOS MPa suppresses the voltage VDS of the NMOS MNa, so the current flowing through the NMOS MNa decreases, and the voltage GN decreases. Therefore, the output voltage Vo is pulled down. In addition, if the voltage at the terminal T2 increases, the output voltage Vo will be directly pulled down.

與第3圖所示的實施例相反，第5圖繪示了壓控傳輸電路101在參考電壓REF介於0和VDD / 2之間時的電路圖，其形成的額外傳輸路徑增加輸出電壓Vo 。如第5圖所示，壓控傳輸電路101包含NMOS N1，PMOS P1和PMOS P2。 PMOS P1由參考電壓REF控制而開啟或關閉。具體來說，當參考電壓REF低於第二預定值時，PMOS P1開啟。Contrary to the embodiment shown in FIG. 3 , FIG. 5 shows a circuit diagram of the voltage-controlled transmission circuit 101 when the reference voltage REF is between 0 and VDD/2, and the additional transmission path formed by it increases the output voltage Vo . As shown in FIG. 5, the voltage-controlled transmission circuit 101 includes NMOS N1, PMOS P1 and PMOS P2. The PMOS P1 is turned on or off controlled by the reference voltage REF. Specifically, when the reference voltage REF is lower than a second predetermined value, the PMOS P1 is turned on.

NMOS N1耦接在第二電流鏡CM_2和PMOS P1之間，並耦接至VDD，VDD是第1圖所示的放大器100的操作電壓 (operating voltage)。具體來說，NMOS N1的源極作為第1圖所示的端點T2，且NMOS N1的閘極耦接到VDD。 PMOS P2耦接在PMOS P1和第一電流鏡CM1之間，且被第二偏壓電壓B2所偏壓。此外，在第5圖的實施例中，PMOS P2的源極作為第1圖所示的端點T1。The NMOS N1 is coupled between the second current mirror CM_2 and the PMOS P1, and is coupled to VDD, which is the operating voltage of the amplifier 100 shown in FIG. 1 . Specifically, the source of the NMOS N1 serves as the terminal T2 shown in FIG. 1 , and the gate of the NMOS N1 is coupled to VDD. The PMOS P2 is coupled between the PMOS P1 and the first current mirror CM1, and is biased by the second bias voltage B2. In addition, in the embodiment shown in FIG. 5, the source of the PMOS P2 serves as the terminal T1 shown in FIG. 1.

在一實施例中，於實際操作中，如果參考電壓REF減少到0.5 * VDD和地電位之間，則可以增加第二偏壓電壓B2以減少端點T1和T2之間的短路等級。例如，可以將第二偏壓電壓B2增加至0.25×VDD，以增加PMOS P2的開啟電阻，進而降低端點T1和T2之間的短路等級。In one embodiment, in actual operation, if the reference voltage REF is reduced to between 0.5*VDD and the ground potential, the second bias voltage B2 can be increased to reduce the short circuit level between the terminals T1 and T2. For example, the second bias voltage B2 can be increased to 0.25×VDD to increase the turn-on resistance of the PMOS P2, thereby reducing the short-circuit level between the terminals T1 and T2.

另外，為避免製程漂移的影響。壓控傳輸電路101可更包含NMOS N1，以在NMOS導通得太少和/或PMOS導通得太多的情況下補償端點T1，T2的短路等級。In addition, in order to avoid the influence of process drift. The voltage-controlled transmission circuit 101 may further include an NMOS N1 to compensate the short-circuit level of the terminals T1 and T2 when the NMOS is turned on too little and/or the PMOS is turned on too much.

NMOS N1，PMOS P1和PMOS P2可以被其他種類的電晶體代替。因此，可以將第5圖所示的實施例描述為包含：由參考電壓REF控制的第一類二電晶體（例如，PMOSP1），被參考電壓REF控制而開啟或關閉，其中當參考電壓低於第二預定值，第一類二電晶體開啟；第一類一電晶體（例如，NMOS N1），耦接在第二電流鏡CM2和第一類二電晶體之間，且耦接到預定電壓位準（例如，VDD）。第二類二電晶體P2耦接在第一類二電晶體和第一電流鏡CM1之間且被第二偏壓電壓B2所偏壓。NMOS N1, PMOS P1 and PMOS P2 can be replaced by other types of transistors. Therefore, the embodiment shown in FIG. 5 can be described as comprising: a first type two transistor (for example, PMOSP1) controlled by a reference voltage REF, which is turned on or off by a reference voltage REF, wherein when the reference voltage is lower than The second predetermined value, the first type two transistor is turned on; the first type one transistor (for example, NMOS N1), is coupled between the second current mirror CM2 and the first type two transistor, and is coupled to a predetermined voltage level (for example, VDD). The second type 2 transistor P2 is coupled between the first type 2 transistor and the first current mirror CM1 and is biased by the second bias voltage B2.

根據第2圖的描述，當參考電壓低於第二預定值時，由於端點T1和T2短路，在第二電流鏡CM2中會形成了額外電流路徑。流過第二電流鏡CM2中的額外電流路徑的電流會經過第一電流鏡CM1流到預定電壓源VDD。通過這種方式，流過NMOS MNc的電流會增加，使得NMOS MNc的電壓VGS增加。 NMOS MNc的大電壓VSG抑制了PMOS MPc的電壓VSD，因此流過PMOS MPc的電流減少，且電壓GN變得更高。因此，輸出電壓Vo被上拉。此外，如果端點T1處的電壓降低，則輸出電壓Vo被直接上拉。According to the description of FIG. 2, when the reference voltage is lower than the second predetermined value, an extra current path is formed in the second current mirror CM2 due to the short circuit between the terminals T1 and T2. The current flowing through the additional current path in the second current mirror CM2 will flow to the predetermined voltage source VDD through the first current mirror CM1. In this way, the current flowing through the NMOS MNc increases, so that the voltage VGS of the NMOS MNc increases. The large voltage VSG of the NMOS MNc suppresses the voltage VSD of the PMOS MPc, so the current flowing through the PMOS MPc decreases, and the voltage GN becomes higher. Therefore, the output voltage Vo is pulled up. Furthermore, if the voltage at the terminal T1 drops, the output voltage Vo is directly pulled up.

根據上述實施例，可以補償由參考電壓的變動所引起的放大器的輸出電壓的漂移。因此，可以改善現有技術中的問題。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 According to the above-described embodiments, the drift of the output voltage of the amplifier caused by the variation of the reference voltage can be compensated. Therefore, problems in the prior art can be improved. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:輸入級 101:壓控傳輸電路 VDD:預定電壓源 CM1:第一電流鏡 CM2:第二電流鏡 DI1:第一輸入差動對 DI2:第二輸入差動對 CS1:第一電流源 CS2:第二電流源 T1, T2:端點 MPa、MPb、P1、P2:PMOS MNa、MNb 、MNc、MNd、N1、N2:NMOS 100: Input stage 101: Voltage-controlled transmission circuit VDD: predetermined voltage source CM1: first current mirror CM2: second current mirror DI1: The first input differential pair DI2: Second input differential pair CS1: the first current source CS2: second current source T1, T2: endpoints MPa, MPb, P1, P2: PMOS MNa, MNb, MNc, MNd, N1, N2: NMOS

第1圖為繪示了根據本發明一實施例的放大器的方塊圖。第2圖為繪示了根據本發明一實施例的第1圖中的放大器的電路圖。第3圖為繪示了根據本發明一實施例的第1圖中的壓控傳輸電路的電路圖。第4圖繪示了根據本發明一實施例的第2圖中的放大器的動作的波形圖。第5圖為繪示了根據本發明另一實施例的第1圖中的壓控傳輸電路的電路圖。 FIG. 1 is a block diagram illustrating an amplifier according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the amplifier in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating the voltage-controlled transmission circuit in FIG. 1 according to an embodiment of the present invention. FIG. 4 illustrates a waveform diagram of the operation of the amplifier in FIG. 2 according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating the voltage-controlled transmission circuit in FIG. 1 according to another embodiment of the present invention.

100:輸入級 100: Input stage

VDD:預定電壓源 VDD: predetermined voltage source

CM1:第一電流鏡 CM1: first current mirror

CM2:第二電流鏡 CM2: second current mirror

DI1:第一輸入差動對 DI1: The first input differential pair

DI2:第二輸入差動對 DI2: Second input differential pair

CS1:第一電流源 CS1: the first current source

CS2:第二電流源 CS2: second current source

101:壓控傳輸電路 101: Voltage-controlled transmission circuit

T1,T2:端點 T1, T2: endpoints

Claims

An amplifier having an input stage comprising: a first current mirror coupled to a predetermined voltage source; a first input differential pair coupled to the first current mirror; a first current source coupled to the first input differential pair; a second current source; a second input differential pair coupled to the second current mirror, wherein the first input differential pair and the second input differential pair are used to receive a reference voltage; a second current mirror coupled to the second input differential pair and a ground potential; and a voltage-controlled transmission circuit controlled by a reference voltage; Wherein when the predetermined voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground Potential; Wherein when the predetermined voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined power source.

The amplifier according to claim 1, wherein the voltage-controlled transmission circuit comprises: A first type-transistor is turned on or off controlled by the reference voltage, wherein when the predetermined voltage is higher than the first predetermined value, the first type-transistor is turned on.

The amplifier as claimed in item 2, wherein the voltage-controlled transmission circuit further includes: A first type two transistor is coupled between the first current mirror and the first type one transistor, and is coupled to the ground potential.

The amplifier as claimed in claim 3, wherein the first current mirror includes a plurality of transistors and the first type two transistors are coupled to control terminals of the transistors.

The amplifier as described in Claim 3, further comprising: A second type-1 transistor, biased by a first bias voltage, is coupled between the first type-1 transistor and the second current mirror.

The amplifier according to claim 1, wherein the voltage-controlled transmission circuit comprises: A first type two transistor is turned on or off controlled by the reference voltage, wherein when the predetermined voltage is lower than the second predetermined value, the first type two transistor is turned on.

The amplifier as claimed in item 6, wherein the voltage-controlled transmission circuit further comprises: A first type-1 transistor is coupled between the second current mirror and the first type-2 transistor, and is coupled to the predetermined voltage source.

The amplifier as claimed in claim 6, wherein the first current mirror includes a plurality of transistors and the transistor of the first type is coupled to control terminals of the transistors.

The amplifier as described in Claim 6, further comprising: A second type 2 transistor, biased by a second bias voltage, is coupled between the first type 2 transistor and the first current mirror.

An LPDDR3 input buffer comprising: An amplifier having an input stage comprising: a first current mirror coupled to a predetermined voltage source; a first input differential pair coupled to the first current mirror; a first current source coupled to the first input differential pair; a second current source; a second input differential pair coupled to the second current mirror, wherein the first input differential pair and the second input differential pair are used to receive a reference voltage; a second current mirror coupled to the second input differential pair and a ground potential; and a voltage-controlled transmission circuit controlled by a reference voltage; Wherein when the predetermined voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground Potential; Wherein when the predetermined voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined power source.

The LPDDR3 input buffer as described in claim item 10, wherein the voltage-controlled transmission circuit includes: A first type-transistor is turned on or off controlled by the reference voltage, wherein when the predetermined voltage is higher than the first predetermined value, the first type-transistor is turned on.

The LPDDR3 input buffer as described in claim item 11, wherein the voltage-controlled transmission circuit further includes: A first type two transistor is coupled between the first current mirror and the first type one transistor, and is coupled to the ground potential.

The LPDDR3 input buffer as claimed in claim 12, wherein the first current mirror includes a plurality of transistors and the first type two transistors are coupled to control terminals of the transistors.

The LPDDR3 input buffer as described in claim 12, further comprising: A second type-1 transistor, biased by a first bias voltage, is coupled between the first type-1 transistor and the second current mirror.

The LPDDR3 input buffer as described in claim item 10, wherein the voltage-controlled transmission circuit includes: A first type two transistor is turned on or off controlled by the reference voltage, wherein when the predetermined voltage is lower than the second predetermined value, the first type two transistor is turned on.

The LPDDR3 input buffer as described in claim item 15, wherein the voltage-controlled transmission circuit further includes: A first type-1 transistor is coupled between the second current mirror and the first type-2 transistor, and is coupled to the predetermined voltage source.

The LPDDR3 input buffer as claimed in claim 15, wherein the first current mirror includes a plurality of transistors and the transistor of the first type is coupled to control terminals of the transistors.

The LPDDR3 input buffer as described in claim 15, further comprising: A second type 2 transistor, biased by a second bias voltage, is coupled between the first type 2 transistor and the first current mirror.