KR20100122280A - Trench mosfet with embedded schottky barrier diode and manufacture method thereof - Google Patents

Abstract

PURPOSE: A schottky barrier diode embedded trench metal oxide semiconductor field effect transistor(MOSFET) and a method for manufacturing the same are provided to reduce a forward direction voltage and a reverse recovery time by embedding the schottky barrier diode without a MOSFET channel region. CONSTITUTION: A semiconductor substrate(110) includes a gate trench(113) and a recessed field plate(RFP) trench(114) which is spaced apart from the gate trench. A gate region(120) includes a gate insulating film on the gate trench and gate poly silicon formed on the gate insulating film. An RFP insulating film(131) is formed on the RFP trench. RFP poly-silicon(132) is formed on the RFP insulating film.

Description

TRENCH MOSFET WITH EMBEDDED SCHOTTKY BARRIER DIODE AND MANUFACTURE METHOD THEREOF}

The present invention relates to a trench MOSFET with a Schottky barrier diode and a method of manufacturing the same.

Referring to FIG. 1A, a MOSFET with a conventional parasitic diode is shown, and referring to FIG. 1B, a MOSFET to which an external Schottky barrier diode is connected is shown.

As shown in FIG. 1A, in general, a MOSFET has a parasitic pn junction diode formed between a source (S) and a drain (D). Such parasitic pn junction diodes are used, for example, as a Fast Recovery Diode (FRD) when the load is a motor drive.

However, the parasitic pn junction diode Dpn has a high forward voltage VF of about 0.6V, which acts as a factor of preventing high-speed switching operation and low power consumption. In the case of the pn junction diode, a carrier (hole) is injected from the p-type region to the n-type region when the forward voltage is applied (on state). When the reverse voltage is applied, first, carriers accumulated in the n-type region are discharged or recombined, and then the depletion layer starts to expand. In other words, a time (reverse recovery time: Trr) for the outflow or recombination of this carrier occurs before it is turned off, and this time becomes a factor that hinders high-speed operation.

In other words, the parasitic pn junction diode Dpn may be used as the FRD in applications that do not require high speed switching operation such as a motor drive, but are not suitable when high speed operation is required.

Therefore, as illustrated in FIG. 1B, an external Schottky barrier diode is often used in connection with a conventional MOSFET. In this manner, the parasitic pn junction diode Dpn and the external Schottky barrier diode Dsbd are connected in parallel between the source S and the drain D of the MOSFET.

The forward rise voltage VF of the pn junction diode is about 0.6V, and the forward rise voltage VF of the Schottky barrier diode is about 0.4V. Thus, the Schottky barrier diode Dsbd operates first. That is, the forward voltage VF can be reduced by connecting the Schottky barrier diode Dsbd to the outside of the MOSFET. In addition, since carriers are not accumulated, the reverse recovery time Trr can be reduced.

However, when such an externally attached Schottky barrier diode Dsbd is used, there is a limit in the number of parts and the low cost and miniaturization.

The technical problem to be solved by the present invention is to increase the breakdown voltage while lowering the on-resistance through the shallow junction using the RFP structure, and by embedding a Schottky barrier diode without loss of the MOSFET channel region, the forward voltage VF and reverse The present invention provides a trench MOSFET with a Schottky barrier diode capable of reducing recovery time Trr and a method of manufacturing the same.

According to the present invention, a Schottky barrier diode-embedded trench MOSFET may include a semiconductor substrate having a gate trench and an RFP trench formed to be spaced apart from the gate trench; A gate region having a gate insulating film formed in the gate trench and a gate polysilicon formed in the gate insulating film; And an RFP region having an RFP insulating film formed in the RFP trench and an RFP polysilicon formed in the RFP insulating film, wherein a barrier metal is deposited on the RFP trench in the RFP region, and the barrier metal is shorted with the semiconductor substrate. And key bonded to form a Schottky barrier diode.

The barrier metal may form silicide together with the semiconductor substrate.

A source metal may be deposited on the barrier metal.

The semiconductor substrate may be an N + type substrate; An N-type epitaxial layer formed on the N + type substrate; A p-type body region formed on the N-type epitaxial layer; And an n + type source region formed on the p type body region.

The barrier metal may be schottky bonded to the N-type epitaxial layer.

The barrier metal may be ohmic bonded to the n + type source region.

A p + type region may be further formed in the p type body region to be ohmic bonded to the barrier metal.

The gate trench and the RFP trench may be formed to have the same depth.

The RFP trench may be formed deeper than the depth of the gate trench.

The RFP polysilicon may be formed at a lower position than the gate polysilicon.

An upper surface of the RFP insulating film and the RFP polysilicon may be the same surface.

A drain metal may be further formed on the bottom surface of the semiconductor substrate.

An interlayer insulating layer may be further formed between the gate polysilicon and the barrier metal.

A method of manufacturing a Schottky barrier diode-embedded trench MOSFET according to the present invention includes forming a gate trench and an RFP trench in a semiconductor substrate having a low concentration of an N-type epitaxial layer; Forming a gate insulating film and a gate polysilicon in the gate trench and forming an RFP insulating film and an RFP polysilicon in the RFP trench; Forming a p-type body region and an n + -type source region in the N-type epitaxial layer; And depositing a barrier metal in the RFP trench, and allowing the barrier metal to be Schottky bonded to the N-type epitaxial layer, such that the barrier metal and the N-type epitaxial layer are Schottky diodes. .

The trench MOSFET according to the present invention has a built-in Schottky barrier diode, thereby reducing the forward voltage VF and reverse recovery time Trr with a low cost and simple structure, and improves the switching speed.

In addition, the trench MOSFET according to the present invention can reduce Rds (on), Qg and Qgd by using a recessed field plate (RFP) structure.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

2A and 2B are cross-sectional views illustrating a trench MOSFET with a Schottky barrier diode according to the present invention.

As illustrated in FIG. 2A, the trench MOSFET 100 may include a semiconductor substrate 110, a gate region 120, and an RFP region 130.

The semiconductor substrate 110 includes a high concentration N + type substrate 111 and a low concentration N type epitaxial layer 112 grown on the N + type substrate 111 at a predetermined thickness. In addition, the semiconductor substrate 110 includes a gate trench 113 and an RFP trench 114 formed at a predetermined depth from top to bottom. The gate trench 113 and the RFP trench 114 are spaced apart from each other by a predetermined distance. In addition, RFP trenches 114 are positioned at both sides of the gate trench 113. Of course, the gate trench 113 and the RFP trench 114 are formed in the N-type epitaxial layer 112 to a predetermined depth. In addition, the gate trench 113 and the RFP trench 114 are formed in the same processing step and are therefore self aligned. Accordingly, the separation distance between the gate trench 113 and the RFP trench 114 on both sides is about the same or the same. Of course, the area (ie, mesa) width between the gate trench 113 and the RFP trench 114 is thus approximately equal or the same. In addition, the depth of the gate trench 113 and the depth of the RFP trench 114 are also about the same or the same.

A low concentration p-type body region 115 and a high concentration n + type source region 116 are formed in a region between the gate trench 113 and the RFP trench 114, that is, mesa. In addition, a high concentration p + type region 117 (where the P + type region serves as a guard ring) is further formed between the RFP trench 114 and the p type body region 115. The high concentration n + type source region 116 and the high concentration p + type region 117 form an ohmic contact with a source metal 160 to be described below. In addition, the low concentration N-type epitaxial layer 112 forms a schottky contact with the source metal 160. In addition, a low concentration n-type drain-drift region 118 is formed in the n-type epitaxial layer 112 below the p-type body region 115 and the p + -type region 117. That is, an n-type drain-drift region 118 is formed between the gate trench 113 and the RFP trench 114. Of course, the drain-drift region 118 and the N + type substrate 111 in the N-type epitaxial layer 112 together form a drain of the MOSFET 100.

In this way, the MOSFET 100 according to the present invention, when the reverse bias is applied to the body-drain junction region, the strength of the electric field is weakened, so that the depletion region between the two RFP trench 114 is expanded and eventually The breakdown voltage increases.

The gate region 120 includes a gate insulating layer 121 and a gate polysilicon 122. The gate insulating layer 121 includes a first region 121a formed relatively thickly on the bottom of the gate trench 113 and a second region 121b formed relatively thinly on the sidewall of the gate trench 113. The gate insulating layer 121 may be, for example, a silicon oxide layer. The first region 121a is formed to be relatively thicker than the thickness of the RFP polysilicon 132 to be described below. In addition, the gate polysilicon 122 is formed in the second region 121b over the first region 121a. The gate polysilicon 122 is of course electrically connected to a gate metal not shown. In addition, the gate polysilicon 122 may be doped with, for example, n-type or p-type impurities. In this manner, a relatively thin second region 121b, which is a gate insulating layer 121, is interposed between the p-type body region 115 and the gate polysilicon 122. Thus, in operation of the MOSFET 100 a channel is formed in the p-type body region 115. The channel is indicated by a dashed vertical line in the figure. The upper region of the horizontal dotted line in the figure means the drain-drift region.

In this way the channels have a relatively short distance. That is, the MOSFET 100 according to the present invention has a short channel. Therefore, the MOSFET 100 according to the present invention reduces not only Ron but also gate-source capacitance Cgs and gate-drain capacitance Cgd.

An interlayer insulating layer 140 is formed on the second region 121b and the gate polysilicon 122. Thus, the gate polysilicon 122 and the source metal 160 are not shorted to each other.

The RFP region 130 includes an RFP insulating layer 131 and an RFP polysilicon 132. The RFP insulating layer 131 is formed relatively thin on the bottom of the RFP trench 114. The RFP insulating layer 131 may be, for example, a silicon oxide layer. In addition, the RFP polysilicon 132 is formed on the RFP insulating film 131. Here, the RFP insulating layer 131 and the RFP polysilicon 132 are formed at a relatively lower position than the formation position of the gate polysilicon 122. In addition, the RFP polysilicon 132 may be doped with p-type or n-type impurities.

Meanwhile, a relatively thin barrier metal 150 is formed along sidewalls of the RFP insulating layer 131, the RFP polysilicon 132, and the RFP trench 114. That is, the barrier metal 150 is formed in the low concentration N-type epitaxial layer 112, the high concentration n + type source region 116, and the high concentration p + type region 117. Substantially, the barrier metal 150 and the low concentration N-type epitaxial layer 112 make a Schottky contact with each other and also form a silicide. In addition, the barrier metal 150 and the high concentration n + type source region 116, the barrier metal 150, and the high concentration p + type region 117 form ohmic contacts and form silicides.

In this way, in the MOSFET 100 according to the present invention, when the barrier metal 150 is substantially Schottky contacted to the N-type epitaxial layer 112 of low concentration, a Schottky barrier diode (SBD) is applied to the contact region. It is formed naturally. That is, the barrier metal 150 serves as a schottky metal layer. Here, the barrier metal 150 and the gate polysilicon 122 are electrically separated by the interlayer insulating layer 140. Of course, the p-type body region 115, the N-type epitaxial layer 112, the p + -type region 117, and the N-type epitaxial layer 112 form a pn junction diode. Therefore, the MOSFET 100 according to the present invention incorporates a schottky barrier diode (SBD) as well as a pn junction diode. Here, the barrier metal 150 may be Mo, Ti, Pt, W, Ni, for example, but the present invention is not limited thereto.

A relatively thick source metal 160 is deposited in the RFP trench 114, while at the same time covering an approximately upper region of the semiconductor substrate 110. That is, the source metal 160 is formed on the barrier metal 150. For example, the source metal 160 may be aluminum. The source metal 160 serves as an anode of the Schottky barrier diode (SBD).

A drain metal 170 is formed on the bottom surface of the N + type substrate 111. The drain metal 170 may be conventional Ti, Ba, Ni, Au, Ag, but the present invention is not limited thereto.

In this manner, the trench MOSFET 100 according to the present invention has an RFP structure, which increases the breakdown voltage and simultaneously reduces the forward voltage VF and the reverse recovery time Trr by incorporating a Schottky barrier diode (SBD). Can be. Of course, the trench MOSFET 100 according to the present invention has a recessed field plate (RFP) structure, thereby reducing Rds (on), Qg and Qgd.

Meanwhile, as illustrated in FIG. 2B, the trench MOSFET 200 according to another embodiment of the present invention may have a depth of the RFP trench 114 relatively deeper than that of the gate trench 113. In this way, as the RFP region 130 is deeper, the breakdown voltage further increases. In addition, since the RFP region 130 is deeper, the area of the Schottky barrier diode SBD may be further increased. That is, the current capability is further improved by increasing the Schottky barrier diode (SBD) area.

2A and 2B, although the top and side surfaces of the n + type source region 116 are shown to be in contact with the barrier metal 150 at the same time, only the side surface of the n + type source region 116 is the barrier metal 150. 150 may be contacted.

3 is a flowchart illustrating a method of manufacturing a trench MOSFET with a Schottky barrier diode according to the present invention.

As shown in FIG. 3, a method of manufacturing a trench MOSFET 100 according to the present invention includes a mask forming step S1, a mask patterning step S2, a gate trench and an RFP trench batch forming step S3, and an insulating film batch depositing step ( S4), insulating film full etch step (S5) of RFP trench, insulating film partial etch step (S6) of gate trench, gate insulating film forming step (S7), polysilicon deposition and etch back step (S8), p-type body region forming step (S9), n + type source region forming step (S10), interlayer insulating film forming step (S11), primary contact hole forming step (S12), p + type region forming step (S13), secondary contact hole forming step (S14) The barrier metal deposition and silicide forming step (S15) and the source metal and drain metal forming step (S16) are included.

4A through 4P are sequential cross-sectional views illustrating a method of manufacturing a trench MOSFET with a Schottky barrier diode according to the present invention. Referring to FIG. 3 together, a method of manufacturing a trench MOSFET according to the present invention will be described.

As shown in FIG. 4A, in the mask forming step S1, the semiconductor substrate 110 includes a high concentration N + type substrate 111 and a low concentration N type epitaxial layer 112 formed on the N + type substrate 111. ) To form a mask 119. The mask 119 may be formed of a conventional silicon oxide film and a silicon nitride film, but the present invention is not limited thereto.

As shown in FIG. 4B, in the mask patterning step S2, the mask 119 is patterned in a predetermined pattern using a photo process and an etch process. In this manner, the semiconductor substrate 110 to be etched through the mask pattern is exposed. Here, the regions to be etched are a gate trench and an RFP trench.

As shown in FIG. 4C, in the gate trench and RFP trench batch forming step S3, the gate trench 113 and the RFP having a predetermined depth are etched by etching the semiconductor substrate 110 to a predetermined depth using the mask pattern. The trench 114 is formed in a batch. Here, since the gate trench 113 and the RFP trench 114 are formed at the same time, the depths are almost the same or the same.

As shown in FIG. 4D, in the insulating film batch deposition step S4, an insulating film 129 ′ is deposited in the gate trench 113 and the RFP trench 114. The insulating layer 129 ′ may be a conventional silicon oxide layer.

As shown in FIG. 4E, in the insulating film full etch step S5 of the RFP trench, the insulating film formed in the RFP trench 114 in the state in which the gate trench 113 is closed with a conventional photoresist 139 or the like ( 129 ') full etch. That is, the insulating film 129 ′ present in the RFP trench 114 is completely removed.

As shown in FIG. 4F, in the insulating portion partial etching step S6 of the gate trench, the photoresist 139 is removed, and the insulating layer 121 existing in the gate trench 113 is partially etched. For example, only about half of the insulating film 121 present in the gate trench 113 remains, and all others are removed. Here, for convenience of explanation, reference numeral 129 'of the insulating film is changed to 121.

As shown in FIG. 4G, in the gate insulating film forming step S7, the mask 119 is removed, and an insulating film having a predetermined thickness is formed on sidewalls of the gate trench 113 and the RFP trench 114. do. Of course, the insulating film is evenly formed on the entire upper surface of the semiconductor substrate 110. In this way, an insulating layer 121 is formed in the gate trench 113 and includes a relatively thick first region 121a and a relatively thin second region 121b, and is uniform in the RFP trench 114. A thick insulating film 131 is formed.

As illustrated in FIG. 4H, in the polysilicon deposition and etch back step S8, polysilicon is simultaneously deposited on the gate trench 113 and the RFP trench 114 on which an insulating film is formed, respectively. Here, in order to avoid confusion, the insulating film formed in the gate trench 113 is referred to as the gate insulating film 121, and the insulating film formed in the RFP trench 114 is referred to as the RFP insulating film 131. In addition, the polysilicon deposited on the gate trench 113 is referred to as gate polysilicon 122, and the polysilicon deposited on the RFP trench 114 is referred to as RFP polysilicon 132. Of course, both the gate polysilicon 122 and the RFP polysilicon 132 may be doped with n-type or p-type impurities.

In addition, the gate polysilicon 122 and the RFP polysilicon 132 as described above are etched back to a predetermined depth. Thus, the gate polysilicon 122 and the RFP polysilicon 132 are located only inside the gate trench 113 and the RFP trench 114, respectively, as shown in FIG. 4H.

As shown in FIG. 4I, in the p-type body region forming step S9, a p-type body having a predetermined depth is ion-implanted with a low concentration of p-type impurities on the N-type epitaxial layer 112 in the semiconductor substrate 110. Region 115 is formed. Here, the depth of the p-type body region 115 is smaller than the depth of the N-type epitaxial layer 112.

As shown in FIG. 4J, in the forming of the n + type source region (S10), an n + type source having a predetermined depth is ion-implanted with a high concentration of n type impurities into the p type body region 115 of the semiconductor substrate 110. Allow region 116 to be formed. Herein, the depth of the n + type source region 116 is smaller than the depth of the p type body region 115.

As shown in FIG. 4K, in the interlayer insulating film forming step S11, the gate insulating film 121 and the gate polysilicon 122 are covered with an interlayer insulating film 140 having a predetermined thickness. The interlayer insulating layer 140 may be a conventional silicon oxide layer.

As shown in FIG. 4L, in the primary contact hole forming step S12, the RFP insulating layer 131 and the RFP polysilicon 132 provided in the RFP trench 114 are partially etched. That is, the RFP insulating film 131 and the RFP polysilicon 132 remain only under the RFP trench 114, and the p-type region 115 and the n + -type source region 116 are exposed to the outside. .

As shown in FIG. 4M, in the step of forming the p + type region (S13), a high concentration of p type impurities are implanted into the sidewall of the RFP trench 114 to form a predetermined width of the p + type region 117. .

As shown in FIG. 4N, in the secondary contact hole forming step S14, the RFP insulating layer 131 and the RFP polysilicon 132 remaining in the RFP trench 114 are partially etched. In this way, some regions of the N-type epitaxial layer 112 formed under the p + type region 117 are exposed to the outside. As described below, the exposed N-type epitaxial layer 112 forms a Schottky barrier diode (SBD).

As shown in FIG. 4O, in the barrier metal deposition and silicide formation step S15, the N-type epitaxial layer 112, the n + -type source region 116, and p + exposed to the outside through the RFP trench 114. A relatively thin barrier metal 150 is deposited on the mold region 117, followed by a high temperature thermal process. Of course, the barrier metal 150 may also be formed on the interlayer insulating layer 140 including the RFP insulating layer 131 and the RFP polysilicon 132.

In addition, silicide is formed in the N-type epitaxial layer 112, the n + type source region 116, and the p + type region 117 by the thermal process. In addition, a schottky junction layer is formed between the barrier metal 150 and the N-type epitaxial layer 112 by the thermal process, and the barrier metal 150 and the n + -type source region 116 are formed by the p +. An ohmic bonding layer is formed in the mold region 117. In this way, a Schottky barrier diode (SBD) is naturally formed between the barrier metal 150 and the N-type epitaxial layer 112.

As shown in FIG. 4P, in the source metal and drain metal forming step (S16), both the RFP trench 114 and the upper region thereof are covered with the source metal 160. That is, the source metal 160 is formed on the surface of the barrier metal 150. In addition, after the formation of the source metal 160 as described above, the drain metal 170 is further formed on the lower surface of the semiconductor substrate 110. In addition, although not shown, a gate metal connected to the gate polysilicon 122 is formed.

In this manner, the trench MOSFET 100 according to the present invention has an RFP structure, which increases the breakdown voltage and simultaneously reduces the forward voltage VF and the reverse recovery time Trr by incorporating a Schottky barrier diode (SBD). Can be. In addition, the trench MOSFET 100 according to the present invention can reduce the number of components and implement low cost and miniaturization.

What has been described above is only one embodiment for implementing the Schottky barrier diode-embedded trench MOSFET according to the present invention and a method of manufacturing the same, and the present invention is not limited to the above-described embodiment, and is claimed in the following claims. As will be apparent to those skilled in the art to which the present invention pertains without departing from the gist of the present invention, the technical spirit of the present invention will be described to the extent that various modifications can be made.

FIG. 1A shows a MOSFET with a conventional parasitic diode, and FIG. 1B further shows a MOSFET coupled to a Schottky barrier diode.

2A and 2B are cross-sectional views illustrating a trench MOSFET with a Schottky barrier diode according to the present invention.

3 is a flowchart illustrating a method of manufacturing a trench MOSFET with a Schottky barrier diode according to the present invention.

4A to 4P are sequential cross-sectional views showing a method of manufacturing a trench MOSFET with a Schottky barrier diode according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100,200; Trench MOSFET according to the present invention

110; Semiconductor substrate 111; N + type substrate

112; N-type epitaxial layer 113; Gate trench

114; RFP Trench 115; p-type body area

116; n + type source region 117; p + type region (guard ring)

118; Drain-drift region 120; Gate area

121; A gate insulating film 121a; First area

121b; Second region 122; Gate polysilicon

130; RFP region 131; RFP Insulation Film

132; RFP Polysilicon 140; Interlayer insulation film

150; Barrier metal 160; Source metal

170; Drain Metal SBDs: Schottky Barrier Diodes

119; Mask 129 '; Insulating film

139; Photoresist

Claims (14)

A semiconductor substrate having a gate trench and an RFP trench formed spaced apart from the gate trench; A gate region having a gate insulating film formed in the gate trench and a gate polysilicon formed in the gate insulating film; And, An RFP region having an RFP insulating film formed in the RFP trench and an RFP polysilicon formed in the RFP insulating film; A barrier metal is deposited in the RFP trench in the RFP region, and the barrier metal is schottky bonded to the semiconductor substrate to form a schottky barrier diode. The method of claim 1, And the barrier metal forms silicide with the semiconductor substrate. The method of claim 1, Trench MOSFET, characterized in that the source metal is deposited on the barrier metal. The method of claim 1, The semiconductor substrate N + type substrates; An N-type epitaxial layer formed on the N + type substrate; A p-type body region formed on the N-type epitaxial layer; And, And an n + type source region formed over the p type body region. The method of claim 4, wherein And the barrier metal is a Schottky junction with the N-type epitaxial layer. The method of claim 4, wherein And the barrier metal is ohmic junctioned with the n + type source region. The method of claim 4, wherein And a p + type region in which the p type body region is ohmic-joined with the barrier metal. The method of claim 1, The trench and the RFP trench are formed to have the same depth. The method of claim 1, And the RFP trench is formed deeper than the depth of the gate trench. The method of claim 1, And the RFP polysilicon is formed at a lower position than the gate polysilicon. The method of claim 1, And a top surface of the RFP insulating film and the RFP polysilicon are coplanar. The method of claim 1, The trench MOSFET, characterized in that the drain metal is further formed on the lower surface of the semiconductor substrate. The method of claim 1, A trench MOSFET further comprising an interlayer insulating film formed between the gate polysilicon and the barrier metal. Forming a gate trench and an RFP trench in a semiconductor substrate having a low concentration of N-type epitaxial layer; Forming a gate insulating film and a gate polysilicon in the gate trench and forming an RFP insulating film and an RFP polysilicon in the RFP trench; Forming a p-type body region and an n + -type source region in the N-type epitaxial layer; And, And depositing a barrier metal in the RFP trench, and allowing the barrier metal to be Schottky bonded to the N-type epitaxial layer, such that the barrier metal and the N-type epitaxial layer are Schottky diodes. A method of manufacturing a trench MOSFET, characterized in that.

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