KR20100112236A - A multilayer printed cirkit board and manufacturing method thereof - Google Patents

Abstract

PURPOSE: It laminates the metallic coating to the electroless plating method of construction and the multiayer printed circuit board and manufacturing method thereof form the low resistance circuit. CONSTITUTION: The first insulation layer is formed on the first interconnection layer. The second insulation layer(60) is formed on the second wiring layer(32). The fourth plating ground layer(70) has the resin layer containing the minute metal. The fourth wiring layer(72) is formed in the first interconnection layer into the metallic coating.

Description

A multilayer printed cirkit board and manufacturing method

The present invention relates to a multilayer printed circuit board and a method of manufacturing the same, wherein a circuit is formed of a plating base layer containing metal particles on an insulating substrate, and then a metal plating layer is laminated by an electroless plating method to form a circuit having low resistance. In addition, the manufacturing cost is reduced by reducing the number of processes and the defective rate for manufacturing a printed circuit board, and it is possible to apply the manufacturing process of various types of printed circuit boards.

In general, as a process for manufacturing a printed circuit board, Korean Patent No. 2005-0061285 describes a method of forming a metal pattern by forming a potential pattern by using a photocatalytic compound on the substrate and then plating with a desired metal. There is a shortcoming that the activation time of the potential pattern is short and the defect rate is high according to the continuous process.

Japanese Patent Laid-Open No. 2003-502507 has a method of forming a metal pattern by electroless plating after forming a catalyst pattern layer pressed through a micro stamp on a surface of a substrate, but it is difficult to form a wiring uniformly. there is a problem.

US Patent No. 2004-043691 describes a method of directly forming a pattern of a metal ink through inkjet printing, but it is difficult to form a metal pattern having high resolution and low resistance and has a problem of slow production speed.

Japanese Laid-Open Patent Publication No. 2002-511643 describes a method for plating a printed pattern on a substrate, which is described as printing using a polymer material having conductive particles, which is a well-known technique. It is difficult to print a pattern thinly and uniformly, and the above patent does not provide a specific solution of a method of printing a pattern.

Korean Patent No. 10-832002 describes a method of forming a low resistance metal pattern by printing an Ag pattern on a substrate and then performing electroplating, but the existing technology requires that all circuits in the substrate be connected to the electroplating. Therefore, electrolytic plating is not possible for independent circuits in the substrate. Therefore, there is a problem that the application range of this method is limited to an RFID antenna or a loop antenna having a relatively simple circuit configuration.

The present invention has been made to solve the above problems, and an object of the present invention is to form a circuit with a plating base layer containing metal particles on an insulating substrate, and then to laminate a metal plating layer by an electroless plating method to reduce the resistance By forming a circuit of the present invention, the manufacturing cost is reduced by reducing the number of processes and the defective rate for manufacturing a printed circuit board, and it is possible to apply to various types of printed circuit board manufacturing processes.

The present invention for achieving the above object,

In a printed circuit board having a first wiring layer formed on the first surface of the insulating substrate and a second wiring layer formed on the second surface,

A first insulating layer formed on the first wiring layer and having a second through hole;

A second insulating layer formed on the second wiring layer and having a third through hole;

A fourth plating base layer formed on the upper surface of the first wiring layer and the inner wall surface of the second through hole in a desired pattern shape and having a resin layer containing metal fine particles;

A fourth wiring layer formed of a metal plating layer on the first wiring layer opened through the fourth plating base layer and the second through hole;

A fifth plating base layer formed on the upper surface of the second wiring layer and the inner wall surface of the third through hole in a desired pattern shape and having a resin layer containing metal fine particles;

Provided is a multilayer printed circuit board comprising a fifth wiring layer made of a metal plating layer in the second wiring layer opened through the fifth plating base layer and the third through hole.

In the multilayer printed circuit board of the present invention as described above,

A third insulating layer formed on the fourth wiring layer and having a fourth through hole;

A fourth insulating layer formed on the fifth wiring layer and having a fifth through hole;

A sixth plating base layer formed on the upper surface of the third insulating layer and the inner wall surface of the fourth through hole in a desired pattern shape and having a resin layer containing metal fine particles;

A sixth wiring layer formed of a metal plating layer on the fourth wiring layer opened through the sixth plating base layer and the fourth through hole;

A seventh plating base layer formed on the upper surface of the fourth insulating layer and the inner wall surface of the fifth through hole in a shape of a desired pattern and having a resin layer containing metal fine particles; And

The fourth wiring layer opened through the seventh plating base layer and the fifth through hole may further include at least one set of a seventh wiring layer made of a metal plating layer.

The substrate comprises at least one component of polyimide, polyethylene terephthalate, polyethylene aphthalate, polyether sulfone, nylon, polytetrafluoroethylene, polyether ether ketone, polycarbonate, polyarylate, paper, ceramic, epoxy Is done.

Each of the plating base layers comprises at least one of copper, gold, silver, platinum, palladium or nickel and alloys thereof.

Each of the wiring layers comprises at least one component of copper, aluminum, nickel, silver, gold or chromium and alloys thereof.

Each said insulating layer contains one or more components from insulating materials, such as a prepreg, a bonding sheet, a coverlay film, a resist ink, and a film.

Meanwhile, a through hole penetrating at least two of each of the plating base layer, each of the wiring layer, and each of the insulating layers may be formed, and the through hole may be filled with a conductive filler for connecting the exposed wiring layer. .

In addition, the present invention for achieving the above object,

Forming a first wiring layer on the first surface of the insulating substrate and forming a second wiring layer on the second surface;

Forming a first insulating layer having a second through hole on the first wiring layer, and forming a second insulating layer having a third through hole on the second wiring layer;

On the upper surface of the first wiring layer and the inner wall surface of the second through hole, a resin layer containing metal fine particles in a desired pattern shape is printed to form a fourth plating base layer, and the upper surface of the second wiring layer and the third Forming a fifth plating base layer by printing a resin layer containing the metal fine particles in the shape of a desired pattern on the inner wall surface of the through hole; And

Electroless metal plating is performed to form a fourth wiring layer in the first wiring layer opened through the fourth plating base layer and the second through hole, and open through the fifth plating base layer and the third through hole. It provides a multi-layer printed circuit board manufacturing method comprising the step of forming a fifth wiring layer on the second wiring layer.

In the multilayer printed circuit board manufacturing method as described above,

Forming a third insulating layer having a fourth through hole on the fourth wiring layer, and forming a fourth insulating layer having a fifth through hole on the fifth wiring layer;

On the upper surface of the third insulating layer and the inner wall surface of the fourth through hole, a resin layer containing fine metal particles in a desired pattern shape is printed to form a sixth plating base layer, and the upper surface of the fourth insulating layer and the Forming a seventh plating base layer by printing a resin layer containing the metal fine particles in the desired pattern shape on the inner wall surface of the fifth through hole; And

Electroless metal plating is performed to form a sixth wiring layer in the fourth wiring layer opened through the sixth plating base layer and the fourth through hole, and is opened through the seventh plating base layer and the fifth through hole. The method may further include adding a process of forming a seventh wiring layer to the fifth wiring layer.

The first through hole is formed by one of mechanical drilling, laser drilling, and chemical etching.

Each of the plating base layers is formed by electrophotographic printing.

Meanwhile, a process of forming a through hole penetrating at least two of each of the plating base layer, each of the wiring layer, and each of the insulating layers, and filling the through hole with a conductive charge for connecting the exposed wiring layer It may include.

The present invention provides a process number for manufacturing a printed circuit board by forming a circuit having a low resistance by forming a circuit with a plating base layer containing metal particles on an insulating substrate and then laminating a metal plating layer by an electroless plating method. The manufacturing cost is reduced by reducing the defective rate, and there is an effect that can be applied to the manufacturing process of various types of printed circuit boards.

Hereinafter, the first embodiment of the present invention will be described with reference to the accompanying drawings to implement the present invention.

1 is a cross-sectional view of a first plating base layer printed on a substrate as a first embodiment of the present invention, and FIG. 2 is a first embodiment of the present invention, in which a first through hole is formed in the substrate. 3 is a cross-sectional view of a state in which a second plating base layer and a third plating base layer are printed on a substrate as a first embodiment of the present invention.

FIG. 4 shows a first embodiment of the present invention, in which an electroless plating is performed on a first plating base layer, a second plating base layer, and a third plating base layer to form a first wiring layer, a second wiring layer, and a third wiring layer. 5 is a cross-sectional view of a state in which a first insulating layer and a second insulating layer are formed in a first wiring layer and a second wiring layer, respectively, as a first embodiment of the present invention, and FIG. 1 is a cross-sectional view of a state in which a fourth plating base layer and a fifth plating base layer are formed on the first insulating layer and the second insulating layer, respectively.

7 is a cross-sectional view showing a fourth wiring layer and a fifth wiring layer formed on a fourth plating base layer and a fifth plating base layer as a first embodiment of the present invention, and FIG. 8 is a first embodiment of the present invention. FIG. 9 is a cross-sectional view of a third insulating layer and a fourth insulating layer formed on a fourth wiring layer and a fifth wiring layer, respectively. FIG. 9 is a cross-sectional view of a filler filled in a through hole as a first embodiment of the present invention. 9 is a cross-sectional view of a filling state in a through hole as a first embodiment of the present invention.

The multilayer printed circuit board according to the present embodiment is formed of an insulating substrate 10 having a first through hole 12 and a desired pattern formed on a first surface of the substrate 10 and containing metal fine particles. The first plating base layer 20 having a ground layer, the first wiring layer 22 formed on the first plating base layer 20 and made of a metal plating layer, and the shape of a desired pattern on the second surface of the substrate 10. A second plating base layer 30 formed along the side and having a resin layer containing metal fine particles, a second wiring layer 32 formed on the second plating base layer 30 and made of a metal plating layer, and a first through The third plating base layer 40 covering the inner wall surface of the hole 12 and the third plating base layer 40 are formed on the metal to connect the first wiring layer 22 and the second wiring layer 32. A third wiring layer 42 made of a plating layer, a first insulating layer 50 formed on the first wiring layer 22 and having a second through hole 52; The second insulating layer 60 formed on the second wiring layer 32 and having the third through hole 62, the upper surface of the first wiring layer 22 and the inner wall surface of the second through hole 52 have a desired pattern. A fourth plating base layer 70 formed along the shape and having a resin layer containing metal fine particles, and a first wiring layer 22 opened through the fourth plating base layer 70 and the second through hole 52. A resin layer containing metal fine particles formed on the upper surface of the fourth wiring layer 72 formed of the metal plating layer on the upper surface of the second wiring layer 32 and the inner wall surface of the third through hole 62. The fifth wiring layer 82 made of a metal plating layer on the fifth plating base layer 90 having the first and second wiring layers 32 opened through the fifth plating base layer 90 and the third through hole 62. Is done.

And a third insulating layer 90 formed on the fourth wiring layer 72 and having a fourth through hole 92 and a fifth through hole 102 formed on the fifth wiring layer 82. A sixth plating base having a resin layer containing metal fine particles formed on the upper surface of the fourth insulating layer 100 and the upper surface of the third insulating layer 90 and the inner wall surface of the fourth through hole 92. Layer, a sixth wiring layer formed of a metal plating layer in the fourth wiring layer 72 opened through the sixth plating base layer and the fourth through hole 92, and an upper surface and a fifth through hole of the fourth insulating layer 100; A seventh plating base layer formed along the shape of the desired pattern on the inner wall surface of the hole 102 and having a resin layer containing metal fine particles, and opened through the seventh plating base layer and the fifth through hole 102. A seventh wiring layer made of a metal plating layer is further formed on the four wiring layer 72.

Each of the insulating layer, the plating base layer, and the wiring layer may be repeatedly formed in a desired quantity, thereby manufacturing a plurality of printed circuit boards.

Substrate 10 is based on one of polyimide, polyethylene terephthalate, polyethylene aphthalate, polyether sulfone, nylon, polytetrafluoroethylene, polyether ether ketone, polycarbonate, polyarylate, paper, ceramic, and epoxy. Select to manufacture.

Each plating base layer is formed by electrophotographic printing by selecting one of copper, gold, silver, platinum, palladium or nickel and alloys thereof as a main component.

Each wiring layer is manufactured through an electroless metal plating process by selecting one of copper, aluminum, nickel, silver, gold or chromium and alloys thereof.

Each insulating layer is formed by selecting one of insulating materials such as a prepreg, a bonding sheet, a coverlay film, a resist ink, and a film.

As a method of forming each of these insulating layers, there exists a method of apply | coating the insulating material of a gel state by the printing method, and there exists a method of adhering the insulating material of a plate shape by the coating method.

Meanwhile, as another example of the present embodiment, through holes 110 are formed through the respective plating base layers, the respective wiring layers, and the respective insulating layers in order to connect the respective wiring layers. The hole 110 is electrically connected to each of the wiring layers exposed to the through hole 100 by charging the charging filler 120 for connecting the exposed wiring layers.

The filler 120 may be made of a resin containing a C _U component, it may be configured as a C _U plating layer.

Hereinafter, a process of manufacturing the multilayer printed circuit board of the present embodiment will be described.

First, the first plating base layer 20 is formed by printing a resin layer containing metal fine particles in the shape of a desired pattern on the first surface of the insulating base 10.

Then, the first through hole 12 is drilled into the first plating base layer 20 and the base material 10.

Then, the second plating base layer 30 and the third plating base layer are printed by printing a resin layer containing metal fine particles in a desired pattern on the second surface of the substrate 10 and the wall surface of the first through hole 12. 40 is formed.

Then, electroless metal plating is performed to form the first wiring layer 22 and the second wiring layer 32 on the first plating base layer 20, the second plating base layer 30, and the third plating base layer 40. And third wiring layers 42 are formed, respectively.

The first insulating layer 50 having the second through hole 52 is formed on the first wiring layer 22, and the second insulating layer having the third through hole 62 is formed on the second wiring layer 32. Form layer 60.

Then, the fourth plating base layer 70 is formed by printing a resin layer containing metal fine particles in the shape of a desired pattern on the upper surface of the first wiring layer 22 and the inner wall surface of the second through hole 52. On the upper surface of the second wiring layer 32 and the inner wall surface of the third through hole 62, a resin layer containing the metal fine particles in the shape of a desired pattern is printed to form the fifth plating base layer 90.

Then, the fourth wiring layer 72 is formed on the first wiring layer 22 opened through the fourth plating base layer 70 and the second through hole 52 by electroless metal plating. A fifth wiring layer 82 is formed in the second wiring layer 32 opened through the layer 90 and the third through hole 62.

In the above, the first through hole 12 is formed by one of mechanical drilling, laser drilling, and chemical etching.

Each plating base layer is formed by electrophotographic printing.

On the other hand, following the above process, the third insulating layer 90 having the fourth through hole 92 is formed on the fourth wiring layer 72, and the fifth through hole 102 is formed on the fifth wiring layer 82. A fourth insulating layer 100 having a portion is formed.

Then, a resin layer containing fine metal particles is printed on the upper surface of the third insulating layer 90 and the inner wall surface of the fourth through hole 92 in the shape of a desired pattern to form a sixth plating base layer. On the upper surface of the layer 100 and the inner wall surface of the fifth through hole 102, a resin layer containing the metal fine particles in the shape of a desired pattern is printed to form a seventh plating base layer.

Electroless metal plating is performed to form a sixth wiring layer in the fourth wiring layer 72 opened through the sixth plating base layer and the fourth through hole 92, and the seventh plating base layer and the fifth through hole ( A seventh wiring layer is formed on the fifth wiring layer 82 opened through the 102.

As described above, the steps of adding each insulating layer and wiring layer are repeatedly performed as many times as desired to produce a plurality of printed circuit boards.

Meanwhile, as another example of this embodiment, in order to electrically connect each wiring layer, a through hole 110 is formed in each of the plating base layer, each wiring layer, and each insulating layer, as shown in FIG. In the following, the process of filling the conductive filler 120 for connecting the exposed wiring layer may be added.

Hereinafter, a second embodiment of the present invention will be described with reference to the accompanying drawings to implement the present invention.

FIG. 10 is a cross-sectional view of a state in which a first copper plate layer and a second copper plate layer are stacked on a substrate as a second embodiment of the present invention, and FIG. 11 is a second embodiment of the present invention, wherein 12 is a cross-sectional view of a perforated state, and FIG. 12 is a cross-sectional view of a first panel plating layer and a second panel plating layer respectively formed on the first copper plate layer and the second copper plate layer as a second embodiment of the present invention.

FIG. 13 is a cross-sectional view of a circuit in which a circuit is formed by etching a first panel plating layer and a second panel plating layer as a second embodiment of the present invention, and FIG. 14 is a first panel plating layer as a second embodiment of the present invention. FIG. 15 is a cross-sectional view of a state in which a first insulating layer and a second insulating layer are respectively formed on the second panel plating layer, and FIG. 15 is a second embodiment of the present invention. It is sectional drawing of the state which formed the layer and the 5th plating base layer.

FIG. 16 is a cross-sectional view of a fourth wiring base layer and a fifth plating base layer in a state in which a fourth wiring layer and a fifth wiring layer are respectively formed as a second embodiment of the present invention, and FIG. 17 is a second embodiment of the present invention. A cross-sectional view of a state in which a third insulating layer and a fourth insulating layer are formed in the fourth wiring layer and the fifth wiring layer, respectively.

The printed circuit board of this embodiment includes an insulating base material 10 having a first through hole 12, a first copper plate layer 24 formed along a shape of a desired pattern on the first surface of the base material 10, The first panel plating layer 26 formed on the first copper plate layer 24, the second copper plate layer 34 formed along the shape of the desired pattern on the second surface of the substrate 10, and the second copper plate layer ( 34, the third panel plating layer 36 formed on the inner wall surface of the first through hole 12, and the third panel plating layer 44 for connecting the first plating layer and the second plating layer, A first insulating layer 50 formed on the panel plating layer 26 and having a second through hole 52, and a second insulation formed on the second panel plating layer 36 and having a third through hole 62. A fourth plating base layer having a resin layer containing metal fine particles formed on the layer 60, the upper surface of the first panel plating layer 26 and the inner wall surface of the second through hole 52, 70) And a fourth wiring layer 72 formed of a metal plating layer on the first panel plating layer 26 opened through the fourth plating base layer 70 and the second through hole 52, and the second panel plating layer 36. A fifth plating foundation layer 90, a fifth plating foundation layer 90, and a fifth plating foundation layer 90 having a resin layer containing metal fine particles formed on the upper surface of the inner surface and the inner wall surface of the third through hole 62. The second panel plating layer 36 opened through the third through hole 62 is formed of a fifth wiring layer 82 made of a metal plating layer.

And a third insulating layer 90 formed on the fourth wiring layer 72 and having a fourth through hole 92 and a fifth through hole 102 formed on the fifth wiring layer 82. A sixth plating base having a resin layer containing metal fine particles formed on the upper surface of the fourth insulating layer 100 and the upper surface of the third insulating layer 90 and the inner wall surface of the fourth through hole 92. Layer, a sixth wiring layer formed of a metal plating layer in the fourth wiring layer 72 opened through the sixth plating base layer and the fourth through hole 92, and an upper surface and a fifth through hole of the fourth insulating layer 100. A seventh plating base layer formed along the shape of the desired pattern on the inner wall surface of the hole 102 and having a resin layer containing metal fine particles, and opened through the seventh plating base layer and the fifth through hole 102. The seventh wiring layer including the metal plating layer is additionally included in the four wiring layer 72 to constitute a multilayer printed circuit board.

Substrate 10 is a polyimide, polyethylene terephthalate, polyethylene aphthalate, polyether sulfone, nylon, polytetrafluoroethylene, polyether ether ketone, polycarbonate, polyarylate, paper, ceramic, epoxy It is made to include.

Each plating base layer comprises at least one of copper, gold, silver, platinum, palladium or nickel and alloys thereof.

Each wiring layer comprises at least one of copper, aluminum, nickel, silver, gold or chromium and alloys thereof.

Each insulating layer contains one or more components from insulating materials, such as a prepreg, a bonding sheet, a coverlay film, a resist ink, and a film.

As a method of forming each of these insulating layers, there exists a method of apply | coating the insulating material of a gel state by the printing method, and there exists a method of adhering the insulating material of a plate shape by the coating method.

On the other hand, as another example of the present embodiment, in order to connect each wiring layer, a through hole 110 through each plating base layer, each wiring layer, and each insulating layer is formed as shown in FIG. The hole 110 is electrically connected to each of the wiring layers exposed to the through hole 100 by charging the charging filler 120 for connecting the exposed wiring layers.

The filler 120 may be made of a resin containing a C _U component, it may be configured as a C _U plating layer.

The manufacturing process of this embodiment is described below.

First, the first copper plate layer 24 is formed on the first surface of the insulating base 10, and the second copper plate layer 34 is formed on the second surface.

Then, the first through hole 12 is drilled into the first copper plate layer 24, the base material 10, and the second copper plate layer 34.

The first panel plating layer 26, the first panel plating layer 26, and the third panel plating layer are formed on the inner wall surfaces of the first copper plate layer 24, the second copper plate layer 34, and the first through hole 12, respectively. Form 44.

Then, a circuit is formed on the first panel plating layer 26, the first copper plate layer 24, the second panel plating layer 36, and the second copper plate layer 34 by etching.

The first insulating layer 50 having the second through hole 52 is formed on the first panel plating layer 26, and the third through hole 62 is formed on the second panel plating layer 36. 2 insulating layer 60 is formed.

Then, on the upper surface of the first panel plating layer 26 and the inner wall surface of the second through hole 52, a resin layer containing fine metal particles in the shape of a desired pattern is printed to form a fourth plating base layer 70, On the upper surface of the second panel plating layer 36 and the inner wall surface of the third through hole 62, a resin layer containing the metal fine particles in the shape of a desired pattern is printed to form the fifth plating base layer 90. .

Then, the fourth wiring layer 72 is formed on the first panel plating layer 26 opened through the fourth plating base layer 70 and the second through hole 52 by electroless metal plating. A fifth wiring layer 82 is formed in the second panel plating layer 36 opened through the base layer 90 and the third through hole 62.

On the other hand, in addition to the above process, a third insulating layer 90 having a fourth through hole 92 is formed on the fourth wiring layer 72, and the fifth through hole 102 is formed on the fifth wiring layer 82. The branches form a fourth insulating layer 100.

Then, a resin layer containing fine metal particles in the shape of a desired pattern is printed on the upper surface of the third insulating layer 90 and the inner wall surface of the fourth through hole 92 to form a sixth plating base layer. On the upper surface of the insulating layer 100 and the inner wall surface of the fifth through hole 102, a resin layer containing the metal fine particles in the shape of a desired pattern is printed to form a seventh plating base layer.

Then, electroless metal plating is performed to form a sixth wiring layer in the fourth wiring layer 72 opened through the sixth plating base layer and the fourth through hole 92, and the seventh plating base layer and the fifth through hole. The multilayer printed circuit board is manufactured by performing the process of adding the process of forming the seventh wiring layer to the fifth wiring layer 82 opened through the 102 at least once.

The first through hole 12 is selected by one of mechanical drilling, laser drilling, and chemical etching.

It is best to form each plating base layer by electrophotographic printing.

Meanwhile, as another example of the present embodiment, in order to connect each wiring layer, a through hole 110 is formed in each plating base layer, each wiring layer, and each insulating layer as shown in FIG. 18, and the exposed hole 110 is exposed. The process of charging the electricity supply filler 120 for connecting the wiring layer which has been provided can be added.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above-described embodiments, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the following claims. Anyone skilled in the art will have the technical idea of the present invention to the extent that various changes or modifications can be made.

1 is a cross-sectional view of a state in which a first plating base layer is printed on a substrate as a first embodiment of the present invention;

2 is a cross-sectional view of a state in which a first through hole is drilled in a substrate as a first embodiment of the present invention;

3 is a cross-sectional view of a state in which a second plating base layer and a third plating base layer are printed on a substrate as a first embodiment of the present invention;

FIG. 4 shows a first embodiment of the present invention, in which an electroless plating is performed on a first plating base layer, a second plating base layer, and a third plating base layer to form a first wiring layer, a second wiring layer, and a third wiring layer. Section of status,

5 is a cross-sectional view of a state in which a first insulating layer and a second insulating layer are formed in a first wiring layer and a second wiring layer, respectively, as a first embodiment of the present invention;

FIG. 6 is a cross-sectional view of a fourth plating base layer and a fifth plating base layer formed on a first insulating layer and a second insulating layer, respectively, as a first embodiment of the present invention;

FIG. 7 is a cross-sectional view of a fourth wiring base layer and a fifth plating base layer in a state in which a fourth wiring layer and a fifth wiring layer are respectively formed as a first embodiment of the present invention; FIG.

8 is a cross-sectional view of a third insulating layer and a fourth insulating layer formed on a fourth wiring layer and a fifth wiring layer, respectively, as a first embodiment of the present invention;

9 is a cross-sectional view showing a filling state in a through hole as a first embodiment of the present invention;

FIG. 10 is a cross-sectional view of a state in which a first copper plate layer and a second copper plate layer are stacked on a substrate as a second embodiment of FIG.

11 is a cross-sectional view of a second embodiment of the present invention in a state in which a first through hole is drilled in a base material;

12 is a cross-sectional view of a second embodiment of the present invention in which a first panel plating layer and a second panel plating layer are formed on a first copper plate layer and a second copper plate layer, respectively;

FIG. 13 is a cross-sectional view of a second embodiment of the present invention in which a circuit is formed by etching a first panel plating layer and a second panel plating layer;

14 is a cross-sectional view of a second embodiment of the present invention in which a first insulating layer and a second insulating layer are formed on a first panel plating layer and a second panel plating layer, respectively;

FIG. 15 is a cross-sectional view of a fourth plating base layer and a fifth plating base layer formed on a first insulating layer and a second insulating layer, respectively, as a second embodiment of the present invention; FIG.

FIG. 16 is a cross-sectional view illustrating a fourth wiring layer and a fifth wiring layer formed on a fourth plating base layer and a fifth plating base layer, respectively, as a second embodiment of the present invention; FIG.

FIG. 17 is a cross-sectional view of a third insulating layer and a fourth insulating layer formed on a fourth wiring layer and a fifth wiring layer, respectively, as a second embodiment of the present invention; FIG.

18 is a cross-sectional view of a second embodiment of the present invention in a state where a filler is filled in a through hole.

Description of the Related Art

10: base material 12: first through hole

20: first plating base layer 22: first wiring layer

24: first copper plate layer 26: first panel plating layer

30: second plating base layer 32: second wiring layer

34: second copper plate layer 36: second panel plating layer

40: third plating base layer 42: third wiring layer

44: third panel plating layer 50: first insulating layer

52: second through hole 60: second insulating layer

62: third through hole 70: fourth plating base layer

72: fourth wiring layer 80: fifth plating base layer

82: fifth wiring layer 90: third insulating layer

92: fourth through hole 100: fourth insulating layer

102: fifth through hole 110: throw hole

120: Filling

Claims (12)

In a printed circuit board having a first wiring layer formed on the first surface of the insulating substrate and a second wiring layer formed on the second surface, A first insulating layer formed on the first wiring layer and having a second through hole; A second insulating layer formed on the second wiring layer and having a third through hole; A fourth plating base layer formed on the upper surface of the first wiring layer and the inner wall surface of the second through hole in a desired pattern shape and having a resin layer containing metal fine particles; A fourth wiring layer formed of a metal plating layer on the first wiring layer opened through the fourth plating base layer and the second through hole; A fifth plating base layer formed on the upper surface of the second wiring layer and the inner wall surface of the third through hole in a desired pattern shape and having a resin layer containing metal fine particles; And a fifth wiring layer made of a metal plating layer in the second wiring layer opened through the fifth plating base layer and the third through hole. The semiconductor device of claim 1, further comprising: a third insulating layer formed on the fourth wiring layer and having a fourth through hole; A fourth insulating layer formed on the fifth wiring layer and having a fifth through hole; A sixth plating base layer formed on the upper surface of the third insulating layer and the inner wall surface of the fourth through hole in a desired pattern shape and having a resin layer containing metal fine particles; A sixth wiring layer formed of a metal plating layer on the fourth wiring layer opened through the sixth plating base layer and the fourth through hole; A seventh plating base layer formed on the upper surface of the fourth insulating layer and the inner wall surface of the fifth through hole in a shape of a desired pattern and having a resin layer containing metal fine particles; A seventh wiring layer made of a metal plating layer on the fourth wiring layer opened through the seventh plating base layer and the fifth through hole; Multi-layer printed circuit board comprising at least one trillion. The method according to claim 1 or 2, wherein the substrate is polyimide, polyethylene terephthalate, polyethylene phthalate, polyether sulfone, nylon, polytetrafluoroethylene, polyether ether ketone, polycarbonate, polyarylate, paper, ceramic, A multilayer printed circuit board comprising at least one component in an epoxy. The multilayer printed circuit board according to claim 1 or 2, wherein each of the plating base layers comprises at least one component of copper, gold, silver, platinum, palladium or nickel and alloys thereof. The multilayer printed circuit board of claim 1, wherein each of the wiring layers comprises at least one component of copper, aluminum, nickel, silver, gold, or chromium and alloys thereof. The multilayer printed circuit board according to claim 1 or 2, wherein each of the insulating layers comprises at least one component among insulating materials such as prepregs, bonding sheets, coverlay films, resist inks, and films. The through hole which penetrates 2 or more of each said plating base layer, each said wiring layer, and each said insulating layer is formed, The said through hole is an electricity supply for connecting an exposed wiring layer. Multilayer printed circuit board, characterized in that the filling is filled. Forming a first wiring layer on the first surface of the insulating substrate and forming a second wiring layer on the second surface; Forming a first insulating layer having a second through hole on the first wiring layer, and forming a second insulating layer having a third through hole on the second wiring layer; On the upper surface of the first wiring layer and the inner wall surface of the second through hole, a resin layer containing metal fine particles in a desired pattern shape is printed to form a fourth plating base layer, and the upper surface of the second wiring layer and the third Forming a fifth plating base layer by printing a resin layer containing the metal fine particles in the shape of a desired pattern on the inner wall surface of the through hole; And Electroless metal plating is performed to form a fourth wiring layer in the first wiring layer opened through the fourth plating base layer and the second through hole, and open through the fifth plating base layer and the third through hole. A method for manufacturing a multilayer printed circuit board comprising the step of forming a fifth wiring layer on the second wiring layer. The method of claim 8, further comprising: forming a third insulating layer having a fourth through hole on the fourth wiring layer, and forming a fourth insulating layer having a fifth through hole on the fifth wiring layer; On the upper surface of the third insulating layer and the inner wall surface of the fourth through hole, a resin layer containing fine metal particles in a desired pattern shape is printed to form a sixth plating base layer, and the upper surface of the fourth insulating layer and the Forming a seventh plating base layer by printing a resin layer containing the metal fine particles in the desired pattern shape on the inner wall surface of the fifth through hole; And Electroless metal plating is performed to form a sixth wiring layer in the fourth wiring layer opened through the sixth plating base layer and the fourth through hole, and is opened through the seventh plating base layer and the fifth through hole. The method of manufacturing a multi-layer printed circuit board, characterized in that the step of adding the step of forming a seventh wiring layer to the fifth wiring layer is performed at least one time. 10. The method of claim 8 or 9, wherein the first through hole is formed by one of mechanical drilling, laser drilling, and chemical etching. 10. The method of claim 8 or 9, wherein each of the plating base layers is formed by an electrophotographic printing method. 10. The through hole according to claim 8 or 9, wherein a through hole penetrating at least two of each of the plating base layer, each of the wiring layer, and each of the insulating layers is formed, and the wiring hole is connected to the exposed hole. A method for manufacturing a multilayer printed circuit board comprising the step of filling a filling material.

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