KR20100109046A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
KR20100109046A
KR20100109046A KR1020090027428A KR20090027428A KR20100109046A KR 20100109046 A KR20100109046 A KR 20100109046A KR 1020090027428 A KR1020090027428 A KR 1020090027428A KR 20090027428 A KR20090027428 A KR 20090027428A KR 20100109046 A KR20100109046 A KR 20100109046A
Authority
KR
South Korea
Prior art keywords
electrode
barrier layer
diffusion barrier
semiconductor chip
semiconductor package
Prior art date
Application number
KR1020090027428A
Other languages
Korean (ko)
Inventor
김성철
이하나
조재호
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090027428A priority Critical patent/KR20100109046A/en
Publication of KR20100109046A publication Critical patent/KR20100109046A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor package is disclosed. The semiconductor package includes a semiconductor chip having an upper surface and a lower surface facing the upper surface, a through hole penetrating the upper surface and the lower surface, a through electrode protruding from the lower surface, and a protruding electrode protruding from the lower surface and protruding from the lower surface. And a diffusion barrier layer covering at least a portion of the surface of the through electrode.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package.

Recently, semiconductor packages including semiconductor chips and semiconductor chips capable of storing massive data and processing massive data in a short time have been developed.

Recently, in order to further improve data storage capacity and data processing speed, a multilayer semiconductor package in which at least two semiconductor chips are stacked has been developed.

In the case of a stacked semiconductor package, signal transfer members for applying an electrical signal to each stacked semiconductor chips are required. The signal transmitting members for applying an electrical signal to each semiconductor chip in the stacked semiconductor package may be conductive wires or through electrodes penetrating through the semiconductor chips.

However, when the semiconductor chips stacked by using the through electrodes are electrically connected, especially when the through electrodes include copper, many problems occur due to diffusion of copper ions.

The present invention provides a semiconductor package which prevents ion diffusion by a through electrode containing copper.

According to the present invention, a semiconductor package includes a semiconductor chip having an upper surface and a lower surface facing the upper surface and a through hole penetrating through the upper surface and the lower surface, a through electrode penetrating the semiconductor chip and protruding to a predetermined height from the lower surface; And a diffusion barrier layer covering at least a portion of the through electrode exposed from the semiconductor chip.

The diffusion barrier layer is disposed on an end of the through electrode.

The diffusion barrier layer extends to an end portion of the through electrode and a side surface connected to the end portion.

The diffusion barrier layer extends between the inner surface of the semiconductor chip formed by the through electrode and the through hole.

The through electrode includes copper, and the diffusion barrier layer includes any one of a zinc film, a palladium film, a nickel film, and a manganese film.

According to the present invention, the copper ions are prevented from diffusing from the semiconductor chip from the through electrode including copper, and thus the wirings disposed in a portion adjacent to the through electrode have an effect of preventing the short or the through electrode from disconnection.

Hereinafter, a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The present invention may be embodied in various other forms without departing from the spirit of the invention.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor package 100 includes a semiconductor chip 10, a through electrode 20, and a diffusion barrier layer 30.

The semiconductor chip 10 has a rectangular parallelepiped shape, for example. The semiconductor chip 10 having a rectangular parallelepiped shape has an upper surface 1 and a lower surface 2 facing the upper surface 1. Inside the semiconductor chip 10, a circuit unit 3 including a data storage unit (not shown) for storing data and a data processing unit (not shown) for processing data is disposed.

The semiconductor chip 10 includes a through hole 4, and the through hole 4 penetrates the upper surface 1 and the lower surface 2 facing the upper surface 1 of the semiconductor chip 10. An insulating film 5 having a thin thickness is formed on the inner surface of the semiconductor chip 10 formed by the through holes 4 penetrating the upper surface 1 and the lower surface 2 of the semiconductor chip 10. The insulating film 5 may be an organic film or an inorganic film.

The through electrode 20 is disposed in the through hole 4 of the semiconductor chip 10, and the through hole 4 is disposed above the insulating film 5. The through electrode 20 has a columnar shape, for example, and at least one end of both ends of the through electrode 20 is predetermined from the upper surface 1 and / or the lower surface 2 of the semiconductor chip 10. Protrudes to a height. In this embodiment, one end of the through electrode 20 protruding from the lower surface 2 of the semiconductor chip 10 protrudes from the lower surface 2 to a specified height H. In the present embodiment, the through electrode 20 includes copper.

When the through electrode 20 includes copper, copper ions contained in the through electrode 20 are diffused, which causes copper ions from short circuits of the wirings (not shown) adjacent to the through electrode 20 and from the through electrode 20. This discharge may cause the through electrode 20 to be disconnected.

In this embodiment, in order to prevent diffusion of copper ions from the through electrode 20, the diffusion barrier layer 30 is disposed on at least a part of the surface of the through electrode 20 protruding from the upper surface 1 and the lower surface 2. do. Examples of the material that can be used as the diffusion barrier layer 30 include a zinc film containing zinc, a palladium film containing palladium, a nickel film containing nickel, and a manganese film containing manganese.

In the present embodiment, the diffusion barrier layer 30 may be formed by, for example, a sputtering process, a plating process, or the like.

In FIG. 1, the diffusion barrier layer 30 prevents diffusion of copper ions discharged from the through electrode 20. The diffusion barrier layer 30 is disposed on, for example, the end of the through electrode 20.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention. The semiconductor package illustrated in FIG. 2 is substantially the same as the semiconductor package described with reference to FIG. 1 except for the diffusion barrier layer. Therefore, duplicate descriptions of the same parts will be omitted, and the same parts and the same reference numerals will be given to the same parts.

Referring to FIG. 2, the semiconductor package 100 includes a semiconductor chip 10, a through electrode 20, and a diffusion barrier layer 35.

The diffusion barrier layer 35 is disposed on the surface of the through electrode 20 protruding from the upper surface 1 and the lower surface 2 in order to prevent diffusion of copper ions from the through electrode 20. In the present embodiment, the diffusion barrier layer 35 is disposed on the end of the through electrode 20 and the side of the through electrode 20 connected to the end, respectively. That is, the diffusion barrier layer 35 completely covers the exposed portion of the through electrode 20. Examples of the material that can be used as the diffusion barrier layer 35 include a zinc film containing zinc, a palladium film containing palladium, a nickel film containing nickel, and a manganese film containing manganese.

3 is a cross-sectional view illustrating a semiconductor package in accordance with still another embodiment of the present invention. The semiconductor package illustrated in FIG. 3 is substantially the same as the semiconductor package described with reference to FIG. 2 except for the diffusion barrier layer. Therefore, duplicate descriptions of the same parts will be omitted, and the same parts and the same reference numerals will be given to the same parts.

Referring to FIG. 3, the semiconductor package 100 includes a semiconductor chip 10, a through electrode 20, and a diffusion barrier layer 40.

In order to prevent diffusion of copper ions from the through electrode 20, the diffusion barrier layer 40 may have a surface of the through electrode 20 protruding from the upper surface 1 and the lower surface 2, as well as the insulating film 5 and the through electrode ( It is interposed between 20). The diffusion barrier layer 40 interposed between the insulating film 5 and the through electrode 20 has a pipe shape.

Examples of the material that can be used as the diffusion barrier layer 40 include a zinc film containing zinc, a palladium film containing palladium, a nickel film containing nickel, and a manganese film containing manganese.

The diffusion barrier layer 40 shown in FIGS. 1-3 includes, for example, a single material or a single metal. Alternatively, the diffusion barrier layer 40 may be an alloy including at least two metals.

As described above in detail, the copper ions are prevented from being diffused from the semiconductor chip from the through electrode including copper, and the wirings disposed in a portion adjacent to the through electrode have an effect of preventing the short or the through electrode from being disconnected.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package in accordance with still another embodiment of the present invention.

Claims (5)

A semiconductor chip having an upper surface and a lower surface facing the upper surface and a through hole penetrating through the upper surface and the lower surface; A through electrode penetrating the semiconductor chip and protruding a predetermined height from the lower surface; And And a diffusion barrier layer covering at least a portion of the through electrode exposed from the semiconductor chip. The method of claim 1, The diffusion barrier layer is disposed on the end of the through electrode. The method of claim 1, The diffusion barrier layer extends to an end portion of the through electrode and a side surface connected to the end portion. The method of claim 1, The diffusion barrier layer extends between the inner surface of the semiconductor chip formed by the through electrode and the through hole. The method of claim 1, The through electrode includes copper, and the diffusion barrier layer includes one of a zinc film, a palladium film, a nickel film, and a manganese film.
KR1020090027428A 2009-03-31 2009-03-31 Semiconductor package KR20100109046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090027428A KR20100109046A (en) 2009-03-31 2009-03-31 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090027428A KR20100109046A (en) 2009-03-31 2009-03-31 Semiconductor package

Publications (1)

Publication Number Publication Date
KR20100109046A true KR20100109046A (en) 2010-10-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090027428A KR20100109046A (en) 2009-03-31 2009-03-31 Semiconductor package

Country Status (1)

Country Link
KR (1) KR20100109046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9099541B2 (en) 2011-03-16 2015-08-04 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9099541B2 (en) 2011-03-16 2015-08-04 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device

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