KR20100108076A - Converter capable of outputting multiple voltage by using common capacitor and voltage output method thereof - Google Patents

Abstract

PURPOSE: A converter and a voltage output method thereof are provided to reduce the number of a capacitor and a pin by using a single common capacitor. CONSTITUTION: A converter(10) comprises a common capacitor(Cin) and an output part(70). The common capacitor charges and discharges an input voltage. The output part comprises a switch control signal generating part(20), a first switch(11), and at least one charge pump(71~7n). The switch control signal generating part generates a first and a second switch control signal based on a square wave having a predetermined frequency. The first switch charges the input voltage to the common capacitor in response to the first switch control signal. The charge pump outputs the voltage, which is charged in the common capacitor, to an output terminal.

Description

Converter capable of multiple output using a common capacitor and a voltage output method using the converter {{Converter capable of outputting multiple voltage by using common capacitor and voltage output method}}

The present invention relates to a converter, and more particularly, to a converter capable of multiple output using a common capacitor and a voltage output method using the converter.

Recently, with the development of information and communication technology, various additional service functions of a portable device are enabled. For example, in the case of a mobile phone, initially only a communication function was possible, but various additional service functions such as an MP3 player, a camera, and a PDA are additionally provided and used.

The power supply circuit provided inside the portable device uses separate power domains for the core, IO, memory, and peripherals. In general, a mobile phone is composed of a plurality of blocks, and is largely composed of an RF block and a logic block, and most of the mobile phones are supplied with operating power from a separate low drop-out regulator (LDO).

However, the low dropout regulator (LDO), which is widely used as a multi-output power supply, has a problem of low efficiency because the output voltage is consumed as heat.

On the other hand, the charge-pump DC-DC converter, which is generally used as a multi-output power source for portable devices, has high efficiency compared to a low drop-out regulator (LDO), driving not only a power stage but also a load such as a light emitting diode (LED). It is also widely used.

However, a typical charge pump DC-DC converter requires at least four pins, including two capacitors and input pins, to produce one output. In other words, there is a need for a converter that is more efficient than LDO and minimizes the number of output pins and capacitors.

Accordingly, an object of the present invention is to provide a converter capable of multi-output using a common capacitor and a voltage output method using the converter.

In order to solve the above problems, a converter includes a common capacitor charging and discharging an input voltage; And an output unit configured to charge the input voltage to the common capacitor and output the charged voltage through a plurality of output terminals based on at least one reference voltage.

The output unit may include a switch control signal generator configured to generate first and second switch control signals based on a square wave having a predetermined frequency; A first switch configured to charge the input voltage to the common capacitor in response to the first switch control signal; And at least one charge pump configured to output a voltage charged in the common capacitor to a corresponding output terminal among the plurality of output terminals, wherein each of the at least one charge pumps includes: the second switch control signal and the plurality of charge pumps; The level of the output voltage output to the corresponding output terminal may be controlled based on the feedback signal fed back from the corresponding output terminal among the two output terminals.

The first switch control signal and the second switch control signal may have complementary voltage levels.

The switch control signal generator comprises: an oscillator for generating the square wave having the predetermined frequency; And a dead time unit configured to output the first switch control signal and the second switch control signal having a voltage level complementary to the first switch control signal based on the square wave generated by the oscillator.

Each of the at least one charge pump may include: an output voltage controller configured to output an output voltage control signal based on the second switch control signal and a feedback signal fed back from the corresponding output terminal; And a second switch configured to output a voltage charged in the common capacitor to a corresponding output terminal among the plurality of output terminals in response to the output voltage control signal.

The output voltage controller divides the voltage of the corresponding output terminal and outputs the divided voltage as the feedback signal, compares the feedback signal with the reference voltage, and performs a logical operation between the comparison result and the second switch control signal. An output voltage control block for performing; And a switch driver converting the output signal output from the output voltage control block into a voltage level for driving the second switch and outputting the converted signal as the output voltage control signal.

The output voltage control block may include: a voltage divider for dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A comparator comparing the feedback signal with the reference voltage and outputting a comparison result; And a logic operation unit configured to perform logic operation on the second switch control signal and the output signal of the comparator.

The output voltage controller may include an edge detector configured to detect a first edge of the second switch control signal; A voltage divider for dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A comparator for comparing the feedback signal with a reference voltage; A latch for latching an output signal of the edge detector based on the output signal of the comparator; And a logic operation unit configured to perform a logic operation on an output signal of the latch, the second switch signal, and an output signal of the comparator, and output a logic operation result as the output voltage control signal.

The converter further includes at least one voltage divider located outside the at least one charge pump, for distributing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal. Each of the pumps may include: an output voltage controller configured to output an output voltage control signal based on the second switch control signal and the feedback signal; And a second switch configured to output a voltage charged in the common capacitor to a corresponding output terminal among the plurality of output terminals in response to the output voltage control signal.

According to another aspect of the present invention, there is provided a voltage output method comprising: generating first and second switch control signals based on a square wave having a predetermined frequency; Charging an input voltage to a common capacitor in response to the first switch control signal; And outputting a voltage charged in the common capacitor to a corresponding output terminal among a plurality of output terminals based on the second switch control signal and a feedback signal fed back from a corresponding output terminal among a plurality of output terminals. can do.

The outputting of the corresponding output terminal may include: dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A logic operation step of comparing the feedback signal with a reference voltage and performing a logic operation between the comparison result and the second switch control signal; And controlling the voltage level transmitted from the common capacitor to the corresponding output terminal based on the logic operation result of the logic operation step.

The first switch control signal and the second switch control signal may have complementary voltage levels.

The outputting of the corresponding output terminal may include: an edge detection step of detecting a first edge of the second switch control signal; Dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A latch step of comparing the feedback signal with a reference voltage and latching an edge detection signal by the edge detection step based on a comparison result; A logic operation step of performing a logic operation on an output signal of the latch step, the second switch signal, and an output signal of the comparator; And controlling the voltage level transmitted from the common capacitor to the corresponding output terminal based on the logic operation result of the logic operation step.

According to an embodiment of the present invention, a converter capable of multi-output using a common capacitor and a voltage output method using the converter can output a plurality of output voltages using one common capacitor, and thus the number of capacitors compared to a general charge pump method. And the number of pins can be reduced.

In addition, in the converter capable of multi-output using a common capacitor according to an embodiment of the present invention and the voltage output method using the converter, all circuits except the common capacitor are configured as one integrated circuit, thereby minimizing area and reducing cost. There is an advantage.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, this is not intended to limit the embodiments in accordance with the concept of the present invention to a particular disclosed form, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is implemented, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and, unless expressly defined herein, in ideal or overly formal meanings. It doesn't work.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram of a converter 10 according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the converter 10 according to an embodiment of the present invention. 3 is a circuit diagram of the switch control signal generator 20 of FIG. 2, and FIG. 4 is a circuit diagram of the output voltage controller 21 of FIG. 2 according to the first embodiment of the present invention.

1 to 4, the converter 10 may include a common capacitor Cin and an output unit 70. The common capacitor Cin may charge and discharge the input voltage Vin.

The output unit 70 charges the input voltage Vin to the common capacitor Cin and outputs the charged voltage through the plurality of output terminals out1 through outn based on at least one reference voltage Vrf. can do.

The output unit 70 may include a switch control signal generator 20, a first switch 11, and at least one charge pump 71 to 7n. The switch control signal generator 20 may generate the first and second switch control signals S1 and S2 based on the square wave S0 having a predetermined frequency.

At this time, each of the switch control signal generator 20, the first switch 11, and the at least one charge pump 71 to 7n constituting the output unit 70 are composed of one integrated circuit, thereby minimizing the area and cost. There is an advantage to reduce.

Here, the switch control signal generation unit 20 may output the first switch control signal (S1) and the second switch control signal (S2) having a voltage level complementary to each other, preferably, the switch control signal generation The unit 20 outputs a square wave S0 having a predetermined frequency as a second switch control signal S2 and controls a signal having a voltage level complementary to that of the second switch control signal S2. It can output as signal S1.

Alternatively, the switch control signal generator 20 outputs a signal obtained by delaying and shortening the square wave S0 having a predetermined frequency as a second switch control signal S2 as shown in FIG. S2) may output a signal having a voltage level complementary to the delayed and shortened signal as the first switch control signal S1.

The switch control signal generator 20 may include an oscillator 20-1, a dead time unit 20-2, and a first switch driver 20-3 as shown in FIG. 3. The oscillator 20-1 generates a square wave S0 having a predetermined frequency, and the dead time unit 20-2 generates a second wave based on the square wave S0 generated by the oscillator 20-1. The switch control signal S2 and the signal / S2 having a voltage level complementary to the second switch control signal S2 may be output.

The first switch driver 20-3 receives the signal / S2 having a voltage level complementary to the second switch control signal S2 and drives the first switch 11 with the received signal / S2. The first switch control signal S1 converted to the voltage level for the output may be output.

Referring back to FIG. 2, the first switch 11 may charge or discharge the input voltage Vin to the common capacitor Cin in response to the first switch control signal S1. ) May be implemented with a PMOS transistor.

Each of the at least one charge pump 71 to 7n may output a voltage charged in the common capacitor Cin to a corresponding output terminal among the plurality of output terminals out1 to outn.

Each of the at least one charge pump 71 to 7n may correspond to the second switch control signal S2 based on the feedback signal fed back from a corresponding output terminal among the plurality of output terminals out1 to outn. The level of the output voltage output to the output terminal can be controlled or adjusted.

More specifically, each of the at least one charge pump 71 to 7n is fed back from a corresponding output terminal (eg, the first output terminal out1) among the first to nth output terminals out1 to outn. The level of the output voltage output to the first output terminal out1 may be controlled based on the signal Vf and the second switch control signal S2.

For example, the first charge pump 71 is a voltage transmitted to the first output terminal out1 based on the second switch control signal S2 and the first feedback signal Vf fed back from the first output terminal out1. You can control or adjust the level.

The first charge pump 71 may include an output voltage controller 21 and a second switch 12. The output voltage controller 21 may output the output voltage control signal S3 based on the second switch control signal S2 and the first feedback signal Vf fed back from the first output terminal out1.

The output voltage controller 21 may include an output voltage control block 32 and a second switch driver 32 as shown in FIG. 4. The output voltage control block 32 divides a voltage of a corresponding output terminal (for example, the first output terminal out1) among the plurality of output terminals out1 to outn and converts the divided voltage into a feedback signal (eg, a first signal). The first feedback signal Vf may be output as a first feedback signal Vf and the reference voltage Vrf may be compared with the first feedback signal Vf.

Subsequently, the output voltage control block 32 may perform a logical operation (eg, an AND operation) between the comparison result and the second switch control signal S2.

The output voltage control block 32 may include a voltage divider 35, a comparator 34, and a logic operator 33. The voltage divider 35 divides a voltage of a corresponding output terminal (for example, the first output terminal out1) among the plurality of output terminals out1 through outn and converts the divided voltage into a feedback signal (eg, a first signal). Output signal Vf).

For example, the voltage divider 35 may divide the voltage of the first output terminal out1 using at least two resistors R1 to R2 and output the divided voltage as the first feedback signal Vf.

The comparator 34 may compare the feedback signal (eg, the first feedback signal Vf) with the reference voltage Vrf and output a comparison result. For example, the comparator 34 may output a comparison result of a first logic level (eg, a high ('1') level) when the voltage level of the first feedback signal Vf is greater than the reference voltage Vrf. Can be.

Alternatively, the comparator 34 may output a comparison result of a second logic level (eg, a low level '0') when the voltage level of the first feedback signal Vf is smaller than the reference voltage Vrf. have.

The logic operator 33 may perform a logic operation (eg, an AND operation) between the second switch control signal S2 and the output signal of the comparator 34.

The second switch driver 31 converts the output signal output from the output voltage control block 32 to the voltage level for driving the second switch 12 and outputs the converted signal as the output voltage control signal S3. Can be.

The second switch 12 corresponds to an output terminal (for example, a first output terminal) among the plurality of output terminals out1 to outn for the voltage charged in the common capacitor Cin in response to the output voltage control signal S3. (out1)), wherein the second switch 12 may be implemented as a PMOS transistor.

The configuration and operation of each of the second to nth charge pumps 72 to 7n are the same as or similar to the configuration and operation of the first charge pump 71, and thus a detailed description thereof will be omitted.

On the other hand, each of the first to nth charge pumps 71 to 7n may control the voltage level of the corresponding output terminal among the plurality of output terminals out1 to outn based on different reference voltages.

For example, each of the first to nth charge pumps 71 to 7n outputs different output voltages based on different reference voltages, such that an electronic device (eg, a mobile phone (100 in FIG. 8)) in which the converter 10 is implemented. A voltage required for each component (eg, the base band 121 or the speaker 125) may be supplied.

In addition, each of the first to nth charge pumps 71 to 7n compares the distribution voltage and the reference voltage distributed by the resistors having different resistance values (for example, (R1 to R2)) and based on the comparison result. The voltage level of the corresponding output terminal may be controlled among the plurality of output terminals out1 through outn. For example, resistance values implemented in the output voltage controllers 21 and 22 constituting each of the first charge pump 71 and the second charge pump 72 may be different.

Meanwhile, the first output voltage controller 21 may be implemented in another embodiment as shown in FIG. 5. 5 is a circuit diagram of the first output voltage controller 21 of FIG. 2 according to the second embodiment of the present invention. 1 to 3, 5, and 6, the first output voltage controller 21 includes an edge detector 41, a voltage divider 42, a comparator 43, and a first and second inverters ( 44 and 45, a latch 46, and a logic calculator 47.

The edge detector 41 may detect a first edge (eg, a falling edge) of the second switch control signal S2. For example, the edge detector 41 may have a first logic level (eg, high (') for a predetermined time (eg, 50 ns) at a first edge (eg, a falling edge, “t4” time point) of the second switch control signal S2. 1 ') level), the detection signal (FS in FIG. 6) can be output.

The edge detector 41 includes the first and second switches 51 and 52, the third resistor R3, the third to sixth inverters 53 to 56, the logic operation unit 57, and the seventh inverter 58. It may include.

The first switch 51 is connected between the first power supply voltage Vcc and the first node N1, and in response to the second switch control signal S2, the first power supply voltage Vcc and the first node. It is possible to form an electrical path between (N1).

The second switch 52 is connected between the second node N2 and the second power supply voltage gnd (eg, the ground voltage), and responds to the second switch control signal S2 to the second power supply voltage gnd. And an electrical path between the second node N2.

The third resistor R3 may be connected between the first node N1 and the second node N2, and the capacitor C1 may be connected between the second node N2 and the second power supply voltage gnd. .

The third inverter 53 may receive and invert the second switch control signal S2, and the fourth inverter 54 may receive and invert the output signal of the fourth inverter 53.

The fifth inverter 55 may receive and invert the voltage of the second node N2, and the sixth inverter 56 may receive and invert the output signal of the fifth inverter 55.

The logic operation unit 57 may perform a logic operation (eg, an OR operation) between the output signal of the fourth inverter 54 and the sixth inverter 56, and the seventh inverter 58 may perform the logic operation unit 57. ) Can receive and invert output signals.

The voltage divider 42 divides the voltage of the corresponding output terminal (eg, the first output terminal out1) among the plurality of output terminals out1 through outn and converts the divided voltage into a feedback signal (eg, the first signal). Output signal Vf).

For example, the voltage divider 42 divides the voltage of the first output terminal out1 by using the first and second resistors R1 and R2 and divides the resistance divided voltage into a feedback signal (for example, the first feedback signal). (Vf)).

The comparator 43 may compare the feedback signal (eg, the first feedback signal Vf) with the reference voltage Vrf and output a comparison result. For example, when the voltage level of the first feedback signal Vf is greater than the reference voltage Vrf, the comparator 43 may output a comparison result of the first logic level (eg, a high ('1') level). have.

Alternatively, the comparator 43 may output a comparison result of a second logic level (eg, low level '0') when the voltage level of the first feedback signal Vf is smaller than the reference voltage Vrf. have.

The latch 46 may latch the output signal FS of the edge detector 41 based on the output signal FR of the comparator 43. The latch 46 may be implemented as an SR latch implemented with first and second NOR gates.

The logic operation unit 47 performs a logical operation (eg, an OR operation) with the output signal Q of the latch 46, the second switch signal S2, and the output signal FR of the comparator 43, and performs a logical operation. The result can be output as the output voltage control signal S3.

FIG. 6 is a timing diagram for describing an operation of the converter of FIG. 2. 1 to 3, 5, and 6, the operation of the converter 10 will be described in detail as follows.

Oscillator 20-1 has a first logic level (eg, a high ('1') level) at " t1 " and a second logic level (eg, a low ('0') level) at " t6 ". Square wave SO can be generated.

The dead time unit 20-2 may output a second switch control signal S 2 to a signal obtained by delaying and shortening the square wave S 0 based on the square wave S 0 generated by the oscillator 20-1. . For example, the dead time unit 20-2 has a first logic level (eg, a high ('1') level) at "t2" and a second logic level (eg, a low ('0') at "t4". Second switch control signal S2 having a level) can be output.

In addition, the dead time unit 20-2 may output a signal having a voltage level complementary to that of the delayed and shortened signal of the second switch control signal S2 as the first switch control signal S1. For example, the dead time unit 20-2 has a second logic level (eg, a low ('0') level) at "t3" and a first logic level (eg, high ('1') at "t5". The first switch control signal S1 having the level of?) May be output.

The edge detector 41 detects the first edge (eg, falling edge, " t4 " time) of the second switch control signal S2, and detects the first logic level (eg, high (for example, 50 ns) for a predetermined time (eg, 50 ns). Detection signal FS having a '1' level) can be output.

The comparator 43 may compare the feedback signal (eg, the first feedback signal Vf) with the reference voltage Vrf and output a comparison result FR. For example, when the voltage level of the first feedback signal Vf is greater than the reference voltage Vrf ("t4" time point), the comparator 43 has a first logic level (eg, a high ('1') level). You can output the comparison result of (FR).

The latch 46 may latch the output signal FS of the edge detector 41 based on the output signal FR of the comparator 43. For example, the latch 46 has the edge detector 41 at " t4 " when the output signal FR of the comparator 43 has a first logic level (eg, a high ('1') level) at " t4 ". The detection signal FS may be latched and the result Q may be output.

The logic calculator 47 performs a logic operation (eg, an OR operation) with the output signal Q of the latch 46, the second switch signal S2, and the output signal R of the comparator 43, and performs a logic operation. The result can be output as the output voltage control signal S3. That is, in FIG. 6, the output voltage control signal S3 has a first logic level (eg, a high ('1') level) at "t2", and the second switch 12 is turned off from "t2". Can be maintained.

7 is a circuit diagram of a converter according to another embodiment of the present invention. Referring to FIG. 7, the converter 10 ′ of FIG. 7 has a different output voltage control unit than the converter 10 of FIG. 2. More specifically, the output voltage controller (for example, the first output voltage controller 61) implemented in the converter 10 ′ of FIG. 7 may include a voltage divider (32 of FIG. 4) implemented in the converter 10 of FIG. 2. ) Is not included.

That is, the voltage divider (eg, the first voltage divider 62) of the converter 10 ′ of FIG. 7 as compared to the voltage divider 32 (FIG. 4) implemented in the converter 10 of FIG. 2 is output. Located outside the portion 70 '.

The output voltage of the first voltage divider 62 is a feedback signal of the output terminal (for example, out1) to be compared with the reference voltage Vrf, and the output voltage of the first voltage divider 62 is an output unit ( 70 ') is adjustable outside.

That is, the converter 10 ′ according to another embodiment of the present invention may reduce the chip size by placing the voltage divider (eg, the first voltage divider 62) outside the output unit 70 ′, The output voltage of the first voltage divider 62 may be adjusted outside the output unit 70 ′, thereby outputting a desired output voltage.

8 is a block diagram of an electronic device including the converter 10 according to an exemplary embodiment of the present invention. 2 and 8, the electronic device 100 (eg, a mobile phone, an MP3, a camera, or a PDA, etc.) may include a power supply unit (or a battery pack 110) and an electronic device main body 120. .

The power supply unit 110 may receive a power supply voltage and charge the received voltage. The main body 120 of the electronic device 120 includes a power management IC 115 and a base band block 121 for performing an intrinsic function of the electronic device (eg, a call function, a recording function, and a video playback function). 122, Rx 123, Back light 124, Speaker 125, and Motor 126.

The power control IC 115 may include the converter 10 of FIG. 1 or 7, and adjusts the power supply voltage level supplied from the power supply unit 110 to control each block (eg, Base) of the electronic device main body 120. band block 121, Tx 122, Rx 123, Back light 124, Speaker 125, and Motor 126.

9 is a flowchart illustrating a voltage output method of a converter according to an exemplary embodiment of the present invention. 2, 4, and 9, the switch control signal generator 20 generates the first and second switch control signals S1 and S2 based on a square wave S0 having a predetermined frequency. In operation S10, the first switch 11 charges the input voltage Vin to the common capacitor Cin in response to the first switch control signal S1 (S12).

The charge pump 71 divides a voltage of a corresponding output terminal (for example, out1) among the plurality of output terminals out1 to outn, outputs the divided voltage as a feedback signal Vf (S14), and the feedback signal. (Vf) and the reference voltage (Vrf) are compared and a logical operation of the comparison result and the second switch control signal (S2) is performed (S16).

Subsequently, the charge pump 71 controls the voltage level transmitted from the common capacitor Cin to the corresponding output terminal (eg, out1) based on the logic operation result of the step S16 (S18).

9 is a flowchart illustrating a voltage output method of a converter according to an exemplary embodiment of the present invention. 2, 5, and 9, the switch control signal generator 20 generates the first and second switch control signals S1 and S2 based on the square wave S0 having a predetermined frequency. In operation S20, the first switch 11 charges the input voltage Vin to the common capacitor Cin in response to the first switch control signal S1 (S24).

The edge detector 41 detects the first edge of the second switch control signal S2 (S26), and the voltage divider 42 outputs a corresponding output terminal (eg, a plurality of output terminals out1 through outn). The voltage of out1) is distributed and the divided voltage is output as the feedback signal Vf (S28).

The comparator 43 compares the feedback signal Vf with the reference voltage Vrf and latches the edge detection signal by S28 based on the comparison result (S30), and the logic calculating unit 47 outputs the output signal by the step S30, The logical operation of the second switch signal S2 and the output signal of the comparator 43 is performed (S32).

The second switch 12 controls the voltage level transmitted from the common capacitor (Cin) to the corresponding output terminal based on the logic operation result of step S32 (S34).

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to more fully understand the drawings recited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a conceptual diagram of a converter according to an embodiment of the present invention.

2 is a circuit diagram of a converter according to an embodiment of the present invention.

3 is a circuit diagram of the switch control signal generator of FIG. 2.

4 is a circuit diagram of the output voltage controller of FIG. 2 according to the first embodiment of the present invention.

5 is a circuit diagram of an output voltage controller of FIG. 2 according to a second exemplary embodiment of the present invention.

FIG. 6 is a timing diagram for describing an operation of the converter of FIG. 2.

7 is a circuit diagram of a converter according to another embodiment of the present invention.

8 is a block diagram of an electronic device including a converter according to an embodiment of the present disclosure.

9 is a flowchart illustrating a voltage output method of a converter according to an exemplary embodiment of the present invention.

10 is a flowchart illustrating a voltage output method of a converter according to another embodiment of the present invention.

Claims (13)

A common capacitor charging and discharging the input voltage; And And an output unit configured to charge the input voltage to the common capacitor and to output the charged voltage through a plurality of output terminals based on at least one reference voltage. The method of claim 1, wherein the output unit, A switch control signal generator for generating first and second switch control signals based on square waves having a predetermined frequency; A first switch configured to charge the input voltage to the common capacitor in response to the first switch control signal; And At least one charge pump for outputting a voltage charged in the common capacitor to a corresponding output terminal of the plurality of output terminals, each of the at least one charge pump, And a control unit configured to control a level of an output voltage output to the corresponding output terminal based on the feedback signal returned from a corresponding output terminal among the second switch control signal and the plurality of output terminals. The method of claim 2, wherein the first switch control signal and the second switch control signal, Converters with voltage levels complementary to each other. The method of claim 2, wherein the switch control signal generator, An oscillator for generating the square wave having the predetermined frequency; And And a dead time unit configured to output the first switch control signal and the second switch control signal having a voltage level complementary to the first switch control signal based on the square wave generated by the oscillator. The method of claim 2, wherein each of the at least one charge pump, An output voltage controller configured to output an output voltage control signal based on the second switch control signal and a feedback signal fed back from the corresponding output terminal; And And a second switch configured to output a voltage charged in the common capacitor to a corresponding output terminal among the plurality of output terminals in response to the output voltage control signal. The method of claim 5, wherein the output voltage control unit, Output voltage control for distributing the voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal, comparing the feedback signal with the reference voltage, and performing a logical operation between the comparison result and the second switch control signal. block; And And a switch driver converting an output signal output from the output voltage control block into a voltage level for driving the second switch and outputting the converted signal as the output voltage control signal. The method of claim 6, wherein the output voltage control block, A voltage divider for dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A comparator comparing the feedback signal with the reference voltage and outputting a comparison result; And And a logic calculator configured to perform a logic operation on the second switch control signal and an output signal of the comparator. The method of claim 5, wherein the output voltage control unit, An edge detector detecting a first edge of the second switch control signal; A voltage divider for dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A comparator for comparing the feedback signal with a reference voltage; A latch for latching an output signal of the edge detector based on the output signal of the comparator; And And a logic calculator configured to perform a logic operation on the output signal of the latch, the second switch signal, and an output signal of the comparator, and output a logic operation result as the output voltage control signal. The method of claim 2, wherein the converter, Located at the outside of the at least one charge pump, further comprising at least one voltage divider for distributing the voltage of the corresponding output terminal and outputs the divided voltage as the feedback signal, Each of the at least one charge pump, An output voltage controller configured to output an output voltage control signal based on the second switch control signal and the feedback signal; And And a second switch configured to output a voltage charged in the common capacitor to a corresponding output terminal among the plurality of output terminals in response to the output voltage control signal. Generating first and second switch control signals based on square waves having a predetermined frequency; Charging an input voltage to a common capacitor in response to the first switch control signal; And Outputting a voltage charged in the common capacitor to a corresponding output terminal among a plurality of output terminals based on the second switch control signal and a feedback signal fed back from a corresponding output terminal among a plurality of output terminals; Voltage output method. The method of claim 10, wherein the outputting to the corresponding output terminal, Dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A logic operation step of comparing the feedback signal with a reference voltage and performing a logic operation between the comparison result and the second switch control signal; And And controlling the voltage level transmitted from the common capacitor to the corresponding output terminal based on the logic operation result of the logic operation step. The method of claim 10, wherein the first switch control signal and the second switch control signal, A voltage output method having voltage levels complementary to each other. The method of claim 10, wherein the outputting to the corresponding output terminal, An edge detection step of detecting a first edge of the second switch control signal; Dividing a voltage of the corresponding output terminal and outputting the divided voltage as the feedback signal; A latch step of comparing the feedback signal with a reference voltage and latching an edge detection signal by the edge detection step based on a comparison result; A logic operation step of performing a logic operation on an output signal of the latch step, the second switch signal, and an output signal of the comparator; And And controlling the voltage level transmitted from the common capacitor to the corresponding output terminal based on the logic operation result of the logic operation step.

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