JP6498524B2 - Power supply circuit and electronic equipment - Google Patents

Description

  The present invention relates to a power supply circuit.

  A power circuit is used to convert one voltage to another voltage level and stabilize it. The power supply circuit is roughly divided into a linear regulator and a switching regulator. Switching regulators have high efficiency at heavy loads, but efficiency decreases due to switching losses at light loads. On the other hand, the linear regulator has high efficiency at light load, but at heavy load, the loss due to the on-resistance of the output transistor increases and the efficiency decreases.

  In order to obtain high efficiency in a wide current range, a linear regulator and a switching regulator may be used in combination. FIG. 1 is a circuit diagram of a power supply circuit investigated by the present inventors.

The power supply circuit 100r includes a linear regulator 200 and a switching regulator 300 in which inputs and outputs are connected in common. One of the linear regulator 200 and the switching regulator 300 is enabled and the other is disabled based on the state of the load or the input voltage _VIN .

JP 2008-305387 A JP 2008-61452 A JP 2005-130622 A JP 2014-128038 A

In such a power supply circuit 100r, there is a problem that the output voltage _VOUT overshoots and undershoots when the linear regulator 200 and the switching regulator 300 are switched. In addition, after the output voltage V _OUT deviates from the target voltage, there is a problem that it takes a long time to be stabilized to the original target voltage.

The present invention has been made in view of these problems, and one exemplary object of one aspect thereof is to provide a power supply circuit that can suppress fluctuations in the output voltage _VOUT when switching between a linear regulator and a switching regulator. is there.

  One embodiment of the present invention relates to a power supply circuit. The power supply circuit can be switched between the enable state / disable state, receives the input voltage of the input line, and stabilizes the output voltage of the output line to a predetermined target voltage in the enable state, and the enable state / disable state A switching regulator that receives the input voltage of the input line and stabilizes the output voltage of the output line to the target voltage in the enable state, and a controller that switches the enable state / disable state of each of the linear regulator and the switching regulator . The switching regulator can be switched between an enable state and a disable state, receives a reference voltage at the non-inverting input terminal, receives a feedback signal corresponding to the output voltage at the inverting input terminal, and an error between the reference voltage and the feedback signal in the enabled state. An error amplifier that outputs an error signal, a switch provided between the output terminal and the inverting input terminal of the error amplifier, a slope generator that generates a slope signal having a baseline corresponding to a reference voltage, A pulse modulator that generates a pulse signal that is pulse-modulated based on the error signal and the slope signal; and a driver that switches a switching transistor in accordance with the pulse signal. When switching from the linear regulator enable state to the switching regulator enable state, the controller inserts an overlap period, maintains the linear regulator enable state during the overlap period, enables the error amplifier, and turns on the switch. And the switching of the switching transistor by the driver is stopped.

  In the overlap period, when the switch is turned on, the error amplifier functions as a voltage follower. Therefore, the error signal that is the output of the error amplifier becomes equal to the reference voltage. In addition, by setting the baseline of the slope signal generated by the slope generator based on the reference voltage, the duty ratio of the pulse signal generated during the overlap period can be brought close to that of the switching regulator enabled state. it can. By switching the switching regulator to the enable state after the overlap period ends, the switching regulator switches at an optimum duty ratio, so that overshoot and undershoot of the output voltage can be suppressed.

  The pulse modulator includes an oscillator that generates a periodic signal having a predetermined period, a pulse width modulation comparator that compares the error signal and the slope signal, and generates a reset signal indicating the comparison result, and the period signal and the reset signal. And a logic circuit that generates a pulse signal whose level changes.

  The slope generator may include a capacitor, a current source that charges the capacitor, a discharge switch that discharges the capacitor, and a level shift circuit that combines a ramp voltage generated in the capacitor with a reference voltage to generate a slope signal. .

  The level shift circuit may include an analog adder.

The baseline of the slope signal may be a level that is a predetermined offset width and lowered from the reference voltage.
By optimizing the offset width, overshoot and undershoot can be further suppressed over a wide input voltage range.

  The slope generator includes a capacitor, a current source for charging the capacitor, a discharge switch for discharging the capacitor, an offset voltage generation circuit for generating an offset voltage corresponding to the offset width, and a ramp voltage generated in the capacitor as a reference voltage and an offset. And a level shift circuit that generates a slope signal by combining with the voltage.

  The level shift circuit may include an analog adder / subtracter that adds a reference voltage to a ramp voltage and subtracts an offset voltage.

  The level shift circuit includes a first bipolar transistor receiving a ramp voltage at a base, a first current source connected to the first bipolar transistor, a second bipolar transistor of the same type as the first bipolar transistor connected to the base collector, A resistor connected in series with the second bipolar transistor, a second current source for supplying current to the series connection of the second bipolar transistor and the resistor, an emitter voltage and a reference voltage of the first bipolar transistor are added, and a second And an analog adder / subtracter for subtracting the emitter voltage of the bipolar transistor.

The power supply circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. In one aspect, the main part excluding the inductor and the smoothing capacitor of the switching regulator may be integrated in the power supply circuit.

  Another embodiment of the present invention relates to an electronic device. The electronic apparatus may include a battery, at least one load, and any one of the above-described power supply circuits that receives the voltage of the battery and supplies a power supply voltage to the at least one load.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to suppress fluctuations in the output voltage when switching from a linear regulator to a switching regulator.

It is a circuit diagram of the power supply circuit which the present inventors examined. It is a circuit diagram which shows the power supply circuit which concerns on embodiment. It is a circuit diagram which shows the structural example of a pulse modulator. It is a circuit diagram which shows the structural example of a slope generator. It is a time chart of the power supply circuit of FIG. FIG. 3 is an operation waveform diagram in the overlap period of the power supply circuit of FIG. 2. 7A and 7B are a block diagram and an external view of an electronic apparatus including the power supply circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

FIG. 2 is a circuit diagram showing the power supply circuit 100 according to the embodiment. The power supply circuit 100 receives an input voltage _VIN on an input line 102 (input terminal), and an output voltage V stabilized at a predetermined target voltage on a load (not shown) connected to the output line 104 (output terminal). _OUT is supplied. The input voltage _VIN may be a battery voltage from a battery (not shown) or may be a voltage from an AC / DC converter (not shown) or supplied from a bus such as a USB (Universal Serial Bus). It may be a bus voltage.

The power supply circuit 100 includes a linear regulator 200, a switching regulator 300, and a controller 402. The linear regulator 200 can be switched between an enable state and a disable state, receives the input voltage _VIN of the input line 102, and stabilizes the output voltage _VOUT of the output line 104 to a target voltage in the enabled state.

  The linear regulator 200 is also referred to as LDO (Low Drop Output), and includes an output transistor M1, a first error amplifier EA1, resistors R11 and R12, and an output capacitor (smoothing capacitor) C1. The output transistor M1 is a P-channel MOSFET (or PNP-type bipolar transistor), and is provided between the input line 102 and the output line 104. The output transistor M1 may be composed of an N channel MOSFET or an NPN bipolar transistor.

The resistors R11 and R12 divide the output voltage _VOUT by a predetermined voltage dividing ratio R12 / (R11 + R12) to generate the first feedback signal _VFB1 . The first error amplifier EA1 amplifies an error between the predetermined reference voltage _VREF1 and the first feedback signal _VFB1 , and supplies the amplified error to the gate (base) of the output transistor M1.

In the enabled state, the linear regulator 200 stabilizes the output voltage _VOUT of the output line 104 to the following target voltage.
V _OUT = V _REF1 × (R11 + R12) / R12

  The enable / disable state of the linear regulator 200 corresponds to the enable / disable state of the first error amplifier EA1. The state of the first error amplifier EA1 is switched according to the control signal EN11 generated by the controller 402.

  The disabled states of the first error amplifier EA1, the second error amplifier EA2 and the pulse modulator 320 described later can be realized by cutting off their bias currents or stopping the supply of the power supply voltage to them. That is, it can be understood that the disabled state is a state in which power consumption is substantially zero.

Similarly to the linear regulator 200, the switching regulator 300 can be switched between an enable state and a disable state. The switching regulator 300 receives the input voltage _VIN of the input line 102, and stabilizes the output voltage _VOUT of the output line 104 to the target voltage in the enabled state. The switching regulator 300 is a step-down DC / DC converter (Buck converter).

  The switching regulator 300 includes a switching transistor M2, a rectifying element D1, an inductor L1, an output capacitor C1, resistors R21 and R22, and a converter controller 302 that controls the switching transistor M2.

  The controller 402 switches the enable / disable states of the linear regulator 200 and the switching regulator 300 and controls the internal circuit of the switching regulator 300.

  The converter controller 302 of the switching regulator 300 mainly includes a second error amplifier EA2, a slope generator 310, a pulse modulator 320, and a driver 330.

The second error amplifier EA2 can be switched between an enable state and a disable state. The second error amplifier EA2 receives the reference voltage _VREF2 at the non-inverting input terminal (+) and the second error amplifier EA2 according to the output voltage _VOUT at the inverting input terminal (−). Receives feedback signal V _FB2 . The resistors R21 and R22 divide the output voltage _VOUT and generate a second feedback signal _VFB2 . The reference voltage V _REF2 may be the same as or different from V _REF1 . If they are the same, the pair of resistors R21 and R22 may be omitted and the first feedback signal _VFB1 may be used as the second feedback signal _VFB2 .

The second error amplifier EA2 amplifies the error of the reference voltage _{V REF2} and the feedback signal _{V FB2} in the enable state, and outputs an error signal _{V ERR.} A phase compensation capacitor or resistor is inserted between the inverting input terminal (−) of the second error amplifier EA2 and the output. The state of the second error amplifier EA2 is switched based on the control signal EN21 generated by the controller 402.

  The switch SW1 is provided between the output terminal of the second error amplifier EA2 and the inverting input terminal (−). ON / OFF of the switch SW1 is controlled by a control signal CNT21 generated by the controller 402. For example, the switch SW1 can be composed of an NMOS switch or a transfer gate, and is turned on when the control signal CNT21 is at a high level.

Slope generator 310 receives a reference voltage _{V REF2,} and generates a slope signal _{V SLOPE} having a baseline corresponding to the reference voltage _{V REF2.} The slope generator 310 is also preferably switchable between the enable state and the disable state, and is switched based on the control signal EN22 generated by the controller 402.

The pulse modulator 320 generates a pulse-modulated pulse signal S _PWM based on the error signal V _ERR and the slope signal V _SLOPE . For example, the pulse modulator 320 generates a pulse signal S _PWM subjected to pulse width modulation (PWM) whose period is constant and whose pulse width changes. It is preferable that the pulse modulator 320 can be switched between the enable state / disable state, and in this case, the pulse modulator 320 is switched based on the control signal EN23 generated by the controller 402.

The driver 330 switches the switching transistor M2 of the switching regulator 300 according to the pulse signal _SPWM . In response to the control signal CNT22, the driver 330 can switch between an operation state in which the switching transistor M2 is switched and a stop state in which the switching of the switching transistor M2 is stopped. For example the driver 330, a pulse signal _{S PWM} control signal CNT22 a logic operation, a pulse signal _{S PWM} may be masked.

  In the enable state of the switching regulator 300, the controller 402 enables all of the second error amplifier EA2, the slope generator 310, and the pulse modulator 320, and turns off the switch SW1. On the contrary, in the disabled state of the switching regulator 300, the second error amplifier EA2, the slope generator 310, and the pulse modulator 320 are disabled, thereby reducing power consumption.

  The controller 402 inserts an overlap period τ when switching from the enabled state of the linear regulator 200 (disabled state of the switching regulator 300) to the enabled state of the switching regulator 300 (disabled state of the linear regulator 200). In the overlap period τ, the controller 402 maintains the linear regulator 200 in the enabled state, turns on the second error amplifier EA2, and turns on the switch SW1. Further, the switching of the switching transistor M2 by the driver 330 is stopped.

  In the present embodiment, the main parts (the linear regulator 200, the converter controller 302, and the controller 402) of the power supply circuit 100 are integrated on a single semiconductor substrate. In FIG. 2, circuit elements other than external circuit components (L 1, C 1, R 21, R 22) in the power supply circuit 100 are integrated in a power supply IC (Integrated Circuit) 400.

  The above is the overall configuration of the power supply circuit 100. The present invention includes various modes of circuits grasped in the block diagram of FIG. 2, and specific examples of the configuration will be described below.

FIG. 3 is a circuit diagram showing a configuration example of the pulse modulator 320. The pulse modulator 320 includes an oscillator 322, a PWM (pulse width modulation) comparator 324, and a logic circuit 326. Oscillator 322 generates a periodic signal _{S OCS} having a predetermined period _{T P.} PWM comparator 324 compares the error signal _{V ERR} and the slope signal _{S SLOPE,} generates a reset signal _{S CMP} indicating the comparison result. The logic circuit 326 generates a pulse signal S _PWM whose level transitions according to the periodic signal S _OSC and the reset signal _SCMP . The logic circuit 326 can be configured by an SR flip-flop, a D flip-flop, or the like. The pulse signal S _PWM becomes an on level (for example, high level) in response to the periodic signal S _OSC , and becomes an off level (low level) in response to the reset signal _SCMP .

  FIG. 4 is a circuit diagram showing a configuration example of the slope generator 310. The slope generator 310 includes a capacitor C21, a current source CS21, a discharge switch SW21, and a level shift circuit (arithmetic circuit) 312.

  One end of the capacitor C21 is grounded. The current source CS21 charges the capacitor C21 with the constant current Ic. The discharge switch SW21 is provided in parallel with the capacitor C21 and discharges the capacitor C21 in the on state.

When the discharge switch SW21 is repeatedly turned on and off, a ramp voltage V _RAMP having the ground voltage (0 V) as a base line is generated in the capacitor C21.

The ramp voltage V _RAMP is input to a source follower circuit including a current source CS31 and a first bipolar transistor Q31. The level shift circuit 312 _combines the ramp voltage V _RAMP ′ having passed through the source follower circuit with the reference voltage V _REF to generate a slope signal V _SLOPE .
V _RAMP '= V _RAMP + V _BE
The level shift circuit 312 includes an analog adder (adder / subtracter) 314. The analog adder / subtractor 314 adds the voltage V _RAMP ′ corresponding to the ramp voltage V _RAMP and the reference voltage V _REF2 ′. The reference voltage V _REF2 ′ is the reference voltage V _REF2 through the buffer 316 and they are equal. If the output impedance of the voltage source that generates the reference voltage V _REF2 is sufficiently low, the buffer 316 can be omitted.

Here, the baseline of the slope signal V _SLOPE has a level that is a predetermined offset width and lower than the reference voltage V _REF2 . The offset voltage generation circuit 318 generates an offset voltage V _OFS corresponding to the offset width. The offset voltage generation circuit 318 includes a second current source CS32 and a resistor R31. When the current generated by the second current source CS32 is Ic, V _OFS = R31 × Ic.

The second bipolar transistor Q32 has a base collector connected and is provided in series with the resistor R31. The voltage V _OFS ′ is input to the addition / subtraction circuit 314.
V _OFS '= V _OFS + V _BE

The addition / subtraction circuit 314 generates the slope voltage V _SLOPE by the following calculation.
V _SLOPE = V _RAMP '+ V _REF ' -V _OFS '
= (V _RAMP + V _BE ) + V _REF − (V _OFS + V _BE )
= V _RAMP + V _REF -V _OFS
In this manner, the addition / subtraction circuit 314 _{combines the} ramp voltage V _RAMP generated in the capacitor C21 with the reference voltage V _REF ′ and the offset voltage V _OFS to generate the slope signal V _SLOPE . The pair of transistors Q31 and Q32 cancels the temperature dependence of the source follower.

Next, the operation of the power supply circuit 100 in FIG. 2 will be described.
FIG. 5 is a time chart of the power supply circuit 100 of FIG. FIG. 5 shows an operation from the enable state of the linear regulator 200 to the enable state of the switching regulator 300. FIG. 5 shows the control of the enable / disable state of each block.

Prior to time t1, the linear regulator 200 is enabled. At time t1, when the controller 402 detects an increase in the load current I _OUT or receives an instruction from an external host processor (not shown), a transition to the switching regulator 300 is started.

Time t1 to t2 is set to the overlap period τ. During the overlap period τ, the control signal EN11 is at a high level level instructing enable, and therefore the enable state (EN) of the linear regulator 200 is maintained. During the overlap period τ, the controller 402 enables the second error amplifier EA2, the slope generator 310, and the pulse modulator 320 to generate the pulse signal _SPWM . At this time, the control signal CNT21 is at a high level and the switch SW1 is in an on state. Since the control signal CNT22 is at a low level, the driver 330 is stopped and the switching transistor M2 is not switched.

  At time t2, the control signal CNT21 becomes low level, the switch SW1 is turned off, and the control signal S22 becomes high level, so that the driver 330 is activated.

FIG. 6 is an operation waveform diagram in the overlap period of the power supply circuit 100 of FIG.
The switch SW1 is turned on at time t1. As a result, the error signal _VERR immediately rises to the reference voltage _VREF2 . Note that the feedback signal V _FB2 does not appear in the error signal V _ERR output from the second error amplifier EA2 simply by the switch SW1, but the second error amplifier EA2 and the switch SW1 operate as a voltage follower. The reference voltage V _{REF2 of} the non-inverting input terminal (+) appears in the error signal V _ERR by feedback. That is, the operating point of the differential amplifier inside the second error amplifier EA2 and the transistor element of the amplification stage is equivalent to the enable state of the switching regulator 300.

When the slope generator 310 is enabled at time t1, the baseline of the slope voltage V _SLOPE rises to the level of V _REF2 −V _OFS , and the ramp voltage V _RAMP is superimposed by charging and discharging of the capacitor C21, and the slope is increased. A voltage V _SLOPE is generated.

The slope voltage V _SLOPE and the error signal V _ERR generated in this way are substantially the same as the waveforms that the switching regulator 300 can take in a steady state. That is, the duty ratio of the pulse signal S _PWM generated in the overlap period is substantially the same as the duty ratio of the switching regulator 300 in the steady state. However, since the driver 330 is in a stopped state, the switching transistor M2 is not switched.

During the overlap period, the output voltage _VOUT is stabilized at a predetermined voltage level by the linear regulator 200 between times t1 and t2. During this overlap period, the slope generator 310, the second error amplifier EA2, and the pulse modulator 320 are operated in the same manner as in the steady state, and at time t2, the switching regulator 300 is enabled, and the linear regulator 200 To disable state. Then, immediately after switching, the pulse modulator 320 can generate a pulse signal _SPWM having an appropriate duty ratio (pulse width), and thus the switching transistor M2 is switched at an appropriate duty ratio.

The above is the operation of the power supply circuit 100.
In the power supply circuit 100, during the overlap period τ, the second error amplifier EA2 that receives the reference voltage V _REF2 is operated as a voltage follower, and the baseline of the slope generator 310 is generated based on the reference voltage V _REF2. It was decided to. As a result, even after time t2 in FIG. 6, undershoot and overshoot of the output voltage _VOUT as shown by the alternate long and short dash line can be suppressed, and the target voltage can be maintained as shown by the solid line.

Further, as shown in FIG. 6, the baseline of the slope signal V _SLOPE is set to a level that is lower than the reference voltage V _REF2 by a predetermined offset width V _OFS . Accordingly, by optimizing the offset width V _OFS , overshoot and undershoot can be appropriately suppressed in a wide input voltage range.

  Next, the application of the power supply circuit 100 will be described. 7A and 7B are a block diagram and an external view of an electronic apparatus 500 including the power supply circuit 100 of FIG. The electronic device 500 is, for example, a mobile phone terminal, a tablet PC, a notebook PC, a desktop PC, a digital camera, a digital video camera, a portable audio device, a portable game device, a stationary game console, a television, or the like.

  7A and 7B exemplarily show a device having a wireless communication function as the electronic apparatus 500. FIG.

  The electronic device 500 includes an antenna 502, a wireless unit (RF unit) 504, a baseband processor 506, an application processor 508, a sound processor 510, an audio output device 512, an audio input device 514, a display device 518, and a user interface device 516.

  The baseband processor 506 and the application processor 508 integrally control the electronic device 500. These may be integrated into one chip.

  The radio unit 504 uses the antenna 502 to perform radio communication with a base station (not shown). More specifically, the wireless unit 504 modulates a baseband signal output from the baseband processor 506, converts it to a high frequency signal, and radiates a radio wave having a transmission frequency from the antenna 502. Radio section 504 demodulates the received signal from the base station received by antenna 502, converts it to a baseband signal, and outputs it to baseband processor 506.

  The user interface device 516 includes a touch panel, a keyboard, and a control IC thereof. Application processor 508 detects user input from user interface device 516.

  The display device 518 includes an LCD (Liquid Crystal Display) or an organic EL (Electro-Luminescence) display and its control IC (Display Driver), and displays the image data generated by the application processor 508.

  The sound processor 510 controls input / output of audio signals. The sound processor 510 converts the audio signal generated by the application processor 508 into an analog signal and outputs the analog signal to an audio output device 512 such as a speaker or headphones. The sound processor 510 converts an analog audio signal input to the audio input device 514 such as a microphone into a digital signal and outputs the digital signal to the application processor 508.

The power supply circuit 100 receives the voltage V _BAT from the battery 2 and supplies power supply voltages V _{DD1 to} V _DD3 to the baseband processor 506, the application processor 508, the sound processor 510, and the like connected as loads.

In such an electronic device 500, the application processor 508 or the baseband processor 506 is grasped as a main processor that integrally controls the entire electronic device 500, and other circuit blocks operate under the control of the main processor. Therefore, the main processor may generate a control signal S _MODE that is asserted in an ultra-light load state, for example, a standby state (including a sleep state and a deep sleep state) of the electronic device 500, and may transmit the control signal S _MODE to the power supply circuit 100. The controller 402 of the power supply circuit 100 switches between the linear regulator 200 and the switching regulator 300 based on the control signal S _MODE .

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

(First modification)
The method for stopping the switching of the driver in the overlap period is not limited thereto. For example, in the pulse modulator 320 in the previous stage of the driver 330, the switching may be stopped by masking the periodic signal S _OSC input to the set terminal of the logic circuit 326.

(Second modification)
Although the diode rectification type DC / DC converter has been described in the embodiment, it can also be applied to a synchronous rectification type.

(Third Modification)
The configuration of the pulse modulator 320 is not limited to that shown in FIG. For example, the oscillator 322 and the logic circuit 326 may be omitted from the pulse modulator 320, and the comparison signal _SCMP that is the output of the PWM comparator 324 may be used as the pulse signal _SPWM . In this case, the slope signal V _SLOPE of the ramp waveform (including the sawtooth wave) is sliced by the error signal V _ERR , and the pulse signal S takes different levels when V _SLOPE > V _ERR and V _SLOPE <V _{ERR. PWM} may be generated. Alternatively, pulse modulator 320 may be in current mode instead of voltage mode.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 2 ... Battery, 100 ... Power supply circuit, 102 ... Input line, 104 ... Output line, 200 ... Linear regulator, M1 ... Output transistor, EA1 ... First error amplifier, R11, R12 ... Resistance, C1 ... Output capacitor, 300 ... Switching Regulator, M2 ... switching transistor, D1 ... rectifier, L1 ... inductor, 302 ... converter controller, EA2 ... second error amplifier, SW1 ... switch, 310 ... slope generator, 312 ... level shift circuit, 320 ... pulse modulator, 322 ... Oscillator, 324 ... PWM comparator, 326 ... Logic circuit, 330 ... Driver, 400 ... Power supply IC, 402 ... Controller, 500 ... Electronic device, 502 ... Antenna, 504 ... Wireless unit, 506 ... Baseband processor, 508 ... Application Deployment processor, 510 ... sound processor, 512 ... audio output device, 514 ... audio input device, 516 ... user interface device, 518 ... display device.

Claims (10)

A linear regulator that can be switched between an enable state and a disable state, receives an input voltage of the input line, and stabilizes the output voltage of the output line at a predetermined target voltage in the enable state;
A switching regulator that is switchable between an enable state and a disable state, receives the input voltage of the input line, and stabilizes the output voltage of the output line to the target voltage in the enable state;
A controller that switches between the enable state and the disable state of each of the linear regulator and the switching regulator;
With
The switching regulator is
The enable state / disable state can be switched, a reference voltage is received at the non-inverting input terminal, a feedback signal corresponding to the output voltage is received at the inverting input terminal, and an error between the reference voltage and the feedback signal in the enabled state An error amplifier that amplifies and outputs an error signal;
A switch provided between the output terminal of the error amplifier and the inverting input terminal;
A slope generator for generating a slope signal having a baseline according to the reference voltage;
A pulse modulator for generating a pulse-modulated pulse signal based on the error signal and the slope signal;
A driver that switches a switching transistor of the switching regulator in response to the pulse signal;
With
The controller inserts an overlap period when switching from the enable state of the linear regulator to the enable state of the switching regulator, and maintains the linear regulator in the enable state during the overlap period. A power supply circuit comprising: an enable state; turning on the switch; and stopping switching of the switching transistor by the driver. The pulse modulator is
An oscillator that generates a periodic signal having a predetermined period;
A pulse width modulation comparator that compares the error signal with the slope signal and generates a reset signal indicating a comparison result;
A logic circuit that generates the pulse signal whose level changes according to the periodic signal and the reset signal;
The power supply circuit according to claim 1, comprising: The slope generator is
A capacitor;
A current source for charging the capacitor;
A discharge switch for discharging the capacitor;
A level shift circuit that combines the ramp voltage generated in the capacitor with the reference voltage to generate the slope signal;
The power supply circuit according to claim 1, comprising:   The power supply circuit according to claim 3, wherein the level shift circuit includes an analog adder.   5. The power supply circuit according to claim 1, wherein the baseline of the slope signal has a level that is lower than the reference voltage by a predetermined offset width. 6. The slope generator is
A capacitor;
A current source for charging the capacitor;
A discharge switch for discharging the capacitor;
An offset voltage generation circuit for generating an offset voltage corresponding to the offset width;
A level shift circuit that combines the ramp voltage generated in the capacitor with the reference voltage and the offset voltage to generate the slope signal;
The power supply circuit according to claim 5, comprising:   The power supply circuit according to claim 6, wherein the level shift circuit includes an analog adder / subtracter that adds the reference voltage to the ramp voltage and subtracts the offset voltage. The level shift circuit includes:
A first bipolar transistor receiving the ramp voltage at a base;
A first current source connected to the first bipolar transistor;
A second bipolar transistor of the same type as the first bipolar transistor to which a base collector is connected;
A resistor connected in series with the second bipolar transistor;
A second current source for supplying current to the series connection of the second bipolar transistor and the resistor;
An analog adder / subtracter for adding the emitter voltage of the first bipolar transistor and the reference voltage and subtracting the emitter voltage of the second bipolar transistor;
The power supply circuit according to claim 6, comprising:   The power supply circuit according to claim 1, wherein the power supply circuit is integrated on a single semiconductor substrate. Battery,
At least one load,
The power supply circuit according to any one of claims 1 to 9, which receives a voltage of the battery and supplies a power supply voltage to the at least one load.
An electronic device comprising:

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