KR20100105194A - Thin film transistor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: The thin film is formed from the neutral particle having the energy which the thin film transistor and manufacturing method thereof are similar through the thin film whole. The thin film transistor having the high charge transfer, and, the low-threshold voltage is offered. CONSTITUTION: A gate electrode(20) is formed on the substrate(10). The gate insulating layer(30) is formed on the gate electrode. The bottom half conductor(40) piled up one is formed on the gate insulating layer with the gate electrode. The top semiconductor(45) is formed on the bottom half conductor.

Description

Thin film transistor and manufacturing method therefor {THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a thin film transistor and a method of manufacturing the same.

Thin film transistors (TFTs) are used in various fields, and in particular, liquid crystal displays (LCDs), organic light emitting diode displays (OLED displays) and electrophoretic displays (electrophoretic). It is used as a switching and driving element in flat panel displays such as displays.

The thin film transistor includes a gate electrode connected to a gate line transferring a scan signal, a source electrode connected to a data line transferring a signal to be applied to the pixel electrode, a drain electrode facing the source electrode, and a source electrode and a drain electrode. It includes a semiconductor that is electrically connected.

Among them, the semiconductor is an important factor in determining the characteristics of the thin film transistor. Silicon (Si) is most commonly used as such a semiconductor and can be roughly divided into amorphous, polycrystalline, and microcrystalline semiconductor thin films according to its crystal form.

Hydrogenated amorphous silicon is widely used as an active layer in thin film transistors (TFTs) for active matrix liquid crystal displays. The reason is that the hydrogenated amorphous silicon thin film can be uniformly deposited over a large area by plasma enhanced chemical vapor deposition (PECVD). However, due to the amorphous structure, it has very low carrier mobility, which reduces the switching speed of the device and hinders the use of such transistors in the display driver circuit. In addition, the amorphous silicon TFT has a problem that operating characteristics such as current mobility and threshold voltage (V _th ) vary greatly with time due to a large number of trap states and passivation of incomplete hydrogen. There is a limitation in using the transistor as a driving element of an organic light emitting diode that needs to be driven for a long time.

Compared to the hydrogenated amorphous silicon, the conventional low temperature polycrystalline silicon (LTPS) has a low threshold voltage (Vth) shift problem, but there is no problem of luminance unevenness due to the positional threshold voltage difference. This is a very severe level of mura due to annealing nonuniformity, mainly by excimer laser for crystallization. In general, the pixel compensation circuitry is used to improve the nonuniformity, but sometimes it is difficult to bring the process margin very narrow by deviating from the compensation limit. At this time, the method of heat treatment without using an excimer laser came out again because of the problem of non-uniformity. Non-laser methods include solid phase crystallization (SPC), metal-induced lateral crystallization (MILC), and metal-induced crystallization (MIC). . However, this method has a much higher random mura than laser-based TFTs. In general, the pixel compensation circuitry is used to improve the nonuniformity, but sometimes it is difficult to bring the process margin very narrow by deviating from the compensation limit.

On the other hand, since microcrystalline silicon is crystallized, the change in operating characteristics is smaller than that of hydrogenated amorphous silicon. However, in order to form microcrystalline silicon, crystallization must be performed through a high temperature process or post-treatment process, which requires the use of additional substrates. Due to the dilution of carrier gas such as Ar and He and high hydrogen content, the process has a very slow deposition rate. In addition, the mobility is reduced due to the formation of an amorphous incubation layer between the lower gate insulating film and the polycrystalline and microcrystalline silicon thin film in which the bulk portion of the bottom gate TFT structure is high but the actual channel is formed. And dangling bonds at the grain boundary of the layer and the bulk portion and the disordered state also increase the leakage current in the off state of the TFT.

The microcrystalline silicon has a plurality of crystals having a fine size of nano to micro units, and may have a higher charge mobility and a lower threshold voltage than amorphous silicon.

However, microcrystalline silicon also requires a step of performing crystallization at a high temperature, which limits the substrates that can be used and still requires high manufacturing costs. In addition, due to the carrier gas (carrier gas) and hydrogen gas used in the process, it shows a slow deposition rate, and because of the irregular crystal between the gate insulating film and the microcrystalline silicon layer, the mobility may be lowered and the leakage current may be increased.

Therefore, the problem to be solved by the present invention is to increase the charge mobility and reduce the leakage current while reducing the manufacturing time and manufacturing cost when using the fine crystalline silicon.

A method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention includes forming a gate electrode, forming a gate insulating film on the gate electrode, forming a microcrystalline semiconductor on the gate insulating film, and Forming a source electrode and a drain electrode electrically connected and facing each other, wherein at least one of forming the gate insulating film and forming the microcrystalline semiconductor comprises disposing a substrate in a plasma discharge space; Supplying a solid element or a gas element for forming the gate insulating film or the microcrystalline semiconductor to the plasma discharge space, colliding the solid element or the gas element with plasma particles to generate a cation; Neutral mouth Converting to a ruler, and forming a thin film from the neutral particles.

The manufacturing method of the thin film transistor may further include forming an amorphous semiconductor after the forming of the microcrystalline semiconductor, and the forming of the amorphous semiconductor may include a solid element for forming the amorphous semiconductor in the plasma discharge space or Supplying a gaseous element, colliding the solid element or the gaseous element with plasma particles to produce a cation, converting the cation to neutral particles, and forming a thin film from the neutral particles have.

The method of manufacturing the thin film transistor may further include forming a resistive contact layer including an impurity-containing amorphous silicon after forming the amorphous semiconductor, and the forming of the resistive contact layer may include forming the resistive contact layer in the plasma discharge space. Supplying a solid element or a gaseous element to form a containing amorphous silicon, colliding the solid element or the gaseous element with plasma particles to produce a cation, converting the cation to neutral particles, and the neutral particle Forming a thin film from the may include.

The forming of the gate insulating layer, the forming of the microcrystalline semiconductor, the forming of the amorphous semiconductor, and the forming of the ohmic contact layer may be continuously performed in the plasma discharge space.

The supplying the solid element to the plasma discharge space may impinge the plasma on the target of the solid element to sputter the solid element into the plasma discharge space.

Supplying a gas element to the plasma discharge space may directly supply a gas element to the plasma discharge space in gaseous form.

Converting the cations to neutral particles includes inducing the cations to a metal plate disposed in the plasma discharge space, and converting the cations to the neutral particles by collision of the metal plate with the cations. Can be.

A thin film transistor according to another embodiment of the present invention includes a gate electrode, a microcrystalline semiconductor overlapping the gate electrode, an amorphous semiconductor formed on the microcrystalline semiconductor, and a source electrode and a drain electrode formed on the amorphous semiconductor. do.

The thin film transistor may further include an ohmic contact layer disposed between the amorphous semiconductor and the source electrode and between the amorphous semiconductor and the drain electrode.

In the present invention, it is possible to form a fine crystalline semiconductor without the need for a separate high temperature heat treatment to crystallize the semiconductor, it is possible to form a crystalline semiconductor of nano units smaller than the micro unit by controlling the amount of energy. In addition, it is possible to form a fine crystalline semiconductor having more uniform grains through the entire thin film, thereby preventing the charge mobility from changing irregularly by grain size, thereby preventing the characteristics of the thin film transistors from region to region. In addition, since the thin film is formed from neutral particles having the same energy through the entire thin film, fine crystals formed at the interface with the gate insulating film may also have grains of uniform size, and thus an incubation layer is almost formed between the gate insulating film and the microcrystalline silicon. It can be seen that. Accordingly, the microcrystalline semiconductor fabricated as described above may exhibit uniform thin film transistor characteristics, thereby exhibiting stable electrical characteristics, and a thin film transistor having a higher charge mobility and a lower threshold voltage than using amorphous silicon. Can be produced.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor according to an exemplary embodiment of the present invention will be described with reference to FIG. 1.

1 is a schematic cross-sectional view of a thin film transistor according to an exemplary embodiment.

Referring to FIG. 1, in the thin film transistor according to the exemplary embodiment, the gate electrode 20 is formed on a substrate 10 made of transparent glass, plastic, or silicon. The gate electrode 20 is made of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, gold-based metals such as gold (Au) and gold alloys, and copper (Cu ) And copper-based metals such as copper alloys, and molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), and tantalum (Ta).

A gate insulating film 30 covering the entire surface of the substrate is formed on the gate electrode 20. The gate insulating layer 30 may be made of silicon nitride (SiNx), silicon oxide (SiO ₂ ), or the like.

The lower semiconductor 40 and the upper semiconductor 45 overlapping the gate electrode 20 are sequentially formed on the gate insulating layer 30.

The lower semiconductor 40 is made of nanocrystalline or microcrystalline silicon, and the microcrystalline silicon has a plurality of crystals having a fine size of nano to micro units. The lower semiconductor 40 may be made of fine crystalline silicon to increase charge mobility as compared to amorphous silicon, thereby improving current characteristics.

The upper semiconductor 45 is made of amorphous silicon and is formed on the lower semiconductor 40 to prevent excessive charge from flowing to the lower semiconductor 40 made of fine crystalline silicon in an off state. Current can be reduced.

The source electrode 60 and the drain electrode 70 facing each other are formed on the upper semiconductor 45. Like the gate electrode 20, the source electrode 60 and the drain electrode 70 are aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and gold (Au). ) And gold-based metals such as gold alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), and tantalum ( Ta) or the like. The source electrode 60 and the drain electrode 70 are electrically connected to the upper semiconductor 45 and the lower semiconductor 40 in an on state.

An ohmic contact layer 50 is formed between the source electrode 60 and the upper semiconductor 45 and between the drain electrode 70 and the upper semiconductor 45. The ohmic contact layer 50 may be made of amorphous silicon containing impurities such as phosphorus (P) or boron (B), between the source electrode 60 and the upper semiconductor 45, and the drain electrode 70. Located between the upper semiconductor 45 to lower the contact resistance between them.

The channel Q of the thin film transistor is formed in the lower semiconductor 40 between the source electrode 60 and the drain electrode 70.

Next, a method of manufacturing the thin film transistor of FIG. 1 will be described with reference to FIGS. 2A to 3.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor of FIG. 1, and FIG. 3 is a schematic diagram illustrating a neutral particle beam apparatus used to manufacture the thin film transistor of FIG. 1.

First, the neutral particle beam apparatus used when manufacturing the thin film transistor according to the present invention will be described with reference to FIG. 3.

Referring to FIG. 3, the neutral particle beam apparatus includes a chamber 101 of a predetermined size which is a plasma discharge space.

A solid element target 102 is disposed on one side of the chamber 101, and the solid element target 102 is coated with a solid element on a plate made of metal, and a predetermined bias is applied thereto.

The gas supply port 103 is disposed at the other side of the chamber 101, and the gas supply port 103 may be supplied with a source gas supplying a gas or gas element for plasma formation.

The metal plate 104 is disposed at the upper end of the chamber 101. The metal plate 104 may be made of stainless or the like, and a predetermined bias is applied to generate neutral particles from the plasma particles.

At the lower end of the chamber 101, a support 106 for supporting a substrate is disposed.

A plurality of magnetic array limiters 105 are disposed in the chamber 101. The magnet array limiter 105 serves to block electrons and other ions present in the plasma discharge space from approaching the substrate and to selectively send neutral particles toward the substrate.

Next, a method of forming a thin film on a substrate using the neutral particle beam device will be described. The thin film may be the gate insulating layer 30 of FIG. 1, the lower semiconductor 40 made of fine crystalline silicon, the upper semiconductor 45 made of amorphous silicon, and the ohmic contact layer 50 made of amorphous silicon containing impurities. In the above-described neutral particle beam apparatus, at least one selected from these may be formed.

Referring to FIG. 2A, a conductive layer is stacked on the insulating substrate 10 and photo-etched to form a gate electrode 20 having a predetermined pattern.

Subsequently, the substrate 110 on which the gate electrode 20 is formed is disposed on the support 106 in the neutral particle beam device shown in FIG. 3.

Subsequently, gas for plasma generation is supplied into the chamber 101 through the gas supply port 103. The gas is plasma discharged in the chamber 101 to produce plasma particles.

Subsequently, a source gas containing a gas element is supplied through the gas supply port 103. When silicon nitride (SiNx) is formed as the gate insulating film 30, silicon-containing gas and nitrogen-containing gas are supplied as the source gas, and hydrogen gas (H ₂ ), nitrogen gas (N ₂ ), and other inert gas may be supplied together. Can be. The silicon-containing gas here can be for example silane (SiH ₄ ) and the nitrogen-containing gas can be for example ammonia gas (NH ₃ ).

The source gas containing the gas element collides with the plasma particles in the chamber 101 to become cations. This cation can be induced to the metal plate 104 to which a negative bias is applied. In this case, a negative bias of about 10 to 100V may be applied to the metal plate 104. The cations collide with the metal plate 104 and receive energy from the metal plate 104 to become neutral particles.

The neutral particles move through the plurality of magnet array limiters 105 toward the substrate and contact the surface of the substrate 110 disposed on the support 106 to form a thin film.

At this time, the magnet array limiter 105 forms a magnetic field to block electrons and other ions present in the plasma discharge space from approaching the substrate side, and may selectively send only neutral particles toward the substrate.

Accordingly, as shown in FIG. 2B, the gate insulating film 30 is formed on the gate electrode 20.

Next, a semiconductor is formed by a continuous process.

The semiconductor can be performed by supplying a solid element or a gas element.

First, the case of supplying a solid element will be described.

By the above-described method, the substrate 110 on which the gate insulating film 30 is formed is disposed on the support base 106. Subsequently, gas for plasma formation is supplied into the chamber 101 through the gas supply port 103. The gas is plasma discharged in chamber 101 to convert it into plasma particles. The plasma particles are directed to the solid element target 102 with a negative bias applied. In this case, the solid element may be silicon (Si), and a negative bias of about 500 V may be applied to the solid element target 102.

The plasma particles collide with the solid element target 102 to produce solid element cations, which are sputtered into the plasma discharge space. The sputtered solid element cations can be directed to the metal plate 104 to which a negative bias is applied. In this case, a negative bias of about 10 to 100V may be applied to the metal plate 104. The cations collide with the metal plate 104 and receive energy from the metal plate 104 to become neutral particles.

The neutral particles move through the plurality of magnet array limiters 105 toward the substrate and contact the surface of the substrate 110 disposed on the support 106 to form a thin film.

As a result, as shown in FIG. 2C, a lower semiconductor 40 made of fine crystalline silicon is formed on the gate insulating layer 30.

When the semiconductor is supplied by supplying a gas element, the semiconductor is performed in the same manner as the gate insulating film 30 described above. However, at this time, the source gas containing the gas element may supply the silicon-containing gas together with hydrogen gas (H ₂ ), nitrogen gas (N ₂ ), and other inert gases. The silicon-containing gas here can be, for example, silane (SiH ₄ ).

Next, as shown in FIG. 2D, the upper semiconductor 45 is formed on the lower semiconductor 40. The upper semiconductor 45 is formed in the same manner as described above with the lower semiconductor 40, but the lower semiconductor 40 is made of fine crystalline silicon and the upper semiconductor 45 is made of amorphous silicon. The lower semiconductor 40 and the upper semiconductor 45 both contain silicon, but the lower semiconductor 40 supplies higher energy than the upper semiconductor 45 and is made of fine crystalline silicon, and the upper semiconductor 45 has lower energy. Supply is made of silicon in amorphous form.

Next, referring to FIG. 2E, an ohmic contact layer 50 is formed by stacking silicon containing impurities such as phosphorus (P) or boron (B) on the upper semiconductor 45.

The ohmic contact layer 50 is also carried out in the plasma discharge space in the same manner as described above, wherein the source gas containing the gas element includes silicon-containing gas and impurity-containing gas such as hydrogen gas (H ₂ ) and nitrogen gas (N ₂ ). And other inert gases can be fed together. The silicon-containing gas here may be for example silane (SiH ₄ ) and the impurity-containing gas may be for example phosphine (PH ₃ ) or borane (borane, B ₂ H ₆ ).

Forming the gate insulating film 30 described above, forming the lower semiconductor 40 made of fine crystalline silicon, forming the upper semiconductor 45 made of amorphous semiconductor, and resistive contact made of silicon containing impurities Forming the layer 50 may be performed continuously in the plasma discharge space.

Subsequently, as shown in FIG. 1, the conductive layer is stacked on the ohmic contact layer 50 and photo-etched to form the source electrode 60 and the drain electrode 70.

As described above, in the present invention, since the neutral particle beam device adjusts the bias voltage and supplies energy to the neutral particles to form the fine crystalline semiconductor, a separate high temperature heat treatment for crystallizing the semiconductor is unnecessary. In addition, the amount of energy can be controlled to form crystalline semiconductors smaller than micro units, and thin films are formed from neutral particles having the same energy throughout the thin film, thereby forming a fine crystalline semiconductor having more uniform grain. Can be. Therefore, it is possible to prevent the charge mobility from being changed irregularly by the grain size, thereby preventing the characteristics of the thin film transistor from being different depending on the region.

In addition, the interface characteristics between the gate insulating film and the semiconductor will be described with reference to FIG. 4.

4 is a photograph showing an interface between a gate insulating film and a semiconductor in the thin film transistor according to the present invention.

In general, when a polycrystalline or microcrystalline semiconductor is formed on a gate insulating layer in a bottom gate structure in which a gate electrode is formed under the semiconductor, an incubation layer that is not crystallized in a portion of the semiconductor that contacts the gate insulating layer is formed. exist. Since the portion of the semiconductor, which is in contact with the gate insulating layer, is substantially the portion where the channel Q of the thin film transistor is formed, the charge mobility is lowered by the incubation layer.

In the thin film transistor according to the present invention, as shown in FIG. 4, the size of the fine crystalline grains present in the vicinity of the interface 403 between the gate insulating film 401 and the lower semiconductor 402 made of the microcrystalline silicon has a lower semiconductor 402. You can see that there is no significant difference from other parts of). That is, in the present invention, since the fine particle penetrates the neutral particles while controlling the bias voltage in the neutral particle beam apparatus, the microcrystalline semiconductor gate insulating film and the semiconductor are continuously performed in the plasma discharge space, so that the thin film is formed from the neutral particles having the same energy throughout the entire thin film. Since the fine crystalline formed at the interface with the gate insulating film can also be formed grains of uniform size, it can be seen that the incubation layer is hardly formed between the gate insulating film and the fine crystalline silicon. Accordingly, the microcrystalline semiconductor fabricated as described above may exhibit uniform thin film transistor characteristics, thereby exhibiting stable electrical characteristics, and a thin film transistor having a higher charge mobility and a lower threshold voltage than using amorphous silicon. Can be produced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a cross-sectional view schematically illustrating a thin film transistor according to an exemplary embodiment of the present disclosure.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor of FIG. 1.

FIG. 3 is a schematic diagram showing a neutral particle beam apparatus used to manufacture the thin film transistor of FIG. 1,

4 is a photograph showing an interface between a gate insulating film and a semiconductor in the thin film transistor according to the present invention.

Claims (9)

Forming a gate electrode, Forming a gate insulating film on the gate electrode; Forming a fine crystalline semiconductor on the gate insulating film, and Forming a source electrode and a drain electrode electrically connected to the microcrystalline semiconductor and facing each other; Including, At least one of the step of forming the gate insulating film and the step of forming the fine crystalline semiconductor Placing the substrate in the plasma discharge space, Supplying a solid element or a gas element for forming the gate insulating film or the microcrystalline semiconductor to the plasma discharge space, Colliding the solid element or the gas element with plasma particles to generate a cation, Converting the cation to neutral particles, and Forming a thin film from the neutral particles  Method of manufacturing a thin film transistor comprising a. In claim 1, Forming an amorphous semiconductor after the forming of the microcrystalline semiconductor, Forming the amorphous semiconductor is Supplying a solid element or a gas element for forming the amorphous semiconductor to the plasma discharge space, Colliding the solid element or the gas element with plasma particles to generate a cation; Converting the cation to neutral particles, and Forming a thin film from the neutral particles Method of manufacturing a thin film transistor comprising a. In claim 2, Forming an ohmic contact layer including an impurity-containing amorphous silicon after the forming of the amorphous semiconductor, Forming the ohmic contact layer Supplying a solid element or a gas element for forming the impurity-containing amorphous silicon into the plasma discharge space, Colliding the solid element or the gas element with plasma particles to generate a cation; Converting the cation to neutral particles, and Forming a thin film from the neutral particles Method of manufacturing a thin film transistor comprising a. 4. The method of claim 3, And forming the gate insulating film, forming the microcrystalline semiconductor, forming the amorphous semiconductor, and forming the ohmic contact layer are continuously performed in the plasma discharge space. In claim 4, The supplying a solid element into the plasma discharge space may impinge the plasma on a target of the solid element to sputter the solid element into the plasma discharge space. In claim 5, Converting the cation to neutral particles Directing the cations to a metal plate disposed in the plasma discharge space, and Converting the cation into the neutral particles by collision of the metal plate with the cation Method of manufacturing a thin film transistor comprising a. In claim 2, The supplying a gas element to the plasma discharge space is a method of manufacturing a thin film transistor for supplying a gas element directly to the plasma discharge space in the form of a gas. Gate electrode, A fine crystalline semiconductor overlapping the gate electrode, An amorphous semiconductor formed on the microcrystalline semiconductor, and Source and drain electrodes formed on the amorphous semiconductor Thin film transistor comprising a. In claim 8, And a resistive contact layer between the amorphous semiconductor and the source electrode and between the amorphous semiconductor and the drain electrode.

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