KR20100097300A - Manufacturing method of phase change random access memory device - Google Patents

Manufacturing method of phase change random access memory device Download PDF

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KR20100097300A
KR20100097300A KR1020090016176A KR20090016176A KR20100097300A KR 20100097300 A KR20100097300 A KR 20100097300A KR 1020090016176 A KR1020090016176 A KR 1020090016176A KR 20090016176 A KR20090016176 A KR 20090016176A KR 20100097300 A KR20100097300 A KR 20100097300A
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phase change
memory device
layer
oxide film
electrode contact
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김현우
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주식회사 하이닉스반도체
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    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
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Abstract

PURPOSE: A phase change memory device manufacturing method is provided to improve the contact property between a phase change material layer and a bottom electrode contact by removing an oxide layer formed during transfer between chambers. CONSTITUTION: An impurity region(100a) is formed on the top of a semiconductor substrate(100). A first interlayer dielectric layer(110) is formed on the top of the semiconductor substrate on which the impurity region is formed. A switching element(120) is formed within the first interlayer dielectric layer to contact the impurity region.

Description

상변화 메모리 소자의 제조방법{Manufacturing Method of Phase Change Random Access Memory Device}Manufacturing Method of Phase Change Random Access Memory Device

본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 보다 구체적으로는 상변화 메모리 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a phase change memory device.

정보 산업이 발달함에 따라 대용량의 정보 처리가 요구되어 왔다. 따라서 고용량의 정보를 저장할 수 있는 정보 저장 매체에 관한 수요는 지속적으로 증가되었다. 수요의 증가에 따라 정보 저장 속도가 빠르면서 소형의 정보 저장 매체에 관한 연구가 진행되고 있으며 결과적으로 다양한 종류의 정보 저장 장치가 개발되었다.As the information industry develops, a large amount of information processing has been required. Therefore, the demand for an information storage medium capable of storing a large amount of information has continuously increased. As the demand increases, the research on small information storage media is progressing rapidly. As a result, various types of information storage devices have been developed.

차세대 메모리 소자로 현재 연구가 진행중인 것으로 상변화 메모리 소자(Phase Change Random Access Memory Device: PRAM)를 들 수 있다. 상변화 메모리 소자는 주로 칼코게나이드(chalcogenide) 계열 등의 상변화 물질로 형성된 상변화층을 포함한다. 상변화 물질은 결정질 상태일 때와 비결정질 상태일 때, 명확히 다른 저항을 갖는다. 즉, 상변화 물질은 저항값으로 명확히 구분되는 두가지 상태를 지니며, 두가지 상태는 온도에 따라 가역적으로 변화될 수 있다. 현재, 상변화 물질로 많은 물질이 알려져 있으나, 그 중에서 대표적이며 가장 많이 사용되고 있 는 물질이 GST(Ge2Sb2Te5)이다.Current research is being conducted on next-generation memory devices, including Phase Change Random Access Memory Device (PRAM). The phase change memory device mainly includes a phase change layer formed of a phase change material such as a chalcogenide series. Phase change materials have distinctly different resistances when in the crystalline state and in the amorphous state. That is, the phase change material has two states that are clearly distinguished by resistance values, and the two states may be reversibly changed with temperature. Currently, many materials are known as phase change materials, but the representative and most used materials among them are GST (Ge 2 Sb 2 Te 5 ).

일반적으로, 상변화 메모리 소자는 하부 전극 및 상부 전극을 통하여 전류를 인가함으로써 상변화층과 하부 전극 콘택과의 접촉 영역에서의 주울 열을 발생시켜 상변화층의 결정질 및 비결정질의 가역적인 변화를 일으킴으로써 정보를 기록하게 된다. 특히 상변화가 집중적으로 발생하는 영역을 프로그램 영역(Program Volume; 이하, PV영역)이라 한다.In general, the phase change memory device generates Joule heat in the contact region between the phase change layer and the lower electrode contact by applying a current through the lower electrode and the upper electrode, thereby causing a crystalline and amorphous reversible change of the phase change layer. Information is recorded. In particular, an area in which phase change occurs intensively is called a program area (hereinafter, referred to as a PV area).

도 1은 일반적인 상변화 메모리 소자의 단면도이다.1 is a cross-sectional view of a general phase change memory device.

도 1을 참조하면, 하부 전극 콘택(미도시)을 포함하는 하부 구조(10)를 제 1 챔버 내에서 형성한다. 이후, 후속 공정 즉, 상변화 물질층 증착 공정을 위하여 챔버 간 이동을 실행한다. 이때, 챔버 간 이동중에 공기와의 접촉으로 인해 상기 하부 구조(10) 상에 산화막(30)이 형성될 수 있다. 이렇게 형성된 산화막(30) 상에 상변화 물질층이 증착될 경우, 상변화 메모리 소자의 내구성 불량을 발생시키는 원인이 된다. 이러한 내구성 불량은 PV 영역과 하부 전극 콘택과의 접촉 계면의 부착(adhesion) 불량 현상 중의 하나로서 상변화 패턴층(35)과 하부 전극 콘택과의 계면에서 약, 수백 MΩ의 비저항 증가을 야기시켜 열손실을 유발 시킨다. Referring to FIG. 1, a bottom structure 10 including a bottom electrode contact (not shown) is formed in a first chamber. Thereafter, the inter-chamber movement is performed for the subsequent process, that is, the phase change material layer deposition process. In this case, the oxide layer 30 may be formed on the lower structure 10 due to contact with air during the movement between the chambers. When the phase change material layer is deposited on the oxide film 30 formed as described above, it causes a failure in durability of the phase change memory device. This poor durability is one of the poor adhesion of the contact interface between the PV region and the lower electrode contact, causing an increase in resistivity of about several hundred MΩ at the interface between the phase change pattern layer 35 and the lower electrode contact. Cause.

따라서, 본 발명의 목적은 상변화 물질층과 하부 전극 콘택과의 접촉 특성을 향상시킬 수 있는 상변화 메모리 소자의 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a phase change memory device capable of improving the contact characteristics of a phase change material layer and a lower electrode contact.

또한, 본 발명의 다른 목적은 상변화 물질층의 열손실 및 상변화 물질층의 프로그램 영역의 상태 변화를 줄일 수 있는 상변화 메모리 소자의 제조방법을 제공하는 것이다. Another object of the present invention is to provide a method of manufacturing a phase change memory device capable of reducing heat loss of a phase change material layer and a change in state of a program region of the phase change material layer.

상기 목적을 달성하기 위한 본 발명의 상변화 메모리 소자의 제조방법은 제 1 챔버 내에서 하부 전극 콘택을 포함하는 하부 구조를 형성한 반도체 기판을 제 2 챔버로 이동하는 단계, 상기 반도체 기판을 상기 제 2 챔버로 이동함에 따라 형성된 산화막을 제거하는 단계, 및 상기 하부 전극 콘택을 노출시키는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a phase change memory device, including: moving a semiconductor substrate having a lower structure including a lower electrode contact in a first chamber to a second chamber; Removing the oxide film formed as it moves to the two chambers, and exposing the lower electrode contacts.

본 발명에 의하면, 챔버간 이동중에 형성되는 산화막을 제거함으로써 상변화 패턴층과 하부 전극 콘택과의 접촉 계면의 부착성을 향상시켜 상변화 메모리 소자의 열화를 방지 할 수 있다.According to the present invention, the adhesion of the contact interface between the phase change pattern layer and the lower electrode contact can be improved by removing the oxide film formed during the inter-chamber movement, thereby preventing deterioration of the phase change memory device.

이하, 첨부한 도면에 의거하여 본 발명의 바람직한 일 실시예를 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2 내지 도 6은 본 발명의 일 실시예에 따라 형성된 상변화 메모리 소자의 각 공정별 단면도이다. 2 to 6 are cross-sectional views of processes of a phase change memory device formed in accordance with an embodiment of the present invention.

먼저, 도 2에 도시된 것과같이, 반도체 기판(100) 상에 불순물 영역(100a)을 형성한다. 상기 불순물 영역(100a)이 형성된 반도체 기판(100) 상부에 제 1 층간 절연층(110)을 형성한 다음, 제 1 층간 절연층(110) 내에 불순물 영역(100a)과 콘택되도록 스위칭 소자(120)를 형성한다. 본 발명의 실시예에서는 스위칭 소자(120)로서 PN 다이오드를 사용하였다.First, as shown in FIG. 2, the impurity region 100a is formed on the semiconductor substrate 100. After forming the first interlayer insulating layer 110 on the semiconductor substrate 100 on which the impurity region 100a is formed, the switching element 120 is in contact with the impurity region 100a in the first interlayer insulating layer 110. To form. In the exemplary embodiment of the present invention, a PN diode is used as the switching element 120.

상기 스위칭 소자(120) 상부에 오믹 콘택층(130)을 형성할 수 있고, 본 발명에서는 오믹 콘택층(130) 물질로 코발트실리사이드(CoSi2)를 사용하였다.An ohmic contact layer 130 may be formed on the switching element 120. In the present invention, cobalt silicide (CoSi 2 ) is used as the ohmic contact layer 130 material.

다음으로, 전체구조 상부에 제 2 층간 절연층(140)을 형성한 후, 상기 제 2 층간 절연층(140)을 부분적으로 식각하여, 오믹 콘택층(130)을 선택적으로 노출시키는 콘택홀(141)을 형성한다.Next, after the second interlayer insulating layer 140 is formed on the entire structure, the contact hole 141 selectively exposes the ohmic contact layer 130 by partially etching the second interlayer insulating layer 140. ).

상기 층간 절연층(110,140)은 예를들어, TEOS(Tetra Ethly Ortho Silicate), USG(Undoped Silcate Glass) 또는 HDP-CVD(High Density Plasma-CVD) 등을 이용한 산화물이거나, 혹은 산화물과 질화물의 복합층일 수 있다.The interlayer insulating layers 110 and 140 may be, for example, oxides using Tetra Ethly Ortho Silicate (TEOS), Undoped Silcate Glass (USG), or High Density Plasma-CVD (HDP-CVD), or a composite layer of oxide and nitride. Can be.

그리고 나서, 도 3에 도시된 바와같이, 전체구조 상부에 도전성 물질인 티타늄(Ti), 질화티타늄(TiN) 또는 질화알루미늄티타늄(TiAlN) 등을 증착하여 하부 전극 콘택층(150)을 형성한다. 상기 하부 전극 콘택층(150)은 하부 전극 콘택홀(141)의 하부면과 측벽 및 제 2 층간 절연막(140) 상부에 증착된다.3, the lower electrode contact layer 150 is formed by depositing titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), or the like, on the entire structure. The lower electrode contact layer 150 is deposited on the lower surface and sidewalls of the lower electrode contact hole 141 and on the second interlayer insulating layer 140.

그리고 나서, SOD(Spin-On Dielectric)와 같은 유동성 절연막(160)을 이용하여 상기 하부 전극 콘택층(150)이 형성된 하부 전극 콘택홀(141) 내부를 충진시킨다. Then, the inside of the lower electrode contact hole 141 in which the lower electrode contact layer 150 is formed is filled by using a fluid insulating layer 160 such as spin-on dielectric (SOD).

부연하자면, 상기 하부 전극 콘택층(150)이 측벽에 형성된 하부 전극 콘택홀(141) 내부를 종래의 일반적인 절연물(예컨대, 실리콘산화막)로 충진하게 되면 하부 전극 콘택홀(141) 내부가 절연물로 완전히 충진되지 못하고, 중간에 보이드(Void)가 형성된다. 그러므로 보이드(Void) 없이 하부 전극 콘택홀(141)를 충진시키기 위해서는 매립 특성이 우수하며 액상인 SOD(Spin-On Dielectric)와 같은 유동성 절연막(160)을 이용하여 하부 전극 콘택홀(141) 내부를 충진시킴이 바람직하다. In other words, when the lower electrode contact layer 150 fills the inside of the lower electrode contact hole 141 formed on the sidewall with a conventional general insulator (eg, a silicon oxide film), the inside of the lower electrode contact hole 141 may be completely filled with an insulator. It is not filled, and a void is formed in the middle. Therefore, in order to fill the lower electrode contact hole 141 without a void, the buried property is excellent and the inside of the lower electrode contact hole 141 is formed by using a fluid insulating layer 160 such as liquid spin-on dielectric (SOD). Filling is preferred.

상기 유동성 절연막(160)은 액상이기 때문에 스핀코팅에 의해 하부 전극 콘택홀(141) 내부를 충진하고, 후속으로 어닐링 공정을 통하여 교차결합(Cross-linking) 및 SOD 절연막(160)의 치밀화를 수행할 수 있다.Since the fluid insulating layer 160 is a liquid phase, the inside of the lower electrode contact hole 141 is filled by spin coating, and subsequently, cross-linking and densification of the SOD insulating layer 160 are performed through an annealing process. Can be.

이때, 상기 SOD 절연막과 같은 유동성 절연막(160) 이외에도, 매립 특성이 우수한 HDP(High Density Plasma) 절연막, O3 USG(Undoped Silcate Glass), TEOS(Tetra Ethyl Ortho Silicate), HLD(High temp, low pressure dielectric)등을 사용할 수도 있다.At this time, in addition to the fluid insulating film 160 such as the SOD insulating film, HDP (High Density Plasma) insulating film, O3 Undoped Silcate Glass (O3 USG), Tetra Ethyl Ortho Silicate (TEOS), High temp, low pressure dielectric You can also use).

그리고 나서, 상기 제 2 층간 절연막(140) 상의 하부 전극 콘택층(150)과 유동성 절연막(160)을 평탄화하여, 상기 콘택홀(141) 내에 하부 전극 콘택층(150) 및 유동성 절연막(160)을 매립시킨다. 이때, 상기 평탄화 방법으로는 이등방성 식각 및 CMP(Chemical Mechanical Polishing)가 이용될 수 있다.Thereafter, the lower electrode contact layer 150 and the flowable insulating layer 160 on the second interlayer insulating layer 140 are planarized to form the lower electrode contact layer 150 and the flowable insulating layer 160 in the contact hole 141. Landfill. In this case, anisotropic etching and chemical mechanical polishing (CMP) may be used as the planarization method.

이후, 도 4에 도시된 바와같이, 상변화 물질층 형성을 위해 상기 전체 구조가 형성된 반도체 기판(100)을 제 2 챔버 내로 이동한다. 이때, 제 1 챔버에서 제 2 챔버로 이동 대기중에 공기와의 접촉으로 인해 전체 구조 상부에 20Å~25Å의 산화막(170)이 형성된다. 상기 형성된 산화막(170)은 후속 증착되는 상변화 물질층의 발열과정상의 문제점을 열화 시킬 수 있다. 따라서, 본 발명에서는 상변화 물질층 증착전에 형성된 산화막을 RF 식각 공정(190)을 통해 제거한다. Thereafter, as shown in FIG. 4, the semiconductor substrate 100 having the entire structure is moved into the second chamber to form a phase change material layer. At this time, the oxide film 170 of 20 kV to 25 kV is formed on the entire structure due to contact with air during the moving air from the first chamber to the second chamber. The formed oxide film 170 may deteriorate a problem in the heating process of the phase change material layer which is subsequently deposited. Therefore, in the present invention, the oxide film formed before the deposition of the phase change material layer is removed through the RF etching process 190.

이때, RF 식각(190)을 하기 전 전체 구조 상에 약 20Å~25Å 범위 내의 두께로 잔존하는 산화막(170)은 RF 식각(190)으로 제거하기에는 너무 얇은 두께를 갖기 때문에 RF 식각(190) 공정으로 제거할 수 있는 최소한의 두께인 45Å의 두께가 형성되도록 잔존하는 산화막 상에 추가 산화막(180)을 20~25Å 정도 형성하도록 한다. 그리고 나서, 제 2 챔버 내에 아르곤(Ar) 가스를 주입하여 400W 전력의 플라즈마 파워로 30초간 상기 RF 식각(190) 공정을 진행한다. At this time, the oxide film 170 remaining in the thickness within the range of about 20 ~ 25 상 에 on the entire structure before the RF etch 190 has a thickness too thin to be removed by the RF etch 190 to the RF etching 190 process An additional oxide film 180 is formed on the remaining oxide film by about 20 to 25 GPa so as to form a thickness of 45 GPa which is a minimum thickness that can be removed. Thereafter, argon (Ar) gas is injected into the second chamber to perform the RF etching 190 for 30 seconds using a plasma power of 400 W.

이후, 도 5에 도시된 바와같이, 산화막이 제거된 전체 구조 상부에 상변화 물질층(200), 상부전극층(210) 및 하드 마스크막 예컨데, 실리콘 질산화막(SiON)(220)을 순차적으로 증착하고 실리콘질산화막(220) 상부에 감광막 패턴(도시하지 않음)을 형성한 후, 식각 공정 과정을 거쳐 상변화 패턴층(225)을 형성한다.Subsequently, as shown in FIG. 5, the phase change material layer 200, the upper electrode layer 210, and the hard mask layer, for example, silicon nitride oxide (SiON) 220 are sequentially deposited on the entire structure from which the oxide film is removed. After forming a photoresist pattern (not shown) on the silicon oxynitride layer 220, a phase change pattern layer 225 is formed through an etching process.

그리고 나서, 도 6에 도시된 바와같이, 캡핑막 증착 공정을 진행한다. 상기 캡핑막 공정은 상기 후속 공정인 절연막 증착시에 상변화 패턴층(225)이 산화되는 것을 방지 하기 위한 공정으로 200℃의 저온에서 상기 전체구조 상부에 실리콘질산화막(SiON)(230), 산화알루미늄막(Al2O3)(230a), 실리콘 질산화막(SiON)(230b)을 순차적으로 증착한다.Then, as shown in FIG. 6, a capping film deposition process is performed. The capping film process is a process for preventing the phase change pattern layer 225 from being oxidized during the deposition of the insulating film, which is a subsequent process. An aluminum film (Al 2 O 3 ) 230a and a silicon nitride oxide (SiON) 230b are sequentially deposited.

따라서, 본 발명은 제 1 챔버에서 제 2 챔버로 이동시에 상변화 패턴층과 하부 전극 콘택과의 접촉계면에 생성되는 산화막을 제거함으로써 하부 전극 콘택과 상변화 패턴층과의 접촉 능력을 향상시킴으로써 후속 공정에 따른 상변화 물질층의 데미지를 최소화 할 수 있다. Accordingly, the present invention is improved by removing the oxide film formed on the contact interface between the phase change pattern layer and the lower electrode contact when moving from the first chamber to the second chamber, thereby improving the ability to contact the lower electrode contact with the phase change pattern layer. The damage of the phase change material layer according to the process can be minimized.

이와 같이, 본 발명이 속하는 기술분야의 당업자는 본 발명이 그 기술적 사상이나 필수적 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적인 것이 아닌것으로서 이해해야만 한다. 본 발명의 범위는 상세한 설명보다는 후술하는 특허청구범위에 의하여 나타내어지며, 특허청구범위의 의미 및 범위 그리고 그 등가 개념으로부터 도출되는 모든 변경 또는 변형된 형태가 본 발명의 범위에 포함되는 것으로 해석되어야 한다.As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

도 1은 일반적인 상변화 메모리 소자의 단면도, 및1 is a cross-sectional view of a general phase change memory device, and

도 2 내지 도 6는 본 발명의 일 실시예에 따른 상변화 메모리 소자의 각 공정별 단면도이다. 2 to 6 are cross-sectional views of each process of the phase change memory device according to the exemplary embodiment of the present invention.

〈주요 도면부호의 상세한 설명〉<Detailed description of the main reference numerals>

170,180 : 산화막 225 : 상변화 패턴층170,180: oxide film 225: phase change pattern layer

230.230a,230b : 캡핑막230.230a, 230b: capping film

Claims (7)

제 1 챔버 내에서 하부 전극 콘택을 포함하는 하부 구조를 형성한 반도체 기판을 제 2 챔버로 이동하는 단계;Moving a semiconductor substrate having a lower structure including a lower electrode contact in the first chamber to a second chamber; 상기 반도체 기판을 상기 제 2 챔버로 이동함에 따라 형성된 산화막을 제거하는 단계; 및 Removing the oxide film formed by moving the semiconductor substrate to the second chamber; And 상기 하부 전극 콘택을 노출시키는 단계를 포함하는 상변화 메모리 소자의 제조방법.And exposing the bottom electrode contact. 제 1 항에 있어서,The method of claim 1, 상기 산화막을 제거하는 단계는,Removing the oxide film, 상기 제 2 챔버로 이동 중에 형성된 상기 하부 구조 상에 잔존하는 산화막에 추가 산화막을 재증착하여 제거하는 것을 특징으로 하는 상변화 메모리 소자의 제조방법.And re-depositing an additional oxide film on the remaining oxide film on the lower structure formed during movement to the second chamber. 제 1 항에 있어서,The method of claim 1, 상기 산화막을 제거하는 단계는 RF 식각 공정을 이용하여 진행하는 것을 특징으로 하는 상변화 메모리 소자의 제조방법.The removing of the oxide layer may be performed using an RF etching process. 제 3 항에 있어서,The method of claim 3, wherein 상기 RF 식각 공정시, 상기 산화막의 식각 타겟 범위는 40Å~45Å으로 설정하는 것을 특징으로 상변화 메모리 소자의 제조방법.During the RF etching process, the etching target range of the oxide film is set to 40 ~ 45 ~, the method of manufacturing a phase change memory device. 제 3 항에 있어서,The method of claim 3, wherein 상기 RF 식각 공정을 진행함에 있어서,In the RF etching process, RF 식각 가스는 아르곤(Ar) 가스를 이용하며, DC 400W의 플라즈마 파워로 30초 간 진행하는 것을 특징으로 하는 상변화 메모리 소자의 제조방법.RF etching gas using an argon (Ar) gas, the method of manufacturing a phase change memory device, characterized in that for 30 seconds to proceed with a plasma power of DC 400W. 제 1 항에 있어서,The method of claim 1, 상기 하부 전극 콘택 상에 상변화 패턴층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 상변화 메모리 소자의 제조방법.And forming a phase change pattern layer on the lower electrode contact. 제 6 항에 있어서,The method of claim 6, 상기 상변화 패턴층 형성후, 캡핑막을 형성하는 단계를 더 포함하는 상변화 메모리 소자의 제조방법.And forming a capping film after the phase change pattern layer is formed.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592796B2 (en) 2011-06-21 2013-11-26 Hynix Semiconductor Inc. Phase-change random access memory device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592796B2 (en) 2011-06-21 2013-11-26 Hynix Semiconductor Inc. Phase-change random access memory device and method of manufacturing the same

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