KR101069655B1 - Manufacturing Method of Phase Change Random Access Memory Device - Google Patents

Abstract

A method of manufacturing a phase change memory device according to the present invention includes providing a semiconductor substrate having a lower electrode contact, forming a phase change pattern layer on an upper portion of a lower electrode contact, and bonding force between a lower electrode contact and the phase change pattern layer. It includes; performing a heat treatment process on the entire structure for reinforcement.

Phase change memory device, ultraviolet heat treatment

Description

Manufacturing Method of Phase Change Random Access Memory Device

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a phase change memory device.

As the information industry develops, a large amount of information processing has been required. Therefore, the demand for an information storage medium capable of storing a large amount of information has continuously increased. As the demand increases, the research on small information storage media is progressing rapidly. As a result, various types of information storage devices have been developed.

Current research is being conducted on next-generation memory devices, including Phase Change Random Access Memory Device (PRAM). The phase change memory device mainly includes a phase change layer formed of a phase change material such as a chalcogenide series. Phase change materials have distinctly different resistances when in the crystalline state and in the amorphous state. That is, the phase change material has two states that are clearly distinguished by resistance values, and the two states may be reversibly changed with temperature. Currently, many materials are known as phase change materials, but the representative and most used materials among them are GST (Ge ₂ Sb ₂ Te ₅ ).

In general, the phase change memory device generates Joule heat in the contact region between the phase change layer and the lower electrode contact by applying a current through the lower electrode and the upper electrode, thereby causing a crystalline and amorphous reversible change of the phase change layer. Information is recorded. In particular, an area in which phase change occurs intensively is called a program area (hereinafter, referred to as a PV area).

1A is a cross-sectional view illustrating a general phase change memory device.

Referring to FIG. 1A, a general phase change memory device forms an interlayer insulating layer 20 having a lower electrode contact (BEC) 30 buried on a semiconductor substrate on which a lower structure 10 is formed. A phase change pattern layer 40 is formed on the lower electrode contact 30, and a capping film 50 is formed around the phase change pattern layer 40. Here, reference numeral 60 shows a contact interface between the lower electrode contact 30 and the phase change pattern layer 40.

FIG. 1B is an enlarged cross-sectional view of the contact interface 60 between the lower electrode contact and the phase change pattern layer illustrated in FIG. 1A.

At this time, referring to Figure 1b, the maintenance of the physical properties, such as the composition of the phase change layer material, for example, GST used in the phase change memory device is the most important problem to ensure the reliability of the phase change memory device. As a cause of poor durability of the current phase change memory device, a problem of poor adhesion of the contact interface between the PV region and the lower electrode contact 30 occurs, and the phase change pattern layer 40 during the phase change process. The problem of heat loss and PV region change due to an increase in resistivity of about several hundred MΩ at the interface between the and bottom electrode contacts and 30 is mentioned.

Here, reference numeral 70 shows an interface in poor contact between the PV region and the lower electrode contact 30.

This problem is difficult to fundamentally solve since the PV region is formed at the contact interface between the phase change pattern layer 40 and the lower electrode contact 30. Various attempts have been made to solve this problem, but no clear solution has been proposed to date.

Accordingly, an object of the present invention is to provide a method of manufacturing a phase change memory device capable of improving the contact characteristics of a phase change material layer and a lower electrode contact.

Another object of the present invention is to provide a method of manufacturing a phase change memory device capable of reducing heat loss of a phase change material layer and a change in state of a program region of the phase change material layer.

According to an aspect of the present invention, there is provided a method of manufacturing a phase change memory device, the method including: providing a semiconductor substrate having a lower electrode contact formed thereon, forming a phase change pattern layer on the lower electrode contact; In order to enhance the adhesion of the phase change pattern layer, the entire structure includes a step of performing a heat treatment process.

According to the present invention, deterioration of the phase change memory device can be prevented by improving the adhesion of the interface between the lower electrode contact and the phase change material layer through ultraviolet heat treatment.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A through 2D are cross-sectional views of processes of a phase change memory device formed in accordance with an embodiment of the present invention.

First, an impurity region 100a is formed on the semiconductor substrate 100 illustrated in FIG. 2A. After forming the first interlayer insulating layer 110 on the semiconductor substrate 100 on which the impurity region 100a is formed, the switching element 120 is in contact with the impurity region 100a in the first interlayer insulating layer 110. To form. In the exemplary embodiment of the present invention, a PN diode is used as the switching element 120.

An ohmic contact layer 130 may be formed on the switching element 120. In the present invention, cobalt silicide (CoSi ₂ ) is used as the ohmic contact layer 130 material.

Next, after the second interlayer insulating layer 140 is formed on the entire structure, the contact hole 141 selectively exposes the ohmic contact layer 130 by partially etching the second interlayer insulating layer 140. ).

The interlayer insulating layers 110 and 140 may be, for example, oxides using Tetra Ethly Ortho Silicate (TEOS), Undoped Silcate Glass (USG), or High Density Plasma-CVD (HDP-CVD), or a composite layer of oxide and nitride. Can be.

Then, as illustrated in FIG. 2B, a conductive material such as titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), or the like is deposited on the lower electrode contact hole 141 to form a lower electrode contact layer ( 150). The lower electrode contact layer 150 is deposited on the lower surface and sidewalls of the lower electrode contact hole 141 and on the second interlayer insulating layer 140.

Then, the inside of the lower electrode contact hole 141 in which the lower electrode contact layer 150 is formed is filled using a fluid insulating layer 160 such as spin-on dielectric (SOD).

In other words, when the lower electrode contact layer 150 fills the inside of the lower electrode contact hole 141 formed on the sidewall with a conventional general insulator (eg, a silicon oxide film), the inside of the lower electrode contact hole 141 may be completely filled with an insulator. It is not filled, and a void is formed in the middle. Therefore, in order to fill the lower electrode contact hole 141 without a void, the buried property is excellent and the inside of the lower electrode contact hole 141 is formed by using a fluid insulating layer 160 such as liquid spin-on dielectric (SOD). Filling is preferred.

Since the fluid insulating layer 160 is a liquid phase, the inside of the lower electrode contact hole 141 is filled by spin coating, and subsequently, cross-linking and densification of the SOD insulating layer 160 are performed through an annealing process. Can be.

At this time, in addition to the fluid insulating film 160 such as the SOD insulating film, HDP (High Density Plasma) insulating film, O3 Undoped Silcate Glass (O3 USG), Tetra Ethyl Ortho Silicate (TEOS), High temp, low pressure dielectric You can also use).

Then, as shown in FIG. 2C, the lower electrode contact layer 150 and the fluid insulating layer 160 on the second interlayer insulating layer 140 are planarized to form the lower electrode contact layer 150 in the contact hole 141. And the fluid insulating film 160 is embedded. In this case, anisotropic etching and chemical mechanical polishing (CMP) may be used as the planarization method.

Next, a silicon nitride oxide layer (SiON) 190 is sequentially deposited as a phase change material layer 170, an upper electrode layer 180, and a hard mask layer on the entire structure, and the photoresist pattern is formed on the silicon nitride oxide layer 190. After forming (not shown), a phase change pattern layer 195 is formed through an etching process.

In this case, an interface between the phase change material layer 170 and the lower electrode contact 160 may be formed in an excited state as shown in 70 of FIG. 1B. Therefore, in the present invention, after the phase change pattern layer is formed, the heat treatment process 200 is performed to improve the interface contact characteristics. For example, the heat treatment is performed by injecting an annealing gas at a temperature in the range of 150 ° C. to 220 ° C. as an ultraviolet lamp type for a time of about 90 seconds to about 120 seconds. The gas injected into the chamber during the UV heat treatment 200 is an inert gas, and in the present invention, nitrogen (N ₂ ) gas is used.

By the UV heat treatment 200, the adhesion of the contact interface between the phase change material layer 170 and the lower electrode contact 150 may be improved to reduce specific resistivity that may occur in the program region to several kΩ.

In addition, since the ultraviolet heat treatment 200 can be carried out at a low temperature as described above, it is possible to improve the adhesion without changing the physical properties of the phase change material layer. In addition, after the phase change material layer is deposited, a UV exposure process may be performed on the phase change material layer to prevent the phase change material layer from being changed by other material layers. Unchanged physical properties Temperature range can generally be heated within the range of 50 ~ 450 degrees.

In addition, the flowable insulating layer 160 is densified by the heat treatment process 200, thereby reducing voids such as voids in an area surrounded by the lower electrode contact 150.

In this case, as illustrated in FIG. 2D, a passivation film 211 is formed to prevent a phase change attack that may occur on the sidewall of the phase change material layer 170 by the heat treatment process.

The passivation film 211 is formed on the sidewall of the phase change material layer 170 by naturally forming the phase change pattern layer 195 by an etching process and then by the ultraviolet heat treatment process. The passivation film 211 may include the same component as the phase change material layer 170.

Next, after the capping film 215 is formed on the entire structure to a predetermined thickness, a subsequent process is performed.

The phase change material layer 170 includes Group 5A-antimony-tellurium, such as germanium, arsenic, tin, indium, germanium, tantalum, niobium to vanadium, and the like. Group 6A elements, such as tungsten, molybdenum to chromium, and antimony- It may be composed of telelium, Group 5A element-antimony-selenium, Group 6A element-antimony-selenide, and the like, and the phase change material layer 160 may be a physical vapor deposition (PVD) method, chemical vapor deposition. (Chemical Vapor Deposition; CVD) method, Atomic Layer Deposition (ALD) method can be formed using. The present invention is deposited using a sputtering process, which is a physical vapor deposition (PVD) method when depositing a phase change material layer.

Therefore, according to the present invention, the adhesion failure phenomenon that occurred at the contact interface between the phase change material layer and the lower electrode contact layer of the general phase change memory device is changed by using the ultraviolet heat treatment method. By suppressing the excitation between the contact interface with and, it is possible to reduce the specific resistance increase and the heat loss caused by the poor adhesion. Accordingly, deterioration of the phase change memory device can be prevented.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1A is a cross-sectional view illustrating a general phase change memory device;

FIG. 1B is an enlarged cross-sectional view of an interface between a lower electrode contact and a phase change pattern layer illustrated in FIG. 1A, and

2A through 2D are cross-sectional views of processes of a phase change memory device formed in accordance with an embodiment of the present invention.

<Detailed description of the main reference numerals>

195: phase change pattern layer 200: ultraviolet heat treatment

211: passivation film 215: capping film

Claims (12)

Providing a semiconductor substrate having a bottom electrode contact formed thereon; Forming a phase change pattern layer on the lower electrode contact; Performing a heat treatment process on the entire structure to enhance adhesion between the lower electrode contacts and the phase change pattern layer; And And forming a passivation film on a portion of the sidewalls of the phase change pattern layer during the heat treatment process. delete Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, After the heat treatment process step, the method of manufacturing a phase change memory device further comprising the step of forming a capping film on the entire structure. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Forming the lower electrode contact, Forming an interlayer insulating layer on the semiconductor substrate; Patterning the interlayer insulating layer to form a contact hole; Forming a conductive material on the bottom and sidewalls of the contact hole; And Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein And the insulating material is a fluid insulating film, and the buried fluid insulating film is densified by the heat treatment process. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The heat treatment process is a manufacturing method of a phase change memory device, characterized in that to proceed with an ultraviolet heat treatment process. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The method of manufacturing a phase change memory device according to claim 1, wherein nitrogen gas is used in the ultraviolet heat treatment process. Claim 8 was abandoned when the registration fee was paid. The method of claim 6, The ultraviolet heat treatment process is a method of manufacturing a phase change memory device, characterized in that at a temperature in the range of 150 ℃ ~ 220 ℃. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 6, The ultraviolet heat treatment process is a manufacturing method of a phase change memory device, characterized in that performed for a time within the range of 90 seconds to 120 seconds. Forming a cylindrical lower electrode contact in which a fluid insulating film is embedded on the semiconductor substrate; Forming a phase change material layer on the lower electrode contact and the fluid insulating layer; Heat-treating the semiconductor substrate product on which the phase change material layer is formed within a preset temperature range; And And forming a passivation film on a portion of the sidewalls of the phase change pattern layer during the heat treatment process. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, The temperature range is a method of manufacturing a phase change memory device, characterized in that the temperature in the range of 150 ℃ to 220 ℃. Claim 12 was abandoned upon payment of a registration fee. 11. The method of claim 10, The heat treatment is a method of manufacturing a phase change memory device, characterized in that the ultraviolet heat treatment.

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