KR20100085849A - Solid-state image device, method for producing the same, and image pickup apparatus - Google Patents

Abstract

PURPOSE: A solid state imaging device, a manufacturing method thereof, and an imaging device are provided to suppress a dark current by including a photoelectric conversion layer with a high light absorption coefficient. CONSTITUTION: A solid state imaging device(1) comprises a silicon substrate(11) and a photoelectric conversion layer(13). The photoelectric conversion layer is formed on the silicon substrate and is lattice-matched on the silicon substrate. The photoelectric conversion layer is made of chalcopyrite-based chemical semiconductor. The photoelectric conversion layer includes first to third photoelectric conversion layers. The first to third photoelectric conversion layers split light into red, green, and blue elements.

Description

Solid-state imaging device, manufacturing method, and imaging device {SOLID-STATE IMAGE DEVICE, METHOD FOR PRODUCING THE SAME, AND IMAGE PICKUP APPARATUS}

This invention relates to a solid-state imaging device, its manufacturing method, and an imaging device.

With multiple pixels, developments for reducing the pixel size are in progress. On the other hand, the development which improves a moving image characteristic by high speed imaging is also progressing simultaneously. When the pixels are reduced in this way or imaged at high speed, the number of photons incident on one pixel is reduced, and the sensitivity is lowered.

In addition, for surveillance cameras, there is a demand for a camera that can shoot in a dark place. In other words, a high sensitivity sensor is required.

In addition, in an ordinary Bayer array image sensor, since pixels are divided for each color, demosaicing processing (arithmetic processing for producing the color of the pixel from the color of the surrounding pixel) is required. For this reason, there is a drawback that a false color appears.

In such a request, there is a report that a CuInGaSe ₂ film is applied to an image sensor as a photoelectric conversion layer having a high light absorption coefficient, thereby achieving high sensitivity (for example, Japanese Patent Application Laid-Open No. 2007-123720 and 2008 Spring Application). See 29p-ZC-12 (2008). However, this photoelectric conversion layer is basically polycrystalline because crystals grow on the electrode. Therefore, generation of dark current due to crystal defects becomes remarkable. In addition, it is impossible to spectroscopy as it is.

On the other hand, as a method without demosaicing and without false color, a method of spectroscopy using a difference in absorption coefficient of silicon by wavelength has been proposed (for example, see US Patent No. 5965875).

In this method, there are many mixed colors and the color reproducibility is bad.

That is, in the structure described in US Patent No. 5965875 using the difference in absorption coefficient by wavelength, the amount of light that can be detected theoretically does not decrease. However, in the layer which detects blue light, since some red light and green light are absorbed when red light and green light pass, those light will be detected as blue light. For this reason, even if the blue signal is not originally present, the green light and the red signal enter the blue signal, thereby producing a false signal. Therefore, it is difficult to obtain sufficient color reproducibility.

In order to avoid the above-mentioned signal, it is necessary to perform signal processing by calculation in all three primary colors and to correct it, so a circuit necessary for the calculation is necessary separately. For this reason, the circuit configuration is complicated and large-scale as well as the cost for the circuit. For example, when any one of the three primary colors saturates, the original value of the saturated light becomes unknown, resulting in a problem in calculation, and as a result, the signal is processed to be different from the original color. In addition, since the signal is read using the plug, a plug area is required separately, and the area of the photodiode is reduced, which is not suitable for miniaturization of pixels.

By the way, as shown in FIG. 46, most semiconductors have absorption sensitivity with respect to infrared light. Therefore, for example, in a solid-state imaging device (image sensor) in which a silicon (Si) semiconductor is used, it is usually necessary to put an infrared cut filter in front of the sensor as an example of a dark blue filter. A sensor is proposed to solve the problem of the structure using the difference in absorption coefficient due to the wavelength. This sensor has good light quantity conversion efficiency and color separation by using a band gap without using a dark blue filter. In addition, each light of three primary colors can be detected by one sensor (for example, see Japanese Patent Application Laid-Open No. Hei 1-51262). The image sensor disclosed in these has a structure which changed the band gap in the depth direction.

In the invention described in Japanese Patent Application Laid-Open No. Hei 1-51262, color separation is performed by sequentially stacking materials having different band gaps (Eg) on a glass substrate in a depth direction of a semiconductor layer. However, for example, in the color classification of blue (B), green (G), and red (R), it is stated that the lamination is performed such that Eg (B)> Eg (G)> Eg (R). There is no description of specific materials.

On the other hand, Japanese Unexamined Patent Application Publication No. 3-289523 describes color separation using a SiC material, and Japanese Unexamined Patent Application Publication No. 6-209107 discloses an AlGaInAs or AlGaAs material.

However, in Japanese Patent Laid-Open Nos. 3-289523 and 6-209107, there is no description of crystallinity in heterojunction of other materials.

In the case where materials of different crystal structures are bonded together, mispit dislocations are generated due to differences in lattice constants, and crystallinity deteriorates. As a result, electrons trapped at the defect level formed in the band gap are discharged to cause the dark current.

As a method of improving this, spectroscopy by band gap control on a silicon (Si) substrate is proposed (for example, see Japanese Patent Laid-Open No. 2006-245088). The SiCGe-based mixed crystal and Si / SiC superlattice, not the lattice matching system, are fabricated on the Si substrate, and the absorption coefficient of silicon (Si) is low. Therefore, there is a problem that dark current easily occurs because crystal defects easily enter. In addition, although the use of a gallium arsenide (GaAs) substrate has been proposed, the GaAs substrate has a high cost and is inferior to a silicon (Si) substrate as a general image sensor.

In addition, one example of an attempt to increase the sensitivity is signal amplification by avalanche multiplication. For example, attempts have been made to multiply photoelectrons by applying high voltages (see, for example, IEEE Transactions Electron Devices Vol. 44, No. 10 October 1997). In this case, since a high voltage of 40 V is applied to multiply the photoelectrons, miniaturization of the pixels becomes difficult due to crosstalk and the like. In this sensor, the pixel size was 11.5 μm × 13.5 μm.

In addition, other avalanche multiplication image sensors (see, for example, IEEE J. Solid-State Circuits, 40, 1847, (2005)) require the application of a voltage of 25.5 V for multiplication, and also crosstalk ( In order to avoid crosstalk, a wide guard-ring layer or the like is required, and the pixel size needs to be increased to 58 mu m x 58 mu m.

The problem to be solved is that the number of photons incident on one pixel decreases due to the demand for making the pixel small due to multiple pixels, the demand for imaging at high speed, and the need for imaging in a dark place, and the sensitivity is lowered. to be.

This invention enables the solid-state imaging device which suppresses generation | occurrence | production of a dark current and raises sensitivity by having a photoelectric conversion layer with a good crystallinity and a high light absorption coefficient.

The solid-state imaging device of the present invention includes a photoelectric conversion layer formed by lattice matching on a silicon substrate and a silicon substrate. The photoelectric conversion layer is composed of a copper-aluminum-gallium-indium-sulfur-selenide (CuAlGaInSSe) mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenide (CuAlGaInZnSSe) mixed crystal. It consists of a semiconductor.

The solid-state imaging device of the present invention includes a photoelectric conversion layer formed by lattice matching on a silicon substrate and a silicon substrate. The photoelectric conversion layer is made of a chalcopyrite-based compound semiconductor composed of a CuAlGaInSSe-based mixed crystal or a CuAlGaInZnSSe-based mixed crystal. As a result, the generation of dark current is suppressed and the sensitivity is increased. Therefore, there is an advantage that a high sensitivity image having excellent image quality can be obtained.

The manufacturing method of the solid-state imaging device of the present invention includes a step of forming a lattice matched photoelectric conversion layer on a silicon substrate, the photoelectric conversion layer being a copper-aluminum-gallium-indium-sulfur-selenide (CuAlGaInSSe) -based mixed crystal. Or a chalcopyrite-based compound semiconductor composed of a copper-aluminum-gallium-indium-zinc-sulfur-selenium (CuAlGaInZnSSe) -based mixed crystal.

In the manufacturing method of the solid-state imaging device of the present invention, a photoelectric conversion layer is formed on a silicon substrate by lattice matching and consists of a chalcoprite-based compound semiconductor composed of CuAlGaInSSe-based mixed crystals or CuAlGaInZnSSe-based mixed crystals. As a result, the generation of dark current is suppressed and the sensitivity is increased. Therefore, there is an advantage that a high sensitivity image having excellent image quality can be obtained.

The imaging device of the present invention includes a condensing optical system that focuses incident light, a solid-state imaging device that receives and photoelectrically converts the light condensed by the condensing optical system, and a signal processing unit that processes the photoelectrically converted signal. The imaging device is formed by lattice matching on a silicon substrate and is made of a copper-aluminum-gallium-indium-sulfur-selenide (CuAlGaInSSe) -based crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenide (CuAlGaInZnSSe) -based crystal It has a photoelectric conversion layer which consists of a copyrite-type compound semiconductor.

In the imaging device of the present invention, a solid-state imaging device is formed by lattice matching on a silicon substrate, and has a photoelectric conversion layer made of a chalcoprite-based compound semiconductor composed of CuAlGaInSSe-based mixed crystals or CuAlGaInZnSSe-based mixed crystals. As a result, since the generation of dark current is suppressed, deterioration in image quality due to white spots is suppressed, and the sensitivity of the solid-state imaging device is increased, so that high sensitivity imaging is possible. Therefore, high sensitivity imaging and suppression of image quality deterioration enable high sensitivity imaging even in a dark environment such as at night.

1 is a schematic configuration sectional view showing a first example of a solid-state imaging device according to a first embodiment of the present invention.
Figure 2 is a schematic structural diagram showing a chalcopyrite-based mixed crystal.
3 is a relation between a band gap and a lattice constant of a chalcopite-based material.
4 is a relation diagram of a band gap and a lattice constant of a chalcopide-based material.
FIG. 5 is a schematic sectional view showing an example of a photoelectric conversion layer of a chalcopide-based material. FIG.
6 is a schematic cross-sectional view showing an example of a photoelectric conversion layer of a chalcopide-based material using a superlattice.
Fig. 7 is a diagram showing a relationship between an absorption coefficient α and a wavelength predicted from a band gap.
8 is a schematic sectional view of an example of a solid-state imaging device of the present invention in which spectral sensitivity characteristics are measured.
9 is a spectral sensitivity characteristic diagram of an example of a solid-state imaging device of the present invention.
10 is a schematic sectional view of an example of a conventional solid-state imaging device having measured spectral sensitivity characteristics.
11 is a spectral sensitivity characteristic diagram of an example of a conventional solid-state imaging device.
12 is a schematic configuration sectional view showing a second example of a solid-state imaging device according to a second embodiment of the present invention.
13 is a circuit diagram showing an example of a read circuit.
14 is a band diagram of a solid-state imaging device according to the second embodiment.
Fig. 15 is a band diagram when an R signal is read.
Fig. 16 is a band diagram when reading a G signal.
17 is a band diagram when reading a B signal.
18 is a schematic sectional view showing a modification example using a reading electrode in the solid-state imaging device according to the second embodiment.
Fig. 19 is a band diagram at the time of zero bias of the solid-state imaging device in the third embodiment of the present invention.
Fig. 20 is a band diagram of reverse biasing of the solid-state imaging device according to the third embodiment of the present invention.
Fig. 21 is a schematic sectional view showing the third example of the solid-state imaging device according to the third embodiment of the present invention.
22 is a circuit diagram showing an example of a read circuit.
Fig. 23 is a band diagram of the solid-state imaging device in the third embodiment of the present invention.
Fig. 24 is a schematic sectional view showing the fourth example of the solid-state imaging device according to the fourth embodiment of the present invention.
25 is a band diagram of a solid-state imaging device according to a fourth embodiment of the present invention.
Fig. 26 is a schematic sectional view showing the fifth example of the solid-state imaging device according to the fifth embodiment of the present invention.
27 is a spectral sensitivity characteristic diagram of the solid-state imaging device according to the fifth embodiment.
Fig. 28 is a relationship diagram between a band gap and a lattice constant of one example of the solid-state imaging device according to the sixth embodiment of the present invention.
29 is a schematic sectional view showing the sixth example of the solid-state imaging device according to the sixth embodiment of the present invention.
30 is a schematic sectional view showing the seventh example of the solid-state imaging device according to the seventh embodiment of the present invention.
31 is a circuit diagram showing an example of a read circuit.
32 is a schematic sectional view showing the modification 1 of the seventh example of a solid-state imaging device.
33 is a schematic sectional view illustrating Modification Example 2 of the seventh example of the solid-state imaging device.
34 is a circuit block diagram showing a CMOS image sensor to which a solid-state imaging device is applied.
35 is a block diagram showing a CCD to which a solid-state imaging device is applied.
36 is a schematic sectional view showing the fifth example of the method of manufacturing a solid-state imaging device according to the twelfth embodiment of the present invention.
37 is a relationship diagram between a band gap and a lattice constant of the solid-state imaging device according to the twelfth embodiment.
38 is a schematic sectional view showing one example of the configuration of a solid-state imaging device for hole reading.
39 is a schematic sectional view showing one example of the configuration of a solid-state imaging device for hole reading.
40 is a schematic sectional view showing one example of the configuration of a solid-state imaging device for hole reading.
Fig. 41 is a schematic sectional view showing one example of the configuration of a solid-state imaging device for hole reading.
42 is a schematic sectional view showing one example of the configuration of a solid-state imaging device for hole reading.
43 is a block diagram showing an example of a MOCVD apparatus.
44 is a schematic structural diagram showing an example of an MBE apparatus;
45 is a block diagram showing an embodiment of the imaging device of the present invention.
Fig. 46 is a light absorption spectrum diagram of a semiconductor.

<1. First embodiment>

[First Example of Configuration of Solid-State Imaging Device]

The 1st example of the solid-state imaging device which concerns on 1st Embodiment of this invention is demonstrated with schematic sectional drawing of FIG.

As shown in FIG. 1, the first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, an n-type silicon region formed in the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a chalcoprite-based compound semiconductor composed of a lattice-matched and copper-aluminum-gallium-indium-sulfur-selenium (hereinafter referred to as CuAlGaInSSe) based crystals Is formed. Copper-aluminum-gallium-indium-zinc-sulfur-selenium (hereinafter, referred to as CuAlGaInZnSSe) -based mixed crystals may also be used as the chalcoidite compound semiconductor. On the photoelectric conversion layer 13, a second electrode layer 14 having light transparency is formed. The second electrode layer 14 is formed of a transparent electrode material such as indium tin oxide (ITO), zinc oxide, indium zinc oxide, or the like. The solid-state imaging device (image sensor) 1 has a basic configuration as described above.

The photoelectric conversion layer 13 made of the chalcopide-based compound semiconductor that performs RGB spectroscopy in the depth direction is formed to lattice match on the silicon substrate 11.

By lattice matching and epitaxial growth on a Si (100) substrate with a mixed crystal of a chalcopyrite-based material having a high light absorption coefficient, crystallinity is improved, and as a result, a highly sensitive solid-state imaging device 1 having a low dark current is provided. .

The chalcopite structure is shown in FIG. As an example, FIG. 2 shows an example of CuInSe ₂ which is one of the chalcoprite materials.

As shown in FIG. 2, the CuInSe ₂ has a diamond structure as a basic type like silicon (Si). Therefore, a part of a silicon atom is substituted by copper (Cu), indium (In), gallium (Ga), etc., and the chalcopite structure is formed. Therefore, epitaxial growth on a silicon substrate is basically possible. As the epitaxial growth method, for example, Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Liquid Phase Epitaxy (LPE), etc. There is this. In other words, any method of film formation may be used as long as it is an epitaxial growth method.

The band gap and lattice constant of the chalcopyrite-based material are shown in FIG. 3.

As shown in FIG. 3, the lattice constant a of silicon (Si) is a = 5.431 (shown with a dashed-dotted line in drawing). As a mixed crystal which can be formed by lattice matching to the lattice constant value, there is a CuAlGaInSSe-based mixed crystal, and when the CuAlGaInSSe-based mixed crystal is used, epitaxial growth is possible on the silicon 100 substrate.

As shown in Fig. 4, the band gap can be controlled by changing the composition under the condition of lattice constant (a) = 5.431 (indicated by a dashed line in the figure), so that it is also possible to grow a film for RGB spectroscopy. Become. Hereinafter, it demonstrates that R is red, G is green, and B is blue. For example, the use of CuGa _{0 .52} In _{0 .48} S ₂ as a photoelectric conversion material for R spectroscopy. As G spectral photoelectric conversion material for use _{CuAl 0 .24 Ga 0 .23 In 0} .53 S 2. Also uses B as a photoelectric conversion material for spectroscopic, CuAl _{.28 0 .36 0 .64} Ga ₁ S Se _{0 .72.} In this case, each band gap is 2.00 eV, 2.20 eV, and 2.51 eV. At this time, as shown in FIG. 5, by laminating in order of the R-spectral photoelectric conversion material, the G-spectral photoelectric conversion material, and the B-spectral photoelectric conversion material on the silicon substrate 11, spectroscopy in the depth direction becomes possible. .

Thus, as a band gap area | region which can spectrograph in a depth direction, when considering photon energy of RGB, it becomes as follows. That is, the photoelectric conversion layer 13 shown in FIG. 1 includes a first photoelectric conversion layer 21 for spectroscopy of red light, a second photoelectric conversion layer 22 for spectra of green light, and a third for spectroscopy of blue light. It is formed of the photoelectric conversion layer 23. The first photoelectric conversion layer 21 may have a band gap in the range of 2.00 eV ± 0.1 eV (wavelength of 590 nm to 650 nm). The second photoelectric conversion layer 22 may have a band gap in the range of 2.20 eV ± 0.15 eV (wavelengths of 530 nm to 605 nm). The third photoelectric conversion layer 23 may have a band gap in the range of 2.51 eV ± 0.2 eV (wavelengths of 460 nm to 535 nm).

At this time, the first photoelectric conversion layer 21 is CuAl _x Ga _y In _z S ₂ , and 0 + x ≦ 0.12, 0.38 ≦ y ≦ 0.52, 0.48 ≦ z ≦ 0.50 and x + y + z. = 1. The second photoelectric conversion layer 22 is CuAl _x Ga _y In _z S ₂ , and 0.06 ≦ x ≦ 0.41, 0.01 ≦ y ≦ 0.45, 0.49 ≦ z ≦ 0.58 and x + y + z = 1. The third photoelectric conversion layer 23 is CuAl _x Ga _y S _u Se _v , further 0.31 ≦ x ≦ 0.52, 0.48 ≦ y ≦ 0.69, 1.33 ≦ _u ≦ 1.38, 0.62 ≦ _v ≦ 0.67, and x + y + u + v = 3 (or x + y = 1 and u + v = 2). In FIG. 1, an example of each is shown.

[Modifications of Solid-State Imaging Apparatus (Application of Superlattice)]

By the way, depending on the constraints and epitaxial growth conditions of the epitaxial growth apparatus, some or all of the layers of the chalcopite-based RGB photoelectric conversion layer may be in solid solution and cannot be crystal-grown. have.

In that case, as shown in FIG. 6, it is also possible to grow using a superlattice within a critical film thickness. For example, in the growth of CuGa _X In _{1 - X} S _2, the growable CuGaS ₂ layer 32 and the CuInS ₂ layer 31 are alternately grown on the silicon substrate 11 to within the critical film thickness.

At this time, by controlling the thickness of each layer, it is possible to design so that the total composition ratio becomes a desired composition ratio, and a pseudo mixed crystal can be formed. The reason why each layer of the superlattice is set within the critical film thickness hc is to avoid this because film formation exceeding the critical film thickness hc causes defects in mispit dislocations and impairs crystallinity. . As the definition of the critical film thickness, it is defined by the equation of Matthews-Blakeslee in the figure.

In addition, when a wide band gap material is used as the photoelectric conversion layer, generation of carriers due to heat is suppressed, whereby thermal noise is reduced, and as a result, a good image can be provided.

By the way, in the crystal growth method, a portion of a transistor, a readout circuit, a wiring, or the like is previously covered with a material such as silicon oxide (SiO ₂ ), silicon nitride (SiN), and at least a portion of the silicon substrate is exposed to the photoelectric. The conversion layer 13 may be grown. After that, the photoelectric conversion layer 13 may be grown almost on the entire surface by growing in the lateral direction on the surface of a material such as silicon oxide or silicon nitride.

At this time, RGB spectroscopy is also favorable and mixing color becomes small. The wavelength dependence of the absorption coefficient α predicted from the band gap of this material is shown in FIG.

As shown in FIG. 7, it can be seen that the absorption coefficient α is steeply reduced with the photon energy on the lower energy side than the band gap.

[Comparison of Characteristics]

Next, the spectral sensitivity characteristic of one example of the solid-state imaging device of the present invention is shown. As an example, as the light sensitivity characteristic, one having a configuration spectroscopically in the depth direction shown in FIG. 8 was used. That is, the first photoelectric conversion layer 21 of the photoelectric conversion layer 13 has a thickness that was used CuGa _{0 .52} In _{0 .48} S ₂ film of 0.8㎛. Further it was used the second photoelectric conversion layer 22, the thickness of _{0.7㎛ CuAl 0 .24 Ga 0 .23 In} 0 .53 S 2 of the film. The third photoelectric conversion layer to 23, Se _{0 .28 0 .36} CuAl the thickness 0.3㎛ Ga _{0 .64} S _{1. 72} was used.

As shown in FIG. 9, the spectral sensitivity characteristics of the photoelectric conversion layer 13 having the above-described configuration have good separation of each color of the R light, the G light, and the B light, and show that the mixed color is small.

On the other hand, in the structure spectroscopically described in the depth direction described in the above-mentioned US Patent No. 5965875, for example, as shown in FIG. 10, the R-spectral photoelectric conversion layer 121 has a Si layer of 2.6 mu m thickness. Formed. In the G-spectral photoelectric conversion layer 122, the Si layer is formed to a thickness of 1.7 mu m. In the B-spectral photoelectric conversion layer 123, the Si layer is formed to a thickness of 0.6 mu m. That is, the film thickness of the photoelectric conversion layer 113 is 4.9 micrometers.

As shown in FIG. 11, the spectral sensitivity characteristics of the photoelectric conversion layer 113 are poor in separation of each color of the R light, the G light, and the B light, and have a large spectral sensitivity characteristic.

The solid-state imaging device 1 can perform spectroscopy with good color separation without using an on-chip color filter (OCCF), and does not cut light like an on-chip color filter (OCCF). This is high and the sensitivity is also high.

In addition, since information of three colors of RGB is obtained in one pixel, demosaicing processing becomes unnecessary, and there is no generation of false colors in principle, resulting in high resolution.

At the same time, the low-pass filter becomes unnecessary, and there is a cost merit.

In addition, since lattice matching is performed on the silicon (Si) substrate, crystal defects do not enter even when the crystal is grown thick. Therefore, the dark current is small.

By the way, the invention of Japanese Patent Laid-Open No. 2006-245088 (Japanese Patent Laid-Open No. 2006-245088) manufactures a SiCGe-based mixed crystal and a Si / SiC superlattice on a silicon (Si) substrate. In this configuration, since the absorption coefficient of silicon (Si) is low, it is necessary to form thick for spectroscopy, and therefore crystal defects tend to enter. In addition, although mention is also made of crystal growth on a GaAs substrate, in the case of GaAs, Ga elements are small as resources and the substrate cost is high. In addition, the toxicity to the substrate adversely affects the environment.

<2. Second Embodiment>

[2nd example of the structure of a solid-state imaging device]

Next, the 2nd example of the solid-state imaging device which concerns on 2nd Embodiment of this invention is demonstrated with the schematic block sectional drawing of FIG. 12, the circuit diagram of the signal reading of FIG. 13, and the band diagram in the zero bias state of FIG. do. Here, a structure for causing signal reading and avalanche multiplication at the same time will be described.

As shown in FIG. 12 and FIG. 13, the silicon substrate 11 is formed of a p-type silicon substrate. The first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, an n-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, first electrode layer 12 _{on, i-CuGa 0.52 In 0.48 S} 2 film, the first photoelectric conversion layer (21), i-CuAl Ga _{0 .24 0 .23 0 .53} In S ₂ film a second photoelectric conversion layer _{(22), p-CuAl 0} .36 Ga 0 .64 S 1 .28 third photoelectric conversion layer 23 are sequentially stacked of Se _{0 .72,} is formed. On the photoelectric conversion layer 13, a second electrode layer 14 having light transparency is formed. The second electrode layer 14 is formed of a transparent electrode material such as indium tin oxide (ITO), zinc oxide, indium zinc oxide, or the like.

However, the photoelectric conversion layer 13 has a p-i-n structure as a whole.

The first electrode layer 12 is provided with a read electrode 15, and the silicon substrate 11 has a read circuit 51 for reading in the direction of the arrow through the gate MOS 41. The gate MOS 41 has a structure in which a gate electrode is formed on the gate insulating film, and the gate MOS described below has the same structure.

In the readout circuit 51, the diffusion layer of the reset transistor M ₁ and the gate electrode of the amplifying transistor M ₂ are connected to the floating diffusion portion FD connected to the photoelectric conversion layer 13. Further, a selection transistor M3 having a common diffusion layer of the amplifying transistor M ₂ is connected. An output line is connected to the diffusion layer of the selection transistor M ₃ .

The solid-state imaging device (image sensor) 2 has a structure as described above.

Next, as shown in the band diagram of FIG. 14, since the photoelectric conversion layer 13 has a p-i-n structure, the band is inclined by an internal electric field. Because of this inclination, the electron-hole pairs generated by light irradiation are spatially separated into electrons and holes.

Further, spike-like barriers by continuous composition control are formed on the wide gap side near the interface of each of the three layers, respectively, under the conditions of _B B ≥ B _G ≥ B _R > kT (= 26 meV), whereby the photoelectrons are trapped and for each RGB Accumulation is possible (photoelectron accumulation). Where k is the Boltzmann constant and kT corresponds to the thermal energy at room temperature.

In addition, without the above-mentioned barrier, since carriers naturally move from a layer having a high band gap to a layer having a low band gap, accumulation by RGB becomes impossible.

In such a solid-state imaging device 2, as shown in FIG. 15, only the R signal can be read first by applying the reverse bias V _R. The G and B signals are trapped by spike-like barriers.

At this time, an energy step of the conduction band is originally present between the n-type silicon layer of the first electrode layer 12 and the i-CuGa _0.52 In _0.48 S ₂ film of the first photoelectric conversion layer 21. For this reason, even with a low voltage application, by giving a large kinetic energy to the lattice by collision, a new electron-hole pair by ionization is generated, and avalanche multiplication occurs.

Further, for signal reading, once the charge is accumulated in the n-type silicon layer of the first electrode layer 12, the signal is read from the read circuit 51 side using the gate MOS 41. 16 and 17, by sequentially applying voltages in the order of V _G and V _B , it becomes possible to read the G signal and the B signal (only V _B > V _G > V _R ). . In this case as well as the energy level difference of the conduction band between the _{i-CuGa 0 .52 In 0 .48} S 2 film of the first electrode layer (12) n-type silicon layer and the first photoelectric conversion layer 21 of each knife Even with the effect of the energy step of the conduction band of the copyrite-based material, avalanche multiplication occurs similarly.

In such a reading method, since the plug structure as in Japanese Patent Laid-Open No. 2007-123720 (US Patent No. 5965875) is unnecessary, the photodiode area can be large. As a result, not only the sensitivity is improved but also the process is simplified, so that the cost is kept low.

By the way, as described above, the reading method using the gate MOS has been described. However, as shown in Fig. 18, the reading electrode 15 is formed on the n-type silicon layer of the first electrode layer 12 directly. May be read.

As described above, by changing the composition to control the band gap as in the solid-state imaging device 2, the spectroscopy in the RGB depth direction, the photoelectron accumulation, the signal reading by applying the three-stage voltage, and the reduction of the avalanche multiplication at the same time It becomes possible.

<3. Third embodiment>

[Third example of configuration of solid state imaging device]

In the above, the structure which spectroscopy in the depth direction and the structure which produces avalanche multiplication simultaneously were described. Next, as the third embodiment of the present invention, a simple avalanche multiplication structure is also possible, and examples thereof include a band diagram at zero bias in FIG. 19 and a band diagram at reverse bias in FIG. 20. Explain by.

As shown in FIG.19 and FIG.20, a big step | step can be obtained by changing a band gap continuously or stepwise. In this case, since the energy step of the conduction band becomes larger than in the case shown in FIGS. 14 to 17, a large avalanche multiplication is possible at a low driving voltage. In this case, color separation may be performed by attaching a color filter such as an on-chip color filter (OCCF) to the surface side.

In addition, as a method of reading a signal, as described above, not only a voltage is applied in the depth direction. For example, a signal can be read out by applying a voltage using the photoelectric conversion layer as a p-i-n structure or a pn structure. One example of this will be explained with reference to FIGS. 21 and 22.

As shown in FIG. 21, the silicon substrate 11 is formed of a p-type silicon substrate. The first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, an n-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, first electrode layer 12 from the, CuGa ₂ S _{0.48 0.52} In the first photoelectric conversion layer film (21), CuAl Ga _{0 .24 0 .23 0 .53} In the film ₂ S second photoelectric conversion layer (22), CuAl _{0 .36} is Ga _{0 .64} S _{1 .28} Se ₀ the third photoelectric conversion layer 23 of _0.72 is formed is stacked. In the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, each center portion is formed of an i layer, and one side thereof has a p layer and the other side. The side is formed by n layers. Therefore, it has a pin structure.

Alternatively, although not illustrated, each of the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23 has a p layer and the other side thereof. It is formed by n layers. Therefore, it has a pn structure.

Further, a p-type electrode (second electrode layer) layer 14p is formed on the p layer of the second photoelectric conversion layer 22 and the p layer of the third photoelectric conversion layer 23 of the photoelectric conversion layer 13. have. In addition, an n-type electrode (second electrode layer) layer 14n is formed on the n-layer of the second photoelectric conversion layer 22 and the n-layer of the third photoelectric conversion layer 23 of the photoelectric conversion layer 13. have. The p-type electrode layer 14p may not be necessary.

The silicon substrate 11 is provided with a read circuit 51 for reading in the direction of the arrow through the gate MOS 41.

As shown in FIG. 22, the read circuit 51 includes a diffusion layer of the reset transistor M ₁ and a gate electrode of the amplifying transistor M ₂ in the floating diffusion portion FD connected to the photoelectric conversion layer 13. Is connected. Further, a selection transistor M ₃ having a common diffusion layer of the amplifying transistor M ₂ is connected. An output line is connected to the diffusion layer of the selection transistor M ₃ .

The solid-state imaging device (image sensor) 3 has a structure as described above.

As described above, even when the photoelectric conversion layer 13 has a p-i-n structure or a pn structure, it is possible to read a signal by applying a voltage. Further, the signal can be read without necessarily applying the reverse bias.

In the solid-state imaging device 3 shown in FIG. 21, the band diagram shown in FIG. That is, a barrier by composition control is formed on the wide gap side near the interface of the second photoelectric conversion layer 22 / third photoelectric conversion layer 23 under the condition of B> kT (= 26 meV), whereby the photoelectron of B is trapped. It is possible to accumulate B photoelectrons. Similarly, a barrier by composition control is formed on the wide gap side near the interface of the first photoelectric conversion layer 21 / the second photoelectric conversion layer 22 under the condition of B> kT (= 26 meV), whereby G photoelectron Is trapped, allowing the accumulation of G photoelectrons. Regarding R, electrons move to the first electrode layer 12 side of the n-type silicon layer and are read by the gate MOS 41.

<4. Fourth embodiment>

[Fourth Example of Configuration of Solid-State Imaging Device]

Moreover, it is also possible to make the said solid-state imaging device 3 into the following structures. The configuration will be described below as a fourth embodiment of the present invention.

As shown in FIG. 24, the silicon substrate 11 is formed of a p-type silicon substrate. On the silicon substrate 11, a photoelectric conversion layer 13 including lattice matching and CuAlGaInSSe-based mixed crystals is formed. The photoelectric conversion layer 13, first electrode layer 12 from the, CuGa ₂ S _{0.48 0.52} In the first photoelectric conversion layer film (21), CuAl Ga _{0 .24 0 .23 0 .53} In the film ₂ S second photoelectric conversion layer (22), CuAl _{0 .36} is Ga _{0 .64} S _{1 .28} Se ₀ the third photoelectric conversion layer 23 of _0.72 is formed is stacked. In the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, each center portion is formed of an i layer, and one side thereof has a p layer and the other side. The side is formed by n layers. Therefore, it has a pin structure.

Alternatively, although not illustrated, each of the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23 has a p layer and the other side thereof. It is formed by n layers. Therefore, it has a pn structure.

In addition, p is on the p layer of the first photoelectric conversion layer 21 of the photoelectric conversion layer 13, p of the second photoelectric conversion layer 22 and p of the third photoelectric conversion layer 23, respectively. The type electrode (second electrode layer) layer 14p is formed. In addition, n is on the n layer of the first photoelectric conversion layer 21 of the photoelectric conversion layer 13, n of the second photoelectric conversion layer 22 and n of the third photoelectric conversion layer 23, respectively. The type electrode (second electrode layer) layer 14n is formed. The p-type electrode layer 14p may not be necessary.

In the silicon substrate 11, the first electrode layer 12 is formed on one side of the first photoelectric conversion layer 21, for example. The first electrode layer 12 is made of, for example, an n-type silicon layer formed on the silicon substrate 11. The n-type electrode layer 14n formed on the first photoelectric conversion layer 21 is connected to the electrode 17 formed on the first electrode layer 12 by, for example, a wiring 18. In the silicon substrate 11, a gate MOS 41 is formed adjacent to the first electrode layer 12, and through this gate MOS 41, a read circuit similar to that described in the circuit diagram of FIG. Is formed.

The solid-state imaging device (image sensor) 4 has a structure as described above.

The band diagram of the said solid-state imaging device 4 is demonstrated by FIG. As shown in FIG. 25, a barrier by composition control is formed on the wide gap side near the interface of the second photoelectric conversion layer 22 / third photoelectric conversion layer 23 under the condition of B> kT (= 26 meV). The photoelectrons of B are trapped, allowing the accumulation of photoelectrons of B. Similarly, a barrier by composition control is formed on the wide gap side near the interface of the first photoelectric conversion layer 21 / the second photoelectric conversion layer 22 under the condition of B> kT (= 26 meV), whereby G photoelectron Is trapped, allowing the accumulation of G photoelectrons. Similarly, a barrier by composition control is formed on the wide gap side near the interface of the first photoelectric conversion layer 21 / silicon substrate 11 under the condition of B> kT (= 26 meV). In addition, since the n electrode layer 14n is provided on the first photoelectric conversion layer 21, the electrons accumulated in the first photoelectric conversion layer 21 may be directly read.

Alternatively, all of the RGB may be accumulated in the silicon substrate 11 once and read out by the gate MOS 41. Here, although the p-type electrode layer 14p extracts holes, charge up can be avoided by directly attaching to the ground. Further, by setting the p-type concentration high, it is also possible to leave holes on the silicon substrate 11 side. In this case, the p-type electrode layer 14p is not necessarily necessary. In this structure, since there is no energy step except for reading R, avalanche multiplication is not necessarily caused by low voltage driving, but there is an advantage that the reading of signals can be performed simultaneously rather than sequentially as described above. have.

<5. Fifth Embodiment>

[Fifth Example of Configuration of Solid-State Imaging Device]

In the above description, although the first to third photoelectric conversion layers for spectroscopy are laminated in the depth direction, the lamination is not necessary. Next, as an example of the fifth embodiment of the solid-state imaging device according to the fifth embodiment of the present invention, the first photoelectric conversion layer to the third photoelectric conversion layer are not laminated. Explain.

As shown in Fig. 26, in the lateral direction, the first photoelectric conversion layer 21 for R spectra, the second photoelectric conversion layer 22 for G spectra, and the third photoelectric conversion layer 23 for B spectroscopy are You may arrange them in a row.

Hereinafter, this will be described in detail. The silicon substrate 11 is formed of a p-type silicon substrate. In this silicon substrate 11, a first electrode layer 12 is formed corresponding to a position where a photoelectric conversion layer for spectroscopically analyzing each color of RGB is formed. The first electrode layer 12 is made of, for example, an n-type silicon layer formed on the silicon substrate 11.

On the first electrode layer 12 at the R-split position, a first photoelectric conversion layer 21 made of lattice-matched CuAlGaInSSe-based mixed crystals is formed. The first photoelectric conversion layer 21 are formed of, for example, a CuGa _{0 .52} In _{0 .48} S ₂ film.

Further, on the first electrode layer 12 at the G-split position, a second photoelectric conversion layer 22 made of lattice matched CuAlGaInSSe-based mixed crystals is formed. The second photoelectric conversion layer 22 are formed of, for example, a _{CuAl 0 .24 Ga 0 .23 In 0} .53 S 2 film.

Further, a third photoelectric conversion layer 23 formed of lattice-matched CuAlGaInSSe-based mixed crystals is formed on the first electrode layer 12 at the B-split position. The third photoelectric conversion layer 23 are formed of, for example, a _{.28 CuAl 0 .36 Ga 0 .64 S} 1 Se 0 .72.

The thicknesses of the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23 are, for example, 0.8 μm, 0.7 μm, and 0.7 μm, respectively.

The second electrode layer 14 is formed on the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, respectively. This second electrode layer 14 is formed of the same transparent electrode as described in the first embodiment.

Accordingly, the first photoelectric conversion layer 24 formed by stacking the first electrode layer 12, the first photoelectric conversion layer 21, and the second electrode layer 14 is formed on the silicon substrate 11. Similarly, the 2nd photoelectric conversion layer 25 formed by laminating | stacking the 1st electrode layer 12, the 2nd photoelectric conversion layer 22, and the 2nd electrode layer 14 is formed. Similarly, the third photoelectric conversion layer 26 formed by stacking the first electrode layer 12, the third photoelectric conversion layer 23, and the second electrode layer 14 is formed. Accordingly, the first to third photoelectric conversion layers 24 to 26 are disposed on the silicon substrate 11 in the lateral direction.

In the solid-state imaging device 5 having the above-described configuration, the photocoil is naturally moved to the silicon substrate 11 (silicon) side by an energy difference without necessarily applying a reverse bias to the p-type chacopyrite-based material. The signal may be read out by the gate MOS 41 formed on the silicon substrate 11. This gate MOS 41 is formed in the silicon substrate 12 adjacent to each first electrode layer 12. With such a structure, the RGB signal can be read simultaneously.

Like the Bayer arrangement, the G resolution may be increased by increasing the number of G pixels. The spectral sensitivity characteristic in the case of this structure is shown in FIG.

As shown in Fig. 27, since the short wavelength side is not cut, for example, the following color calculation processing may be performed after demosaicing processing.

R = r-g, G = g-b, B = b

Here, r, g, and b are RAW data.

The above-described chalcopyrite-based material is a mixed crystal of CuAlGaInSSe system.

<6. Sixth embodiment>

[Sixth Example of Configuration of Solid-State Imaging Device]

Next, as a sixth example of the solid-state imaging device according to the sixth embodiment of the present invention, a case where a mixed crystal of, for example, CuGaInZnSSe system is used for the chalcopite-based material will be described. With such a CuGaInZnSSe-based mixed crystal, the same band gap control as described above can be performed, and the same effects as those of the respective solid-state imaging devices can be obtained.

28 shows the relationship between the band gap of the CuGaInZnSSe system and the lattice constant.

As shown in FIG. 28, it can be seen that CuGaInZnSSe-based mixed crystals can grow crystals while lattice matching on the silicon 100 substrate 11.

As a structure which has such a characteristic, RGB spectroscopy becomes possible by setting it as the cross-sectional structure shown in FIG. 29, for example.

As an example, as shown in FIG. 29, the first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, an n-type silicon region formed in the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a chalcopide-based compound semiconductor composed of CuAlGaInZnSSe-based mixed crystals is formed. On the photoelectric conversion layer 13, a second electrode layer 14 having transparency is formed. The second electrode layer 14 is formed of a transparent electrode material such as indium tin oxide (ITO), zinc oxide, indium zinc oxide, or the like. The solid-state imaging device (image sensor) 6 has a basic configuration as described above.

The photoelectric conversion layer 13 for RGB spectroscopy in the depth direction of the chalcopite system is formed on the silicon substrate 11 to be lattice matched.

By lattice matching and epitaxially growing on a Si (100) substrate with a mixed crystal of a chacopyrite-based material having a high light absorption coefficient, crystallinity is improved, and as a result, a highly sensitive solid-state imaging device (image sensor) having low dark current (6) ) Is provided.

The photoelectric conversion layer 13 includes a first photoelectric conversion layer 21 made of an R-spectral photoelectric conversion material, a second photoelectric conversion layer 22 made of a G-spectral photoelectric conversion material, and a B-spectral photoelectric conversion. The third photoelectric conversion layer 23 made of a material is laminated in this order.

For example, the use of CuGa _{0 .52} In _{0 .48} S ₂ as a photoelectric conversion material for R spectroscopy. _.39 CuGaIn G ₁ as the photoelectric conversion material for spectroscopic Se _{0. 6} is used. Further, CuGa _0.74 Zn _0.26 S _1.49 Se _0.51 is used as the photoelectric conversion material for B spectroscopy. Thus, by laminating | stacking on the silicon substrate 11 in order of the R-spectral photoelectric conversion material, the G-spectral photoelectric conversion material, and the B-spectral photoelectric conversion material, it becomes possible to spectroscopically in a depth direction.

Thus, as a band gap area | region which can spectrograph in a depth direction, when considering photon energy of RGB, it becomes as follows. That is, the first photoelectric conversion layer 21 may have a band gap in the range of 2.00 eV ± 0.1 eV (wavelength of 590 nm to 650 nm). The second photoelectric conversion layer 22 may have a band gap in the range of 2.20 eV ± 0.15 eV (wavelengths of 530 nm to 605 nm). The third photoelectric conversion layer 23 may have a band gap in the range of 2.51 eV ± 0.2 eV (wavelengths of 460 nm to 535 nm).

At this time, the composition range of the first photoelectric conversion layer 21 is CuGa _y In _z S _u Se _v, and 0.52 ≦ _y ≦ 0.76, 0.24 ≦ _z ≦ 0.48, 1.70 ≦ _u ≦ 2.00, 0 ≦ _u ≦ 0.30, and y + z + u + v = 3. Or y + z = 1 and u + v = 2.

The second photoelectric conversion layer 22 is CuGa _y In _{z Z n w} S _u Se _v, and 0.64 ≦ _y ≦ 0.88, 0 ≦ _z ≦ 0.36, 0 ≦ _w ≦ 0.12, 0.15 ≦ _u ≦ 1.44, 0.56 ≦ v + 1.85 and y + z + w + u + v = 3. Or y + z + w = 1 and u + v = 2.

The third photoelectric conversion layer 23 is CuGa _y Zn _w S _u Se _v , and 0.74 ≤ y ≤ 0.91, 0.09 ≤ w ≤ 0.26, 1.42 ≤ _u ≤ 1.49, 0.51 ≤ _v ≤ 0.58 and y + w +. u + v = 3.

The composition of CuAlGaInSSe system described above may be partially substituted with those of these compositions, or may be substituted in its entirety. 29 shows one example of each.

<7. Seventh embodiment>

[Seventh Example of Configuration of Solid-State Imaging Device]

Next, a seventh example of the solid-state imaging device according to the seventh embodiment of the present invention will be described with a schematic configuration sectional view of FIG. 30 and a circuit diagram of FIG. 31. In FIG. 30, as an example, the back side irradiation type sensor which light injects from the back surface side opposite to the surface side in which a transistor, wiring, etc. were formed is shown. Also with this backside irradiation type sensor, the same effect as the surface irradiation type sensor in which light injects from the surface side in which a transistor, wiring, etc. were formed can be acquired.

As shown in FIG. 30, the silicon substrate 11 is formed of a p-type silicon substrate. The first electrode layer 12 is formed in the silicon substrate 11 to the vicinity of the back surface side of the silicon substrate 11. The first electrode layer 12 is made of, for example, an n-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, on the first electrode layer (12), i-CuGa _{0 .52 0 .48} S ₂ In the film the first photoelectric conversion layer _{(21), i-CuAl 0.24} Ga 0.23 In 0.53 S 2 film a second photoelectric conversion layer 22, a _{p-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 the third photoelectric conversion layer 23 of _0.72 is formed is stacked.

Therefore, the photoelectric conversion layer 13 has a p-i-n structure as a whole.

As the photoelectric conversion layer 13, one having the composition range described above may be used, and the CuGaInZnSSe based mixed crystal described above may be used.

On the photoelectric conversion layer 13, a second electrode layer 14 having transparency is formed. The second electrode layer 14 is formed of a transparent electrode material such as indium tin oxide (ITO), zinc oxide, indium zinc oxide, or the like.

In addition, a read electrode 15 of the first electrode layer 12 is formed on the surface side of the silicon substrate 11 (in the lower surface side of the silicon substrate 11 in the drawing), and the silicon substrate 11 On the surface side of the side, a read circuit 51 for reading in the direction of the arrow through the gate MOS 41 is formed.

As shown in FIG. 31, the read circuit 51 includes a diffusion layer of the reset transistor M ₁ and a gate electrode of the amplifying transistor M ₂ in the floating diffusion portion FD connected to the photoelectric conversion layer 13. Is connected. Further, a selection transistor M ₃ having a common diffusion layer of the amplifying transistor M ₂ is connected. An output line is connected to the diffusion layer of the selection transistor M ₃ .

The solid-state imaging device (image sensor) 7 has a structure as described above.

In the solid-state imaging device 7, spectroscopy in the depth direction of RGB, photoelectron accumulation, signal reading by applying a three-stage voltage, and reduction of avalanche multiplication can be simultaneously performed.

Further, electrodes such as the read electrode 15 and the gate MOS 41, transistors, wirings, and the like are formed on the surface side of the silicon substrate 11. The photoelectric conversion layer 13 is formed on the back surface side of the silicon substrate 11 (in the figure, the upper surface side of the silicon substrate 11), thereby providing a gap with the adjacent photoelectric conversion layer 13, as well as providing a gap between the silicon substrate 11 and the silicon substrate 11. The photoelectric conversion layer 13 can be formed on the entire surface of the (11). For this reason, since the opening of light becomes wide, the incident amount of light increases, and a sensitivity can be improved remarkably.

[Modification Example 1 of Seventh Example of Solid State Imaging Device]

In addition, from the side in a solid-state imaging device 7 shown in FIG. 30, as shown in FIG 32, the silicon substrate 11, a photoelectric conversion layer _{(13), n-CuAlS 1} .2 Se 0 .8 or i -CuAlS may be used in which the composition changes from _{1 .2 .8} Se ₀ to _{p-CuGa 0.52 in 0.48 S 2} . In this solid-state imaging device (image sensor) 8, larger avalanche multiplication is possible at a low drive voltage.

[Modification Example 2 of Seventh Example of Solid State Imaging Device]

In addition, a solid-state imaging device (image sensor) is explained with reference to FIG. 33. As shown in FIG. 33, in the solid-state imaging device 5 shown in FIG. 26, the reading electrode 15 is placed on the surface side of the silicon substrate 11 (in the drawing, the lower surface side of the silicon substrate 11). Electrodes such as the gate MOS 41, transistors, wirings, and the like are formed. That is, in the solid-state imaging device 7 shown in FIG. 30, the photoelectric conversion layer 13 forms the spectrophotoelectric conversion layer of only one layer of each color. Therefore, the first photoelectric conversion layer 21 of the R-spectral photoelectric conversion layer 21 and the second photoelectric conversion layer of the G-spectral photoelectric conversion layer are formed on the back side of the silicon substrate 11 (in the figure, the upper surface side of the silicon substrate 11). The layer 22 and the third photoelectric conversion layer 23 of the B-spectral photoelectric conversion layer are not laminated, and are formed for each layer.

Therefore, the solid-state imaging device 9 has a structure in which RGB photoelectric conversion layers are arranged in the lateral direction. The photonic readout circuit (not shown), the readout electrode 15, the gate MOS 41, the wiring (not shown), and the like are used for the surface side of the silicon substrate 11 (not shown). The lower surface side).

In such a configuration, the photoelectric conversion layer 13 can be formed on the entire surface of the silicon substrate 11 in addition to providing a gap with the adjacent photoelectric conversion layer 13. For this reason, since the opening of light becomes wide, the incident amount of light increases, and a sensitivity can be improved remarkably.

<8. 8th Embodiment>

[First Example of Manufacturing Method of Solid-State Imaging Device]

The 1st example of the manufacturing method of the solid-state imaging device which concerns on 8th Embodiment of this invention is demonstrated below.

For example, the solid-state imaging device 2 shown in FIG. 12 can be applied to the photodiode of the CMOS image sensor shown in FIG. The band diagram of the solid-state imaging device 2 is as shown in FIG. 14.

The said solid-state imaging device 2 can be formed in the silicon substrate 11 by a normal CMOS process process, for example. The details will be described below with reference to FIG. 12.

As the silicon substrate 11, a (100) silicon substrate is used. First, a circuit (not shown) of peripheral transistors or electrodes is fabricated on the silicon substrate 11.

Next, the first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is formed of an n-type silicon layer by ion implantation, for example. In this ion implantation, the ion implantation region is determined using a resist mask. This resist mask is removed after ion implantation.

Next, on the first electrode layer 12 of the silicon substrate 11, a first photoelectric conversion layer 21 that is an R-spectral photoelectric conversion layer is formed. The first photoelectric conversion layer 21 is, for example, by using the MBE method, to form by performing the crystal growth of the _{i-CuGa 0 .52 In 0 .48} S 2 mixed crystal. However, the barrier is placed on the interface side with the silicon substrate 11 under the condition of B _R > kT = 26meV. For example, the first after growth in the proportion of _{i-CuAl 0 .06 Ga 0 .45} In 0 .49 S 2, at the same time to reduce gradually the composition of Al and Ga in the In composition gradually increases by, i-CuGa _0. by a composition of ₅₂ in _{0 .48} S _2, it is possible to laminate the barrier spike. Since the energy B _R of this barrier becomes 50 meV or less, it is sufficiently higher than the thermal energy at room temperature. In addition, the thickness of the barrier was 100 nm. The photoelectric conversion layer for R spectroscopy was made 0.8 micrometer in total.

Next, a second photoelectric conversion layer 22 which is a G-spectral photoelectric conversion layer is formed on the first photoelectric conversion layer 21. The second photoelectric conversion layer 22 was formed to have a thickness of, for example, 0.7 µm using, for example, the MBE method. The composition of this second photoelectric conversion layer 22 was i-CuAl _0.24 Ga _0.23 In _0.53 S ₂ .

The barrier is laminated on the interface side with the first photoelectric conversion layer 21. First to _{i-CuAl 0.33 Ga 0.11 In0 .56} S and then to the _second, at the same time to gradually decrease the composition of Al and In, by gradually increasing the composition of Ga, Ga i-CuAl _{0 .24 0 .23 0 .53} In ₂ S By setting it as the composition of, the spike-like barrier can be laminated. Since the energy B _G of this barrier becomes 84 meV or less, it is sufficiently higher than the thermal energy at room temperature and higher than the B _R.

In addition, a third photoelectric conversion layer 23, which is a B-spectral photoelectric conversion layer, is formed on the second photoelectric conversion layer 22. The third photoelectric conversion layer 23 was formed to have a thickness of, for example, 0.3 µm using, for example, the MBE method. The composition of this third photoelectric conversion layer 23 was p-CuAl _0.36 Ga _0.64 S _1.28 Se _0.72 .

The barrier is laminated on the interface side with the second photoelectric conversion layer 22. After the first to _{p-CuAl 0.42 Ga 0.58 S 1.36} Se 0.64 the composition of Al and S while at the same time gradually reduced, by gradually increasing the composition of Ga, p-CuAl Ga _{0 .36 0 .64 1 .28} S Se _{0 .72} By setting it as the composition of, the spike-like barrier can be laminated. Since the energy B _B of this barrier becomes 100 meV or less, it is sufficiently higher than the thermal energy at room temperature and higher than B _G and B _R. In addition, it is possible to make p-type electroconductivity into the Cu / Group 13 element ratio 1 or less. For example, it becomes possible by crystal growth by making this ratio into 0.98-0.99.

However, regarding the crystal growth mentioned above, growth of a solid solution may be difficult depending on conditions. In this case, pseudo-orientation by the superlattice may be grown. For example, if the R photoelectric conversion layer for spectroscopic, i-CuInS by the critical film laminated with a thin film thickness of less than ₂ in the composition and the composition of the shift i-CuGaS _2, the overall composition of i-CuGa _{0 .52} In _0. Laminate to ₄₈ S ₂ .

For example, by using an X-ray diffraction method or the like, the i-CuInS ₂ layer and the i-CuGaS ₂ layer are alternately stacked to obtain growth conditions for lattice matching to Si (100) in advance, and then the total composition is desired. It can be laminated so that.

In the crystal growth, portions of transistors, readout circuits, wirings, and the like are previously covered with a material film such as silicon oxide (SiO ₂ ), silicon nitride (SiN), and the like, where a portion of the silicon substrate 11 is exposed. The photoelectric conversion layer was grown.

After that, growth was made in the lateral direction on the material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and the photoelectric conversion layer was grown almost on the entire surface.

As the second electrode layer 14, indium tin oxide (ITO), which is a transparent electrode material, is formed by laminating by sputter deposition. By wiring the metal on this ITO, the ground is grounded and charges due to hole accumulation are prevented. Further, preferably, a resist mask is formed so as not to be electrically mixed with signals, and is separated for each pixel by reactive ion etching (RIE) processing or the like. At this time, not only the transparent electrode but also the photoelectric conversion layer is separated. In order to increase the light collection efficiency, an on-chip lens OCL may be formed for each pixel.

In the solid-state imaging device (image sensor) 2 manufactured by the above process, by applying voltage to V _R , V _G , and V _B sequentially in reverse bias, avalanche multiplication occurs and RGB is amplified. Each signal can be obtained. However, V _R > V _G > V _B. The image obtained by such a method shows the device level color reproducibility of a normal on-chip color filter (OCCF), and its sensitivity is high.

<9. 9th Embodiment>

[2nd example of manufacturing method of solid-state imaging device]

A second example of the manufacturing method of the solid-state imaging device according to the ninth embodiment of the present invention is described below.

For example, the solid-state imaging device 3 shown in FIG. 21 can be applied to the photodiode of the CMOS image sensor shown in FIG. In addition, the band diagram of the said solid-state imaging device 3 is as showing in FIG.

The said solid-state imaging device 3 can be formed in the silicon substrate 11 by a normal CMOS process process, for example. Details will be described below with reference to FIG. 21.

As the silicon substrate 11, a (100) silicon substrate is used. First, circuits such as transistors and electrodes around the silicon substrate 11 are fabricated.

Next, the first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is formed of an n-type silicon layer by ion implantation, for example. In this ion implantation, the ion implantation region is determined using a resist mask. This resist mask is removed after ion implantation.

Next, on the first electrode layer 12 of the silicon substrate 11, a first photoelectric conversion layer 21 that is an R-spectral photoelectric conversion layer is formed. The first photoelectric conversion layer 21 is, for example, by using the MBE method, to form by performing the crystal growth of the _{i-CuGa 0 .52 In 0 .48} S 2 mixed crystal. The thickness was 0.8 micrometer, for example.

Next, a second photoelectric conversion layer 22 which is a G-spectral photoelectric conversion layer is formed on the first photoelectric conversion layer 21. The second photoelectric conversion layer 22 was formed to have a thickness of, for example, 0.7 µm using, for example, the MBE method. The composition of this second photoelectric conversion layer 22 was i-CuAl _0.24 Ga _0.23 In _0.53 S ₂ .

The barrier is laminated on the interface side with the first photoelectric conversion layer 21. After growing the _{i-CuAl 0.33 Ga 0.11 In 0.56} S 2 to a thickness of the first 50㎚, it can be formed by growing the _{i-CuAl 0 .24 Ga 0 .23} In 0 .53 S 2. Since the energy B _G of this barrier becomes 84 meV or less, it is sufficiently higher than the thermal energy at room temperature and higher than the B _R.

In addition, a third photoelectric conversion layer 23, which is a B-spectral photoelectric conversion layer, is formed on the second photoelectric conversion layer 22. The third photoelectric conversion layer 23 was formed to have a thickness of, for example, 0.3 µm using, for example, the MBE method. The composition of this third photoelectric conversion layer 23 was p-CuAl _0.36 Ga _0.64 S _1.28 Se _0.72 .

The barrier is laminated on the interface side with the second photoelectric conversion layer 22. After growing the _{p-CuAl 0.42 Ga 0.58 S 1.36} Se 0.64 for a thickness of the first 50㎚, by growing a composition of _{i-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 .72, made of a barrier. Since the energy B _G of this barrier becomes 100 meV or less, it is sufficiently higher than the thermal energy at room temperature, and higher than B _G and B _R.

Next, in order to change the conductivity of the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23 in the lateral direction, a mask is formed using lithography technique, and Ion implantation of dopants. Formation of a p-type region becomes possible by ion implantation using a group 13 element as a p-type dopant. For example, gallium (Ga) is ion implanted. In addition, formation of an n-type region is attained by using a Group 12 element as an n-type dopant. For example, zinc (Zn) is ion implanted. Annealing after ion implantation activates the dopant, and a p-i-n structure can be produced.

In the crystal growth, portions of transistors, readout circuits, wirings, and the like are previously covered with a material film such as silicon oxide (SiO ₂ ), silicon nitride (SiN), and the like, where a portion of the silicon substrate 11 is exposed. The photoelectric conversion layer was grown.

Further, after that, growth was made in the lateral direction on a material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and the photoelectric conversion layer was grown almost on the entire surface.

As the second electrode layer 14, indium tin oxide (ITO), which is a transparent electrode material, is formed by laminating by sputter deposition. By wiring the metal on this ITO, the ground is grounded and charges due to hole accumulation are prevented. In this case, when the p concentration is set high, since the holes can move to the silicon substrate 11 side, the second electrode layer 14 is not necessarily required. Further, preferably, a resist mask is formed so as not to be electrically mixed with signals, and is separated for each pixel by reactive ion etching (RIE) processing or the like. At this time, not only the transparent electrode but also the photoelectric conversion layer is separated. In order to increase the light collection efficiency, an on-chip lens OCL may be formed for each pixel.

In the solid-state imaging device (image sensor) 3 produced by the above process, the electrons move toward the first electrode layer 12 side of the n-type silicon layer with respect to the first photoelectric conversion layer 21 for R spectroscopy. This is read by the gate MOS 41. In addition, similar to the second photoelectric conversion layer 22 for G spectroscopy and the third photoelectric conversion layer 23 for B spectroscopy, a barrier is provided at an interface between the first photoelectric conversion layer 21 and the silicon substrate 11. Further, by providing an n electrode on the first photoelectric conversion layer 21, the electrons accumulated in the film may be read directly. The image obtained by such a method shows the device level color reproducibility of a normal on-chip color filter (OCCF), and its sensitivity is high.

<10. 10th Embodiment>

[Third Example of Manufacturing Method of Solid-State Imaging Device]

A third example of the manufacturing method of the solid-state imaging device according to the tenth embodiment of the present invention will be described below.

For example, the solid-state imaging device 2 shown in FIG. 12 can be applied to the photodiode of the CCD shown in FIG. 35. The band diagram of the solid-state imaging device 2 is as shown in FIG. 14.

The said solid-state imaging device 2 can be formed in the silicon substrate 11 by a normal CCD process process, for example. The details will be described below with reference to FIG. 12.

As the silicon substrate 11, a (100) silicon substrate is used. First, a circuit such as a peripheral transfer gate or a vertical register is fabricated on the silicon substrate 11.

Next, the first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is formed of an n-type silicon layer by ion implantation, for example. In this ion implantation, the ion implantation region is determined using a resist mask. This resist mask is removed after ion implantation.

Next, on the first electrode layer 12 of the silicon substrate 11, a first photoelectric conversion layer 21 that is an R-spectral photoelectric conversion layer is formed. The first photoelectric conversion layer 21 is, for example, by using the MBE method, to form by performing the crystal growth of the _{i-CuGa 0 .52 In 0 .48} S 2 mixed crystal. However, the barrier is placed on the interface side with the silicon substrate 11 under the condition of B _R > kT = 26meV. For example, the first i-CuAl _0.06 Ga _0.45 In _0.49 after growth in the proportion of S _2, thereby at the same time to reduce gradually the composition of Al and In composition gradually increases in the Ga, In i-CuGa _{0 .52 0 .48} S By setting it as ₂ , a spike-like barrier can be laminated | stacked. Since the energy B _R of this barrier becomes 50 meV or less, it is sufficiently higher than the thermal energy at room temperature. In addition, the thickness of the barrier was 100 nm. The photoelectric conversion layer for R spectroscopy was made 0.8 micrometer in total.

Next, a second photoelectric conversion layer 22 which is a G-spectral photoelectric conversion layer is formed on the first photoelectric conversion layer 21. The second photoelectric conversion layer 22 was formed to have a thickness of, for example, 0.7 µm using, for example, the MBE method. The composition of this second photoelectric conversion layer 22 was i-CuAl _0.24 Ga _0.23 In _0.53 S ₂ .

The barrier is laminated on the interface side with the first photoelectric conversion layer 21. First, i-CuAl _0.33 Ga _0.11 In _0.56 S ₂ , and then the composition of Al and In is gradually decreased. With that, by gradually increasing the composition of Ga,, it is possible to laminate the barrier spike by the composition of the _{i-CuAl 0 .24 Ga 0 .23} In 0 .53 S 2. Since the energy B _G of this barrier becomes 84 meV or less, it is sufficiently higher than the thermal energy at room temperature and higher than the B _R.

In addition, a third photoelectric conversion layer 23, which is a B-spectral photoelectric conversion layer, is formed on the second photoelectric conversion layer 22. The third photoelectric conversion layer 23 was formed to have a thickness of, for example, 0.3 µm using, for example, the MBE method. The composition of this third photoelectric conversion layer 23 was p-CuAl _0.36 Ga _0.64 S _1.28 Se _0.72 .

The barrier is laminated on the interface side with the second photoelectric conversion layer 22. Initially, p-CuAl _0.42 Ga _0.58 S _1.36 Se _0.64 is gradually reduced in the composition of Al and S. With that, by gradually increasing the composition of Ga,, it is possible to laminate the barrier spike by the composition of the _{p-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 .72. Since the energy B _G of this barrier becomes 100 meV or less, it is sufficiently higher than the thermal energy at room temperature, and higher than B _G and B _R. The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, it becomes possible by crystal growth by making this ratio into 0.98-0.99.

However, regarding the crystal growth mentioned above, growth of a solid solution may be difficult depending on conditions. In this case, pseudo-orientation by the superlattice may be grown. For example, if the R photoelectric conversion layer for spectroscopic, i-CuInS by the critical film laminated with a thin film thickness of less than ₂ in the composition and the composition of the shift i-CuGaS _2, the overall composition of i-CuGa _{0 .52} In _0. Laminate to ₄₈ S ₂ .

For example, by using an X-ray diffraction method or the like, the i-CuInS ₂ layer and the i-CuGaS ₂ layer are alternately stacked to obtain growth conditions for lattice matching to Si (100) in advance, and then the total composition is desired. It can be laminated so that.

In the crystal growth, portions of transistors, readout circuits, wirings, and the like are previously covered with a material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and selectively exposed to a portion where the silicon substrate 11 is exposed. The photoelectric conversion layer was grown.

Thereafter, growth was made in the lateral direction on a material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and the photoelectric conversion layer was grown almost on the entire surface.

Subsequently, as the second electrode layer 14, indium tin oxide (ITO), which is a transparent electrode material, is laminated and formed by sputter deposition. By wiring the metal on this ITO, the ground is grounded and charges due to hole accumulation are prevented. Further, preferably, a resist mask is formed so as not to be electrically mixed with signals, and is separated for each pixel by reactive ion etching (RIE) processing or the like. At this time, not only the transparent electrode but also the photoelectric conversion layer is separated. In order to increase the light collection efficiency, an on-chip lens OCL may be formed for each pixel.

In the solid-state imaging device (image sensor) 2 manufactured by the above process, by applying voltage to V _R , V _G , and V _B sequentially in reverse bias, avalanche multiplication occurs and RGB is amplified. Each signal can be obtained. However, V _R > V _G > V _B.

The signal can be read by transferring the signal thus obtained to the vertical CCD through the transfer gate, and transferring the signal to the horizontal CCD as in the normal CCD and outputting it. The image obtained by such a method shows the device level color reproducibility of a normal on-chip color filter (OCCF), and its sensitivity is high.

<11. Eleventh embodiment>

[Fourth Example of Manufacturing Method of Solid-State Imaging Device]

A fourth example of the manufacturing method of the solid-state imaging device according to the eleventh embodiment of the present invention will be described below.

For example, the solid-state imaging device 5 shown in FIG. 26 can be applied to the photodiode of the CMOS image sensor shown in FIG. 34. This solid-state imaging device 5 has a structure in which RGB photoelectric conversion layers are separated from each other.

The said solid-state imaging device 5 can be formed in the silicon substrate 11 by a normal CMOS process process, for example. Details will be described below with reference to FIG. 26.

As the silicon substrate 11, a (100) silicon substrate is used. First, circuits such as transistors and electrodes around the silicon substrate 11 are fabricated.

Next, the first electrode layer 12 is formed on the silicon substrate 11 corresponding to the position where the photoelectric conversion layer for spectroscopically analyzing each color of RGB is formed. The first electrode layer 12 is formed by forming an n-type silicon layer by ion implanting an n-type dopant into the silicon substrate 11, for example.

Next, an oxide film (not _shown ) of silicon oxide (SiO ₂ ) is formed on the silicon substrate 11, and a region in which an R-spectral photoelectric conversion layer is formed using lithography technique and RIE processing technique. Cover other than the surface of the. Subsequently, on the silicon substrate 11, for example, the MBE method is used to form the first photoelectric conversion layer 21, which is an R-spectral photoelectric conversion layer. The first photoelectric conversion layer 21 is, for example, formed by p-CuGa _{0 .52 0 .48} In determining the S ₂ mixed crystal growth. In this case, it grows about 0.8 micrometer in thickness on the conditions which strengthened the migration so that crystal | crystallization may grow only on the photodiode surface of R selectively. The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, it became possible by making crystal | crystallization grow this ratio to 0.98.

Thereafter, the oxide film is removed.

Next, an oxide film (not _shown ) of silicon oxide (SiO ₂ ) is formed on the silicon substrate 11, and further, by using a lithography technique and a RIE processing technique, a region where the G-spectral photoelectric conversion layer is formed. Cover other than the surface. Subsequently, on the silicon substrate 11, for example, a second photoelectric conversion layer 22 which is a G-spectral photoelectric conversion layer is formed by using the MBE method. The second photoelectric conversion layer 22 is, for example, formed by _{p-CuAl 0 .24 Ga 0 .23} In 0 .53 determine S ₂ mixed crystal growth. In this case, it grows about 0.7 micrometer in thickness on condition that migration was strengthened so that crystal | crystallization may grow only on G photodiode surface selectively. The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, it became possible by crystal growth by making this ratio 0.98.

Thereafter, the oxide film is removed.

In addition, an oxide film (not _shown ) of silicon oxide (SiO ₂ ) is formed on the silicon substrate 11, and the surface of the region where the B-spectral photoelectric conversion layer is formed using lithography technique and RIE processing technique. Cover other than this. Subsequently, on the silicon substrate 11, for example, a third photoelectric conversion layer 23 that is a B-spectral photoelectric conversion layer is formed by using the MBE method. The third photoelectric conversion layer 23 is, for example, formed by _{p-CuAl 0 .36 Ga 0 .64} S 1 .28 _{0 .72} determine Se mixed crystal growth. In this case, it grows about 0.7 micrometer in thickness on condition that the migration was strengthened so that crystal | crystallization might grow only on the photodiode surface of B selectively. The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, this ratio was made possible by crystal growth with 0.98 to 0.99.

Thereafter, the oxide film is removed.

However, regarding the crystal growth mentioned above, growth of a solid solution may be difficult depending on conditions. In this case, pseudo-orientation by the superlattice may be grown.

For example, if the photoelectric conversion layer for the R spectroscopy, by the critical film laminated with a thin film of a thickness within a p-CuInS ₂ of the composition and the composition of alternating p-CuGaS _2, the overall composition of p-CuGa _{0 .52} In ₀ Stack to _.48 S ₂ . For example, by alternately stacking the p-CuInS ₂ layer and the p-CuGaS ₂ layer using X-ray diffraction, etc., the growth conditions for lattice matching to Si (100) are determined in advance, and then the total composition is desired. It can be laminated so that.

Next, second electrode layers 14 are formed on the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, respectively. This second electrode layer 14 is formed of the same transparent electrode as described above. By wiring the metal on the second electrode layer 14, the ground is grounded to prevent charge due to hole accumulation.

Further, preferably, the pixels are separated for each pixel by RIE processing or the like so as not to mix the signals electrically. At this time, not only the second electrode layer 14 but also the photoelectric conversion layer is separated. In order to increase the light collection efficiency, an on-chip lens OCL may be formed for each pixel.

Regarding the image sensor manufactured by the above process, the reverse bias is applied to obtain signals r, g and b (→ RAW data) of each RGB. In addition, after demosaicing, the following color calculation may be performed.

R = r-g, G = g-b, B = b

Here, r, g, and b are RAW data.

The image obtained by such a method shows the device level color reproducibility of a normal on-chip color filter (OCCF), and its sensitivity is high.

<12. 12th Embodiment>

[Fifth Example of Manufacturing Method of Solid-State Imaging Device]

The fifth example of the manufacturing method of the solid-state imaging device according to the twelfth embodiment of the present invention will be described below.

For example, the solid-state imaging device 10 shown in FIG. 36 can be applied to the photodiode of the CMOS image sensor shown in FIG. 34. In this solid-state imaging device 10, as shown in FIG. 37, it is a grating matching system and the composition is changed in the range which can change a band gap to the maximum. By doing in this way, since avalanche multiplication can be taken out to the maximum with low drive voltage, remarkable high sensitivity can be acquired.

As the silicon substrate 11, a (100) silicon substrate is used. First, a circuit such as a peripheral transistor or an electrode is fabricated on the silicon substrate 11.

Next, the first electrode layer 12 is formed on the silicon substrate 11 corresponding to the position where the photoelectric conversion layer for spectroscopically analyzing each color of RGB is formed. The first electrode layer 12 is formed by forming an n-type silicon layer by ion implanting an n-type dopant into the silicon substrate 11, for example.

Next, a photoelectric conversion layer 13 is formed on the silicon substrate 11. For example, using the MBE method, thereby growing the n-CuAlS _{1 .2} Se _{0 .8} or i-CuAlS _{1 .2} determination of Se _{0 .8} in the first place. Subsequently, by a composition of Al and Se at the same time to gradually decrease gradually the composition of Ga and In, and the composition of the _{p-CuGa 0 .52 In 0 .48} S 2. It should just be about 2 micrometers as whole thickness.

However, it changes from n type or i type to p type along the way. In order to make n-type electroconductivity, doping of group 12 element may be performed. For example, when crystal growth, it becomes possible to add a trace amount of zinc (Zn) simultaneously.

On the other hand, in the case of i type, it is not especially doped.

The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, it becomes possible by crystal growth by making this ratio into 0.98-0.99.

Further, in the above growth, the photoelectric conversion is selectively covered where a portion of a transistor, a read circuit, a wiring, or the like is previously covered with a material such as silicon oxide (SiO ₂ ), silicon nitride (SiN), and a portion of the Si substrate is exposed. Grow the layer. Thereafter, the photoelectric conversion layer is grown almost on the entire surface by growing in a lateral direction on a material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN).

As the second electrode layer 14, indium tin oxide (ITO), which is a transparent electrode material, is formed by laminating by sputter deposition. By wiring the metal on this ITO, the ground is grounded and charges due to hole accumulation are prevented. In order to perform color separation, an on-chip color filter (OCCF) may be attached for each pixel. In order to improve light condensation, an on-chip lens OCL may be attached.

Since there is a big change in the band gap as described above, since a large energy step can be obtained at a small driving voltage when the reverse bias is applied as shown in FIGS. 19 and 20, avalanche multiplication occurs largely and high. Sensitivity can be obtained.

<13. Thirteenth Embodiment>

[Sixth Example of Manufacturing Method of Solid State Imaging Device]

A sixth example of the manufacturing method of the solid-state imaging device according to the thirteenth embodiment of the present invention will be described below.

For example, the solid-state imaging device 7 shown in FIG. 30 can be applied to the photodiode of the CMOS image sensor shown in FIG.

The said solid-state imaging device 7 can be formed in the silicon substrate 11 by a normal CMOS process process, for example. Details will be described below with reference to FIG. 30.

In the silicon layer of the SOI substrate (corresponding to the silicon substrate 11 of FIG. 30), a circuit such as a peripheral transistor, an electrode, or the like is produced by a CMOS process. Further, a silicon oxide film (not shown) is formed to cover circuits such as transistors and electrodes in the vicinity.

Next, the silicon layer of the SOI substrate is transferred and pasted onto another glass substrate. At this time, the circuit side sticks to the glass substrate side, and the back surface side of the silicon 100 layer appears on the surface.

In addition, the first electrode layer 12 is formed in the silicon layer. The first electrode layer 12 is formed of an n-type silicon layer by ion implantation, for example. In this ion implantation, the ion implantation region is determined using a resist mask. This resist mask is removed after ion implantation.

Next, on the first electrode layer 12 of the silicon layer, a first photoelectric conversion layer 21 that is an R-spectral photoelectric conversion layer is formed. The first photoelectric conversion layer 21 is, for example, by using the MBE method, to form by performing the crystal growth of the _{i-CuGa 0 .52 In 0 .48} S 2 mixed crystal.

However, the barrier is placed on the interface side with the silicon substrate 11 under the condition of B _R > kT = 26meV. For example, the first after growth in the proportion of _{i-CuAl 0 .06 Ga 0 .45} In 0 .49 S 2, at the same time to reduce gradually the composition of Al and Ga in the In composition gradually increases by, i-CuGa _0. by a composition of ₅₂ in _{0 .48} S _2, it is possible to laminate the barrier spike. Since the energy B _R of this barrier becomes 50 meV or less, it is sufficiently higher than the thermal energy at room temperature. In addition, the thickness of the barrier was 100 nm. The photoelectric conversion layer for R spectroscopy was made 0.8 micrometer in total.

Next, a second photoelectric conversion layer 22 which is a G-spectral photoelectric conversion layer is formed on the first photoelectric conversion layer 21. The second photoelectric conversion layer 22 was formed to have a thickness of, for example, 0.7 µm using, for example, the MBE method. The composition of this second photoelectric conversion layer 22 was i-CuAl _0.24 Ga _0.23 In _0.53 S ₂ .

The barrier is laminated on the interface side with the first photoelectric conversion layer 21. First to _{i-CuAl 0.33 Ga 0.11 In0 .56} S after ₂ at the same time to gradually decrease the composition of Al and In, by gradually increasing the composition of Ga, the _{i-CuAl 0 .24 Ga 0 .23} In 0 .53 S 2 By setting it as a composition, a spike-like barrier can be laminated | stacked. Since the energy B _G of this barrier becomes 84 meV or less, it is sufficiently higher than the thermal energy at room temperature and higher than the B _R.

In addition, a third photoelectric conversion layer 23, which is a B-spectral photoelectric conversion layer, is formed on the second photoelectric conversion layer 22. The third photoelectric conversion layer 23 was formed to have a thickness of, for example, 0.3 µm using, for example, the MBE method. The composition of this third photoelectric conversion layer 23 was p-CuAl _0.36 Ga _0.64 S _1.28 Se _0.72 .

The barrier is laminated on the interface side with the second photoelectric conversion layer 22. After the first to _{p-CuAl 0.42 Ga 0.58 S 1.36} Se 0.64 the composition of Al and S while at the same time gradually reduced, by gradually increasing the composition of Ga, p-CuAl Ga _{0 .36 0 .64 1 .28} S Se _{0 .72} By setting it as the composition of, the spike-like barrier can be laminated. Since the energy B _G of this barrier becomes 100 meV or less, it is sufficiently higher than the thermal energy at room temperature, and higher than B _G and B _R. The p-type conductivity can be achieved by setting the Cu / Group 13 element ratio to 1 or less. For example, it becomes possible by crystal growth by making this ratio into 0.98-0.99.

However, regarding the crystal growth mentioned above, growth of a solid solution may be difficult depending on conditions. In this case, pseudo-orientation by the superlattice may be grown. For example, if the R photoelectric conversion layer for spectroscopic, i-CuInS by the critical film laminated with a thin film thickness of less than ₂ in the composition and the composition of the shift i-CuGaS _2, the overall composition of i-CuGa _{0 .52} In _0. Laminate to ₄₈ S ₂ .

For example, by using an X-ray diffraction method or the like, the i-CuInS ₂ layer and the i-CuGaS ₂ layer are alternately stacked to obtain growth conditions for lattice matching to Si (100) in advance, and then the total composition is desired. It can be laminated so that.

In the crystal growth, portions of transistors, readout circuits, wirings, and the like are previously covered with a material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and selectively exposed to a portion where the silicon substrate 11 is exposed. The photoelectric conversion layer was grown.

Further, after that, growth was made in the lateral direction on a material film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), and the photoelectric conversion layer was grown almost on the entire surface.

As the second electrode layer 14, indium tin oxide (ITO), which is a transparent electrode material, is formed by laminating by sputter deposition. By wiring the metal on this ITO, the ground is grounded and charges due to hole accumulation are prevented. Further, preferably, a resist mask is formed so as not to be electrically mixed with signals, and is separated for each pixel by reactive ion etching (RIE) processing or the like. At this time, not only the transparent electrode but also the photoelectric conversion layer is separated. In order to increase the light collection efficiency, an on-chip lens OCL may be formed for each pixel.

In the solid-state imaging device (image sensor) 7 produced by the above process, by applying a voltage in reverse bias sequentially to V _R , V _G , and V _B , avalanche multiplication occurs and RGB is amplified. Each signal can be obtained. However, V _R > V _G > V _B. The image obtained by such a method shows the device level color reproducibility of a normal on-chip color filter (OCCF), and its sensitivity is high.

<14. 14th Embodiment>

[Tenth Example of Configuration of Solid-State Imaging Device]

In all the solid-state imaging devices mentioned above, it demonstrated as a structure which reads an electron as a signal.

In fact, it may be configured to read holes as a signal. One example thereof will be described below.

The structure of the solid-state imaging device of hole reading corresponding to FIG. 12 will be described with a schematic configuration sectional view of FIG.

As shown in FIG. 38, the silicon substrate 11 is formed of an n-type silicon substrate. The first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, a p-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, first electrode layer 12 from a, i-CuGa _{0 .52 0 .48} S ₂ In the film the first photoelectric conversion layer _{(21), i-CuAl 0} .24 Ga 0 .23 in _{0 .53} S ₂ film a second photoelectric conversion layer 22, the _{i-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 the third photoelectric conversion layer 23 of _0.72 is formed is stacked. Further, on the photoelectric conversion layer 13, a second electrode layer 14 having transparency is formed through a cadmium sulfide (CdS) layer, which is the intermediate layer 16. The second electrode layer 14 is formed of an n-type transparent electrode material such as zinc oxide, for example. Inserting the cadmium sulfide layer as the intermediate layer 16 is for lowering the driving voltage by lowering the potential barrier for moving to the transparent electrode side of the electrons.

In addition, although the chalcopyrite layer of the said photoelectric conversion layer was made into i layer, the p-type layer of light dope may be sufficient.

In the solid-state imaging device 71, a spike-like barrier formed by continuous composition control on the wide gap side near each interface of the first, second, and third photoelectric conversion layers 21, 22, and 23 is provided with a valence band ( It is formed under the condition of B _B ≥ B _G ≥ B _R > kT (= 26 meV) on the side of the electron. As a result, the holes are trapped and the holes can be accumulated for each RGB. Where k is the Boltzmann constant and kT corresponds to the thermal energy at room temperature. In this case, the relationship between the positive and negative of the applied voltage of the read reverses as compared with the case of the electronic read structure. That is, by sequentially applying negative voltages in the order of V _R , V _G , and V _B , it becomes possible to read the R signal, the G signal, and the B signal (only V _B <V _G <V _R ≤ -kT).

Next, the structure of the solid-state imaging device of hole reading corresponding to FIG. 21 will be described with a schematic configuration sectional view of FIG.

As shown in FIG. 39, the silicon substrate 11 is formed of an n-type silicon substrate. The first electrode layer 12 is formed on the silicon substrate 11. The first electrode layer 12 is made of, for example, a p-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, first electrode layer 12 from the, CuGa _{0 .52 0 .48} S ₂ In the film the first photoelectric conversion layer (21), CuAl Ga _{0 .24 0 .23 0 .53} In S ₂ film a second photoelectric conversion layer (22), CuAl _{0 .36} is Ga _{0 .64} S _{1 .28} Se ₀ the third photoelectric conversion layer 23 of _0.72 is formed is stacked. In the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, each center portion is formed of an i layer, and one side thereof has a p layer and the other side. The side is formed by n layers. Therefore, it has a pin structure.

Further, a p-type electrode (second electrode layer) layer 14p is formed on the p layer of the second photoelectric conversion layer 22 and the p layer of the third photoelectric conversion layer 23 of the photoelectric conversion layer 13. have. In addition, an n-type electrode (second electrode layer) layer 14n is formed on the n-layer of the second photoelectric conversion layer 22 and the n-layer of the third photoelectric conversion layer 23 of the photoelectric conversion layer 13. have. The p-type electrode layer 14p may not be necessary.

In addition, a read circuit (not shown) for reading a signal through the gate MOS 41 is formed in the silicon substrate 11.

As mentioned above, the solid-state imaging device 72 is comprised.

Next, the structure of the hole reading solid-state imaging device corresponding to the solid-state imaging device shown in FIG. 26 will be described with a schematic configuration sectional view of FIG.

As shown in FIG. 40, the silicon substrate 11 is formed of an n-type silicon substrate. In this silicon substrate 11, a first electrode layer 12 is formed corresponding to a position where a photoelectric conversion layer for spectroscopic analysis of each color of RGB is formed. The first electrode layer 12 is made of, for example, a p-type silicon layer formed on the silicon substrate 11.

On the first electrode layer 12 at the R-split position, a first photoelectric conversion layer 21 made of lattice-matched CuAlGaInSSe-based mixed crystals is formed. The first photoelectric conversion layer 21 are formed of, for example, a p-In CuGa _{0 .52 0 .48 2} S film.

Further, on the first electrode layer 12 at the G-split position, a second photoelectric conversion layer 22 made of lattice matched CuAlGaInSSe-based mixed crystals is formed. This second photoelectric conversion layer 22 is formed of, for example, a p-CuAl _0.24 Ga _0.23 In _0.53 S ₂ film.

Further, a third photoelectric conversion layer 23 formed of lattice-matched CuAlGaInSSe-based mixed crystals is formed on the first electrode layer 12 at the B-split position. The third photoelectric conversion layer 23 are formed of, for example, a _{p-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 .72.

The thicknesses of the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23 are 0.8 μm, 0.7 μm, and 0.7 μm, respectively.

On the first photoelectric conversion layer 21, the second photoelectric conversion layer 22, and the third photoelectric conversion layer 23, a second light-transmitting layer is formed through a cadmium sulfide (CdS) layer, which is an intermediate layer 16. The electrode layer 14 is formed. The second electrode layer 14 is formed of an n-type transparent electrode material such as zinc oxide, for example.

Accordingly, the first photoelectric conversion layer 24 formed by stacking the first electrode layer 12, the first photoelectric conversion layer 21, and the second electrode layer 14 is formed on the silicon substrate 11. Similarly, the 2nd photoelectric conversion layer 25 formed by laminating | stacking the 1st electrode layer 12, the 2nd photoelectric conversion layer 22, and the 2nd electrode layer 14 is formed. Similarly, the third photoelectric conversion layer 26 formed by stacking the first electrode layer 12, the third photoelectric conversion layer 23, and the second electrode layer 14 is formed. Accordingly, the first to third photoelectric conversion layers 24 to 26 are disposed on the silicon substrate 11 in the lateral direction.

As mentioned above, the solid-state imaging device 73 is comprised.

Next, the structure of the hole reading solid-state imaging device corresponding to the solid-state imaging device shown in FIG. 30 will be described with a schematic configuration cross-sectional view of FIG.

As shown in FIG. 41, the silicon substrate 11 is formed of an n-type silicon substrate. The first electrode layer 12 is formed in the silicon substrate 11 to the vicinity of the back surface side of the silicon substrate 11. The first electrode layer 12 is made of, for example, a p-type silicon layer formed on the silicon substrate 11. On the first electrode layer 12, a photoelectric conversion layer 13 made of a lattice match and formed of a CuAlGaInSSe-based mixed crystal is formed. The photoelectric conversion layer 13, on the first electrode layer (12), p-CuGa _{0 .52 0 .48} S ₂ In the film the first photoelectric conversion layer _{(21), i-CuAl 0.24} Ga 0.23 In 0.53 S 2 film a second photoelectric conversion layer 22, a _{p-CuAl 0 .36 Ga 0 .64} S 1 .28 Se 0 the third photoelectric conversion layer 23 of _0.72 is formed is stacked.

Therefore, the photoelectric conversion layer 13 has a p-i-p structure as a whole.

As the photoelectric conversion layer 13, one having the composition range described above may be used, and the CuGaInZnSSe-based mixed crystal described above may also be used.

On the photoelectric conversion layer 13, a second electrode layer 14 having light transparency is formed through a cadmium sulfide (CdS) layer, which is an intermediate layer 16. The second electrode layer 14 is formed of an n-type transparent electrode material such as zinc oxide, for example.

In addition, on the surface side of the silicon substrate 11 (the lower surface side of the silicon substrate 11 in the drawing), a reading electrode 15 for reading a signal from the first electrode layer 12 is formed, and the silicon On the surface side of the substrate 11, a read circuit (not shown) is formed through the gate MOS 41.

As mentioned above, the solid-state imaging device 74 is comprised.

Next, the structure of the hole reading solid-state imaging device corresponding to the solid-state imaging device shown in FIG. 32 will be described with a schematic configuration cross-sectional view of FIG.

In addition, since, in Fig., The solid-state imaging device 8 is shown in FIG. 32, as shown in 42, the photoelectric conversion layer 13 side of the silicon substrate _{(11), p-CuAlS 1} .2 Se 0 .8 or i-CuAlS may be used in which the composition changes from _{1 .2 .8} Se ₀ to _{i-CuGa 0.52 in 0.48 S 2} . In this configuration, in the solid-state imaging device 75, a large avalanche multiplication is possible at a low driving voltage.

In the solid-state imaging device for hole reading, the government of the applied voltages of all the reads reverses with respect to the solid-state imaging device for electronic reading.

Next, the specific manufacturing method and each raw material of the formation method of the said photoelectric conversion layer 13 are demonstrated.

In the manufacturing method by the MOCVD growth method, crystal growth is performed using, for example, a MOCVD apparatus (Metal Organic Chemical Vapor Deposition) as shown in FIG. 43.

As the source gas, the following organic metals are used. As an organic metal of copper, acetylacetone copper (Cu (C ₅ H ₇ O ₂ ) ₂ ) is used as an example. As an organic metal of gallium (Ga), trimethylgallium (Ga (CH ₃ ) ₃ ) is used as an example. Trimethylaluminum (Al (CH ₃ ) ₃ ), which is one of the organic metals of aluminum (Al), is used. As an organic metal of indium (In), trimethyl indium (In (CH ₃ ) ₃ ) is used as an example. As an organic metal of selenium (Se, for example, dimethyl selenium (Se (CH ₃ ) ₂ ) is used. As an organic metal of sulfur (S), for example, dimethyl sulfide (S (CH ₃ ) ₂ ). As an organic metal of zinc (Zn), dimethyl zinc (Zn (CH ₃ ) ₂ ) is used as an example.

Here, it is not necessary to define these raw materials necessarily, and if it is an organic metal, it can use as a raw material of MOCVD growth similarly.

For example, triethylgallium (Ga (C ₂ H ₅ ) ₃ ), triethylaluminum (Al (C ₂ H ₅ ) ₃ ), triethylindium (In (C ₂ H ₅ ) ₃ ), diethyl selenium ( Se (C ₂ H ₅ ) ₂ ), diethyl sulfide (S (C ₂ H ₅ ) ₂ ), and diethyl zinc (Zn (C ₂ H ₅ ) ₂ ) may be used.

In addition, it is not necessarily organic metal, but may be gas-based. For example, hydrogen selenide (H ₂ Se) as a raw material or Se, may be used for hydrogen sulfide (H ₂ S) as S material.

In the MOCVD apparatus as shown in FIG. 43, by bubbling an organic metal raw material with hydrogen, it becomes a saturated vapor pressure state, and each raw material molecule is transported to a reaction tube. Here, by controlling the flow rate of hydrogen flowing to each raw material by the mass flow controller (MFC), the molar amount to be transported per unit time of the raw material is determined, and the organic metal raw material is thermally decomposed on the silicon substrate to be taken into the crystal, Crystal growth occurs. In that case, it becomes possible to control a composition ratio using what has a correlation with a transport molar amount ratio and the composition ratio of a crystal.

In addition, the silicon substrate is on the susceptor made of carbon, and the susceptor is heated by a high frequency heating device (RF coil), and a thermocouple and its temperature control mechanism are attached to control the substrate temperature. As a general board | substrate temperature, it becomes the range from 400 degreeC to 1000 degreeC in which thermal decomposition becomes possible, In order to lower | hang a substrate temperature, you may assist with thermal decomposition of a raw material by light-irradiating a substrate surface, for example with a mercury lamp.

Further, the raw material such as acetyl acetone copper _{(Cu (C 5 H 7 O} 2) 2) , or trimethyl indium (In (CH _{3) 3)} is a solid phase (固相) state at room temperature. In such a case, the raw material may be heated to be in a liquid state, or may be used in a state in which the vapor pressure is increased to a high temperature even in a solid state.

Next, the manufacturing method by the MBE growth method is demonstrated.

In the MBE growth method, crystal growth is performed using, for example, an MBE apparatus (Molecular Beam Epitaxy) as shown in FIG. 44.

A single raw material of copper and a single raw material of gallium (Ga), aluminum (Al), indium (In), selenium (Se), and sulfur (S) are put in each Knudsen cell. The crystals are grown by heating each molecular beam onto a substrate by heating them to an appropriate temperature. At this time, in the case of a raw material having a particularly high vapor pressure such as sulfur (S), the stability of molecular dose may be insufficient. In this case, a molecular dose may be stabilized by using a valved cracker cell. In addition, like a gas source MBE, some raw materials may be used as a gas source. For example, hydrogen selenide (H ₂ Se) as the Se raw material or hydrogen sulfide (H ₂ S) as the sulfur (S) raw material may be used.

<15. 15th Embodiment>

[1 Example of Configuration of Imaging Device]

Next, an embodiment of the imaging device of the present invention will be described with reference to the block diagram of FIG. 45. This imaging device uses the solid-state imaging device of this invention.

As shown in FIG. 45, the imaging device 200 includes a solid-state imaging device (not shown) in the imaging unit 201. The light condensing side of the imaging unit 201 is provided with a light condensing optical system 202 for forming an image, and the imaging unit 201 processes a signal converted photoelectrically by a drive circuit and a solid-state imaging device which driven it into an image. The signal processing unit 203 having a signal processing circuit or the like to be connected is connected. The image signal processed by the signal processing unit 203 can be stored by an image storage unit (not shown). In such an imaging device 200, the solid-state imaging devices 1 to 10 and 71 to 75 described in the above embodiments can be used as the solid-state imaging device.

In the imaging device 200 of the present invention, since the generation of dark current is suppressed by using the solid-state imaging devices 1 to 10, 71 to 75 of the present invention, deterioration of image quality due to the white point is suppressed, and the solid-state imaging device is further suppressed. Since the sensitivity becomes high, high sensitivity imaging is possible. Therefore, deterioration of image quality is suppressed and imaging with high sensitivity can be performed, and therefore there is an advantage that high quality imaging can be performed even in a dark imaging environment, for example, at night.

In addition, the imaging device 200 of this invention is not limited to the said structure, If it is an imaging device using a solid-state imaging device, it can apply to what kind of structure.

The solid-state imaging devices 1 to 10 and 71 to 75 may be formed as one chip or may be in the form of a module having an imaging function packaged by integrating the imaging unit, the signal processing unit, or the optical system.

In addition, the said imaging apparatus 200 is said to be a portable apparatus which has a camera and an imaging function, for example. In addition, "photographing" not only captures an image at the time of normal camera photography, but also includes fingerprint detection and the like as a broad meaning.

The present invention claims priority to Japanese Patent Application No. 2009-10787 filed with the Japan Patent Office on January 21, 2009.

Those skilled in the art will be able to practice various modifications, combinations, subcombinations and variations of the above embodiments, depending on design needs or other factors, within the scope of the appended claims or their equivalents.

1: solid-state imaging device
11: silicon substrate
13: photoelectric conversion layer

Claims (17)

A silicon substrate;
It includes a photoelectric conversion layer formed by lattice matching on the silicon substrate,
The photoelectric conversion layer is a solid-state imaging, characterized in that consisting of a copper-aluminum-gallium-indium-sulfur-selenium mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium mixed crystal Device. The method of claim 1,
And said photoelectric conversion layer is composed of a superlattice layer within a critical film thickness. 3. The method according to claim 1 or 2,
The photoelectric conversion layer is:
A first photoelectric conversion layer for spectra of red light having a band gap of 2.00 eV ± 0.1 eV;
A second photoelectric conversion layer in which a band gap spectroscopy green light of 2.20 eV ± 0.15 eV; And
And a third photoelectric conversion layer for spectra of blue light having a band gap of 2.51 eV ± 0.2 eV. The method of claim 3, wherein
The first photoelectric conversion layer, the second photoelectric conversion layer, and the third photoelectric conversion layer are sequentially stacked from the silicon substrate side. The method of claim 4, wherein
A carrier barrier is formed on a wide gap side of an interface between the first photoelectric conversion layer and the second photoelectric conversion layer and an interface between the second photoelectric conversion ring layer and the third photoelectric conversion layer, or
And a carrier barrier is formed on the wide gap side of the interface between the silicon substrate and the first photoelectric conversion layer. 3. The method according to claim 1 or 2,
The photoelectric conversion layer has a step gap or a gradually changing band gap and energy step,
An avalanche multiplication occurs by application of a reverse bias voltage. 6. The method of claim 5,
The reverse bias voltage for reading the red R signal is set to V _R ,
Reverse bias voltage to read green G signal is V _G ,
Set the reverse bias voltage for reading the blue B signal to be V _B ,
And V _B > V _G > V _R ,
A reverse imaging voltage is applied to the photoelectric conversion layer in the order of V _R , V _G and V _{B so that} the R signal, the G signal, and the B signal are read in sequence. The method of claim 7, wherein
Potential step in the photoelectric conversion layer,
The first photoelectric conversion layer, the second photoelectric conversion layer and the third photoelectric conversion layer are spectroscopic light as an RGB component in the depth direction
Photoelectrons are accumulated by the barrier of the carrier,
The reverse bias voltage is applied in three steps in the order of V _R , V _G , and V _B , so that the R signal, the G signal, and the B signal are read in sequence,
An avalanche multiplication occurs by the potential step. The method according to any one of claims 1 to 8,
A support substrate;
A wiring portion formed on the support substrate;
A pixel formed on the wiring part and including a photoelectric conversion part for photoelectrically converting incident light to obtain an electrical signal; And
Further comprising a silicon layer including a peripheral circuit formed around the pixel,
The photoelectric conversion layer is formed on the outermost surface on the light incident side of the silicon layer, and includes a first electrode layer formed on the silicon substrate, the photoelectric conversion layer, and a second electrode layer formed on the photoelectric conversion layer. Solid-state imaging device. The method according to claim 3 or 4,
PIN structure or PN structure in the horizontal direction of the silicon substrate; And
Wide gap side near the interface between the second photoelectric conversion layer and the third photoelectric conversion layer, Wide gap side near the interface between the first photoelectric conversion layer and the second photoelectric conversion layer or the first photoelectric conversion layer and the silicon And a barrier formed on the wide gap side near the interface of the substrate and having an energy greater than 26 meV. 4. The method according to any one of claims 1 to 3,
A first photoelectric conversion unit including a photoelectric conversion layer;
A second photoelectric conversion unit including a photoelectric conversion layer; And
Further comprising a third photoelectric conversion unit including a photoelectric conversion layer,
The photoelectric conversion layer of the first photoelectric conversion unit is a first photoelectric conversion layer for spectroscopic red light,
The photoelectric conversion layer of the second photoelectric conversion unit is a second photoelectric conversion layer for spectroscopy of green light,
And said photoelectric conversion layer is a third photoelectric conversion layer for spectroscopic blue light. The method according to any one of claims 3 to 5, 7, 8 and 11,
The first photoelectric conversion layer is made of CuAl _x Ga _y In _z S ₂ , wherein 0 ≦ x ≦ 0.12, 0.38 ≦ y ≦ 0.52, 0.48 ≦ z ≦ 0.50 and x + y + z = 1,
The second photoelectric conversion layer is made of CuAl _x Ga _y In _z S ₂ , wherein 0.06 ≦ x ≦ 0.41, 0.01 ≦ y ≦ 0.45, 0.49 ≦ z ≦ 0.58 and x + y + z = 1,
The third photoelectric conversion layer is composed of CuAl _x Ga _y S _u Se _v , where 0.31≤x≤0.52, 0.48≤y≤0.69, 1.33≤u≤1.38, 0.62≤v≤0.67, and also x + y + u + v = 3, or x + y = 1 and u + v = 2. The method of claim 12,
The first photoelectric conversion layer is formed of a _{CuGa 0 .52 In 0 .48 S 2} ,
The second photoelectric conversion layer is formed of a _{.23 CuAl 0 .24 Ga 0 In 0} .53 S 2,
The third photoelectric conversion layer is a solid-state imaging device which comprises a _{.28 CuAl 0 .36 Ga 0 .64 S} 1 Se 0 .72. The method according to any one of claims 3 to 5, 7, 8 and 11,
The first photoelectric conversion layer is composed of CuGa _y In _z S _u Se _v , where 0.52 ≦ y ≦ 0.76, 0.24 ≦ z ≦ 0.48, 1.70 ≦ u ≦ 2.00, 0 ≦ _v ≦ 0.30, and also y + z + u + v = 3, or y + z = 1 and u + v = 2,
The second photoelectric conversion layer is made of CuGa _y In _{z Z n w} S _u Se _v , where 0.64 ≦ _y ≦ 0.88, 0 ≦ _z ≦ 0.36, 0 ≦ _w ≦ 0.12, 0.15 ≦ _u ≦ 1.44, 0.56 ≦ _v ≦ 1.85, y + z + w + u + v = 2,
The third photoelectric conversion layer is composed of CuGa _y Zn _w S _u Se _v , and also 0.74 ≦ y ≦ 0.91, 0.09 ≦ w ≦ 0.26, 1.42 ≦ u ≦ 1.49, 0.51 ≦ _v ≦ 0.58, and y + w + u + v = 3, wherein the solid-state imaging device. A photoelectric conversion layer made of a chalcoprite-based compound semiconductor lattice matched on a silicon substrate and composed of a copper-aluminum-gallium-indium-sulfur-selenium mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium mixed crystal. The manufacturing method of the solid-state imaging device characterized by having the process of forming a film. The method of claim 15,
And forming a first photoelectric conversion part including a photoelectric conversion layer, a second photoelectric conversion part including a photoelectric conversion layer, and a third photoelectric conversion part including a photoelectric conversion layer in a plane direction of the silicon substrate. ,
The photoelectric conversion layer of the first photoelectric conversion unit is a first photoelectric conversion layer for spectroscopic red light,
The photoelectric conversion layer of the second photoelectric conversion unit is a second photoelectric conversion layer for spectroscopy of green light,
And said photoelectric conversion layer is a third photoelectric conversion layer for spectroscopy blue light. A condensing optical system for condensing incident light;
A solid-state imaging device for receiving and photoelectrically converting light collected by the condensing optical system; And
A signal processing unit for processing the photoelectrically converted signal,
The solid-state imaging device,
A photoelectric conversion layer formed by lattice matching on a silicon substrate and formed of a chalcoprite-based compound semiconductor of copper-aluminum-gallium-indium-sulfur-selenium mixed crystal or copper-aluminum-gallium-indium-zinc-sulfur-selenide mixed crystal An imaging device comprising a.

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