KR20100085654A - Flash memory device and manufacturing of the same - Google Patents

Flash memory device and manufacturing of the same Download PDF

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KR20100085654A
KR20100085654A KR1020090005065A KR20090005065A KR20100085654A KR 20100085654 A KR20100085654 A KR 20100085654A KR 1020090005065 A KR1020090005065 A KR 1020090005065A KR 20090005065 A KR20090005065 A KR 20090005065A KR 20100085654 A KR20100085654 A KR 20100085654A
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film
semiconductor
semiconductor substrate
semiconductor film
layer
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Korean (ko)
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최재욱
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

PURPOSE: A flash memory device and a manufacturing method thereof are provided to improve a program speed by accumulating charges in a semiconductor film in a program operation by forming a semiconductor film between a semiconductor substrate and a tunnel insulation film. CONSTITUTION: A semiconductor substrate(101) is comprised of a bulk structure including an N well or P well and an ion for controlling a threshold voltage. A semiconductor film(103) is formed on the upper side of the semiconductor substrate. A tunnel insulation layer(105) is formed on the upper side of the semiconductor film. A charge trapping layer(107) is formed on the upper side of the tunnel insulation layer.

Description

플래시 메모리 소자 및 그 제조방법{Flash memory device and manufacturing of the same} Flash memory device and manufacturing method thereof

본 발명은 플래시 메모리 소자 및 그 제조방법에 관한 것으로서 특히, 터널링 계수를 개선하여 프로그램 속도를 높일 수 있는 플래시 메모리 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device capable of increasing a program speed by improving a tunneling coefficient and a method of manufacturing the same.

플래시 메모리 소자는 플로팅 게이트, 유전체막 및 컨트롤 게이트가 적층된 게이트 구조를 갖는 다수의 메모리 셀을 포함한다. 메모리 셀의 적층형 게이트는 터널 절연막을 사이에 두고 반도체 기판의 상부에 형성된다.The flash memory device includes a plurality of memory cells having a gate structure in which a floating gate, a dielectric layer, and a control gate are stacked. The stacked gate of the memory cell is formed on the semiconductor substrate with the tunnel insulating film interposed therebetween.

프로그램 동작은 FN 터널링(Fowler-Nordheim tunneling)에 의해 채널을 통과하는 열-전자의 일부가 터널 절연막을 통해 플로팅 게이트에 주입됨으로써 이루어진다. 즉, 프로그램 동작은 FN 터널링에 의해 전자가 기판으로부터 플로팅 게이트에 주입됨으로써 이루어진다.The program operation is achieved by injecting a portion of the heat-electrons through the channel through the tunnel insulation into the floating gate by means of Fowler-Nordheim tunneling. That is, the program operation is performed by injecting electrons from the substrate into the floating gate by FN tunneling.

종래 플래시 메모리 소자의 적층형 게이트 형성방법을 구체적으로 설명하면 먼저, 반도체 기판의 상부에 터널 절연막 및 플로팅 게이트용 도전막을 증착한 후, 플로팅 게이트용 도전막의 상부에 소자 분리 하드 마스크를 형성한다. Referring to a method of forming a stacked gate of a conventional flash memory device in detail, first, a tunnel insulating film and a floating gate conductive film are deposited on a semiconductor substrate, and then a device isolation hard mask is formed on the floating gate conductive film.

이 후, 소자 분리 하드 마스크를 식각 마스크로 이용한 식각 공정으로 플로팅 게이트용 도전막 및 터널 절연막을 식각하여 반도체 기판을 노출시킨다.Thereafter, the semiconductor substrate is exposed by etching the conductive film and the tunnel insulating film for the floating gate by an etching process using the device isolation hard mask as an etching mask.

이어서 노출된 반도체 기판을 식각하여 트렌치를 형성하고, 트렌치 내부를 절연물로 매립하여 소자 분리막을 형성한다. 이러한 소자 분리막의 형성으로 반도체 기판의 활성 영역이 정의되고, 터널 절연막 및 플로팅 게이트용 도전막은 활성 영역의 상부에만 잔여한다. Subsequently, the exposed semiconductor substrate is etched to form trenches, and the inside of the trench is filled with an insulator to form an isolation layer. The formation of the device isolation film defines the active region of the semiconductor substrate, and the tunnel insulating film and the conductive film for the floating gate remain only on the active region.

소자 분리막 형성 후, 소자 분리막의 EFH(effective field oxide height)를 조절한다. 이 후, 소자 분리 마스크를 제거한다.After the device isolation layer is formed, the effective field oxide height (EFH) of the device isolation layer is controlled. After that, the device isolation mask is removed.

이어서 소자 분리막 및 플로팅 게이트용 도전막의 상부에 유전체막, 컨트롤 게이트용 도전막 및 게이트 하드 마스크를 적층한다. 이 후, 게이트 하드 마스크를 식각 마스크로 이용한 식각 공정으로 컨트롤 게이트용 도전막, 유전체막, 및 플로팅 게이트용 도전막을 식각하여 적층형 게이트를 형성한다.Subsequently, a dielectric film, a control gate conductive film, and a gate hard mask are stacked over the device isolation film and the floating gate conductive film. Subsequently, in the etching process using the gate hard mask as an etching mask, the control gate conductive film, the dielectric film, and the floating gate conductive film are etched to form a stacked gate.

상술한 바와 같은 일련의 공정을 통해 형성된 적층형 게이트를 포함하는 플래시 메모리 소자의 프로그램 속도는 컨트롤 게이트와 플로팅 게이트의 접촉 면적을 증가시켜서 커플링 비율을 증가시킴으로써 개선할 수 있다. 그러나, 커플링 비율은 플로팅 게이트 및 소자 분리막 사이의 단차 부분을 제외하고는 평면적 구조에 의하여 결정되므로 커플링 비율을 증가시키는 데는 한계가 있다. 즉 종래 기술로는 프로그램 속도를 개선하는 데에 한계가 있다.The program speed of a flash memory device including a stacked gate formed through a series of processes as described above may be improved by increasing a coupling ratio by increasing a contact area between a control gate and a floating gate. However, since the coupling ratio is determined by the planar structure except for the stepped portion between the floating gate and the device isolation layer, there is a limit in increasing the coupling ratio. That is, there is a limit in improving the program speed in the prior art.

본 발명은 터널링 계수를 개선하여 프로그램 속도를 높일 수 있는 플래시 메모리 소자 및 그 제조 방법을 제공한다.The present invention provides a flash memory device and a method of manufacturing the same that can improve the program speed by improving the tunneling coefficient.

본 발명에 따른 플래시 메모리 소자는 문턱 전압 조절용 이온 및 N웰 또는 P웰을 포함하는 벌크 구조가 형성된 반도체 기판, 반도체 기판의 상부에 형성된 순수한 반도체막, 반도체막 상부에 형성된 터널 절연막, 및, 터널 절연막의 상부에 형성된 전하 저장막을 포함한다.A flash memory device according to the present invention is a semiconductor substrate having a bulk structure including a threshold voltage control ion and an N well or P well, a pure semiconductor film formed on the semiconductor substrate, a tunnel insulating film formed on the semiconductor film, and a tunnel insulating film It includes a charge storage film formed on top of.

본 발명에 따른 플래시 메모리 소자의 제조방법은 문턱 전압 조절용 이온 및 N웰 또는 P웰을 포함하는 벌크 구조가 형성된 반도체 기판을 마련하는 단계, 반도체 기판의 상부에 순수한 반도체막, 터널 절연막, 및 전하 저장막을 형성하는 단계, 전하 저장막, 터널 절연막, 반도체막, 및 반도체 기판을 식각하여 반도체 기판에 소자 분리 트렌치를 형성하고, 소자 분리 트렌치를 사이에 두고 분리된 활성영역을 정의하는 단계, 및 소자 분리 트렌치 내부에 소자 분리막을 형성하는 단계를 포함한다.A method of manufacturing a flash memory device according to the present invention comprises the steps of providing a semiconductor substrate having a bulk structure including a threshold voltage control ion and an N well or P well, a pure semiconductor film, a tunnel insulating film, and charge storage on the semiconductor substrate Forming a film, etching the charge storage film, the tunnel insulating film, the semiconductor film, and the semiconductor substrate to form a device isolation trench in the semiconductor substrate, defining a separated active region with the device isolation trench therebetween, and device isolation Forming an isolation layer in the trench.

반도체막은 실리콘 및 게르마늄 중 적어도 어느 하나를 포함한다.The semiconductor film contains at least one of silicon and germanium.

반도체막은 원자층 증착 방법 또는 물리 기상 증착 방법을 이용하여 형성한다.The semiconductor film is formed using an atomic layer deposition method or a physical vapor deposition method.

반도체막은 30Å 내지 100Å의 두께로 형성된다.The semiconductor film is formed to a thickness of 30 kPa to 100 kPa.

본 발명은 반도체 기판과 터널 절연막의 사이에 반도체 막을 형성함으로써 프로그램 동작시 반도체막에 전하를 축적하여 터널링 계수를 증가시킬 수 있다. 이에 따라 본 발명은 터널링 전류를 증가시켜 프로그램 속도를 개선할 수 있다.According to the present invention, by forming a semiconductor film between the semiconductor substrate and the tunnel insulating film, charge can be accumulated in the semiconductor film during a program operation to increase the tunneling coefficient. Accordingly, the present invention can improve the program speed by increasing the tunneling current.

본 발명은 플래시 메모리 소자의 동작에서 가장 느린 프로그램 속도를 개선하여 전체적인 플래시 메모리 소자의 동작 속도를 개선할 수 있다.The present invention can improve the slowest program speed in the operation of the flash memory device to improve the overall operating speed of the flash memory device.

또한 본 발명은 추가적인 공정 투자 비용을 크게 증대시키지 않으면서 프로그램 속도를 개선할 수 있다.In addition, the present invention can improve program speed without significantly increasing additional process investment costs.

그리고 본 발명은 기존 공정을 사용할 수 있으므로 공정 개발에 큰 시간을 소요하지 않아도 된다.In addition, the present invention can use the existing process does not require a large time for the process development.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 플래시 메모리 소자의 제조방 법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 문턱 전압 조절용 이온이 주입되고 P웰 또는 N웰을 포함하는 벌크(bulk)구조가 형성된 반도체 기판(101) 상에 반도체막(103), 터널 절연막(105), 전하 저장막(107), 버퍼막(111), 소자 분리 하드 마스크막(117), 반사 방지막(119) 및 포토레지스트 패턴(121)을 순차적으로 형성한다. Referring to FIG. 1A, a semiconductor film 103, a tunnel insulating film 105, and a charge storage film are formed on a semiconductor substrate 101 having a bulk structure including a P well or an N well implanted with threshold voltage control ions. 107, the buffer film 111, the element isolation hard mask film 117, the antireflection film 119, and the photoresist pattern 121 are sequentially formed.

반도체막(103)은 비정질 반도체 물질을 이용하여 형성한다. 또한 반도체막(103)은 터널 절연막(105)의 에피택시(epitaxy)를 위하여 100Å 이하의 두께로 증착되는 것이 바람직하며, 프로그램 동작시 전하의 축적을 위하여 30Å 이상의 두께로 증착되는 것이 바람직하다. 이와 같이 30Å 내지 100Å으로 얇은 두께로 반도체막(103)을 증착하기 위하여 반도체막(103)은 원자층 증착 방법(Atomic Layer Deposition) 또는 낮은 증착률(Low Deposition Rate)의 물리 기상 증착 방법(Physical Vapor Deposition) 방법으로 형성하는 것이 바람직하다. 반도체 물질로는 실리콘(Si) 및 게르마늄(Ge) 중 적어도 어느 하나를 이용한다. 이와 같은 반도체막(103)은 문턱 전압 조절용 이온이 주입되고 벌크 구조가 형성된 반도체 기판(101)과는 달리 불순물 이온이 주입되지 않은 순수 반도체 물질로 이루어진다. The semiconductor film 103 is formed using an amorphous semiconductor material. In addition, the semiconductor film 103 is preferably deposited to a thickness of 100 GPa or less for epitaxy of the tunnel insulating film 105, and is preferably deposited to a thickness of 30 GPa or more for accumulation of charge during a program operation. As described above, in order to deposit the semiconductor film 103 in a thin thickness from 30 to 100 microseconds, the semiconductor film 103 may be formed by an atomic layer deposition method or a low deposition rate physical vapor deposition method. It is preferable to form by the Deposition method. At least one of silicon (Si) and germanium (Ge) may be used as the semiconductor material. The semiconductor film 103 is made of a pure semiconductor material in which impurity ions are not implanted, unlike the semiconductor substrate 101 in which the threshold voltage adjustment ions are implanted and the bulk structure is formed.

터널 절연막(105)은 산화막을 이용하여 형성할 수 있다.The tunnel insulating film 105 can be formed using an oxide film.

전하 저장막(107)은 플로팅 게이트용 도전막으로서 폴리 실리콘을 이용하여 형성할 수 있다.The charge storage film 107 may be formed using polysilicon as the conductive film for the floating gate.

버퍼막(109)은 소자 분리 하드 마스크막(119) 형성시 전하 저장막(107)에 가해지는 스트레스를 완화하기 위해 형성된다.The buffer film 109 is formed to relieve stress applied to the charge storage film 107 when the device isolation hard mask film 119 is formed.

소자 분리 하드 마스크막(119)은 질화막(113), 산화막(113) 및 카본(carbon)막(115)의 적층 구조로 형성될 수 있다.The device isolation hard mask layer 119 may have a stacked structure of a nitride layer 113, an oxide layer 113, and a carbon layer 115.

반사 방지막(119)은 포토레지스트 패턴(121)을 형성하기 위한 노광 공정 진행시 광원의 난반사를 방지하기 위해 형성되는 것이다. 이러한 반사 방지막(119)은 SiON을 이용하여 형성할 수 있다.The anti-reflection film 119 is formed to prevent diffuse reflection of the light source during the exposure process for forming the photoresist pattern 121. The anti-reflection film 119 may be formed using SiON.

도 1b를 참조하면, 포토레지스트 패턴(121)을 식각 마스크로 사용하는 식각 공정으로 소자 분리 하드 마스크막(117)을 식각하여 소자 분리 하드 마스크 패턴(117a)을 형성한다. 이 후, 소자 분리 하드 마스크 패턴(117a)을 식각 마스크로 사용하는 식각 공정으로 터널 절연막(105), 반도체막(103) 및 반도체 기판(101)을 식각하여 반도체 기판(101)에 소자 분리 트렌치(123)을 형성한다. 이로써, 소자 분리 트렌치(123)를 사이에 두고 분리된 활성 영역(A)이 정의된다. 또한 활성 영역(A)의 상부에는 반도체막(103), 터널 절연막(105), 전하 저장막(107), 버퍼막(105) 및 소자 분리 하드 마스크 패턴(117a)의 질화막(111)과 산화막(113)이 잔여한다. 상술한 일련의 공정을 실시하는 과정에서 포토레지스트 패턴, 반사 방지막 및 카본막이 제거될 수 있다. Referring to FIG. 1B, the device isolation hard mask layer 117 may be etched to form the device isolation hard mask pattern 117a by an etching process using the photoresist pattern 121 as an etching mask. Thereafter, the tunnel insulating film 105, the semiconductor film 103, and the semiconductor substrate 101 are etched by an etching process using the device isolation hard mask pattern 117a as an etching mask, and the device isolation trench (eg, a semiconductor device 101 may be removed). 123). As a result, the active region A separated by the device isolation trench 123 is defined. In addition, the nitride film 111 and the oxide film of the semiconductor film 103, the tunnel insulating film 105, the charge storage film 107, the buffer film 105, and the device isolation hard mask pattern 117a are disposed on the active region A. 113) remains. The photoresist pattern, the anti-reflection film, and the carbon film may be removed in the course of performing the series of processes described above.

도 1c를 참조하면, 소자 분리 트렌치 내부가 매립될 수 있도록 소자 분리 트렌치를 포함하는 소자 분리 하드 마스크 패턴의 상부에 충분한 두께의 절연막을 형성한다. 이 후, 소자 분리 하드 마스크 패턴의 질화막(111)에서 정지되는 평탄화 공정을 실시하여 절연막의 표면을 평탄화시킴과 아울러 질화막(111)이 노출되도록 하여 소자 분리 트렌치 내부에 소자 분리막(125)을 형성한다.Referring to FIG. 1C, an insulating film having a sufficient thickness is formed on the device isolation hard mask pattern including the device isolation trench so that the device isolation trench may be embedded. Thereafter, a planarization process of stopping the nitride film 111 of the device isolation hard mask pattern is performed to planarize the surface of the insulating film and to expose the nitride film 111 to form the device isolation film 125 inside the device isolation trench. .

도 1d를 참조하면, 질화막 및 버퍼막을 제거하고, 소자 분리막(125)의 EFH(Effective Field oxide Height)를 조절하기 위한 식각 공정을 실시한다. 이로써 반도체 기판(101)의 활성 영역(A) 상부에 반도체막(103), 터널 절연막(105) 및 전하 저장막(107)이 적층되고, 활성 영역(A) 사이에 전하 저장막(107)의 표면보다 낮은 저면을 갖는 소자 분리막(125)이 형성된다.Referring to FIG. 1D, the nitride layer and the buffer layer are removed, and an etching process for adjusting the effective field oxide height (EFH) of the device isolation layer 125 is performed. As a result, the semiconductor film 103, the tunnel insulating film 105, and the charge storage film 107 are stacked on the active region A of the semiconductor substrate 101, and the charge storage film 107 is formed between the active regions A. An isolation layer 125 having a bottom lower than the surface is formed.

도면에 도시하지 않았으나, 이 후 유전체막 및 컨트롤 게이트용 도전막을 증착하고 활성 영역(A)에 교차되는 방향으로 컨트롤 게이트용 도전막, 유전체막 및 전하 저장막을 패터닝하여 적층형 게이트를 형성한다.Although not shown in the drawings, a dielectric film and a conductive film for a control gate are then deposited and the control gate conductive film, the dielectric film, and the charge storage film are patterned in a direction crossing the active region A to form a stacked gate.

이와 같이 반도체 기판(101)의 활성 영역(A)과 터널 절연막(105) 사이에 형성된 반도체막(103)은 플래시 메모리 소자의 프로그램 동작시 전하를 축적하여 터널링 계수를 현격하게 증가시킨다. 이는 터널링 계수의 증가는 터널링 전류의 증가를 가져오게 되어 프로그램 속도를 개선할 수 있다.As described above, the semiconductor film 103 formed between the active region A of the semiconductor substrate 101 and the tunnel insulating film 105 accumulates electric charges during the program operation of the flash memory device, thereby significantly increasing the tunneling coefficient. This increases the tunneling coefficient can lead to an increase in the tunneling current can improve the program speed.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 플래시 메모리 소자의 제조방법을 설명하기 위한 단면도들.1A to 1D are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 103 : 반도체막101 semiconductor substrate 103 semiconductor film

105 : 터널 절연막 107 : 전하 저장막105 tunnel insulating film 107 charge storage film

109 : 버퍼막 111 : 질화막109: buffer film 111: nitride film

113 : 산화막 115 : 카본막113: oxide film 115: carbon film

117 : 소자 분리 하드 마스크막 119 : 반사 방지막117: device isolation hard mask film 119: antireflection film

121 : 포토레지스트 패턴 125 : 소자 분리막121: photoresist pattern 125: device isolation film

A : 활성 영역A: active area

Claims (7)

문턱 전압 조절용 이온 및 N웰 또는 P웰을 포함하는 벌크 구조가 형성된 반도체 기판;A semiconductor substrate having a bulk structure including threshold voltage adjusting ions and N wells or P wells; 상기 반도체 기판의 상부에 형성된 순수한 반도체막;A pure semiconductor film formed on the semiconductor substrate; 상기 반도체막 상부에 형성된 터널 절연막; 및A tunnel insulating film formed over the semiconductor film; And 상기 터널 절연막의 상부에 형성된 전하 저장막을 포함하는 플래시 메모리 소자. And a charge storage layer formed on the tunnel insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 반도체막은 실리콘 및 게르마늄 중 적어도 어느 하나를 포함하는 플래시 메모리 소자.The semiconductor film includes at least one of silicon and germanium. 제 1 항에 있어서,The method of claim 1, 상기 반도체막은 30Å 내지 100Å의 두께로 형성된 플래시 메모리 소자.The semiconductor film is a flash memory device formed to a thickness of 30 ~ 100Å. 문턱 전압 조절용 이온 및 N웰 또는 P웰을 포함하는 벌크 구조가 형성된 반도체 기판을 마련하는 단계;Providing a semiconductor substrate having a bulk structure including a threshold voltage adjusting ion and an N well or a P well; 상기 반도체 기판의 상부에 순수한 반도체막, 터널 절연막, 및 전하 저장막을 형성하는 단계;Forming a pure semiconductor film, a tunnel insulating film, and a charge storage film on the semiconductor substrate; 상기 전하 저장막, 상기 터널 절연막, 상기 반도체막, 및 상기 반도체 기판을 식각하여 상기 반도체 기판에 소자 분리 트렌치를 형성하고, 상기 소자 분리 트렌치를 사이에 두고 분리된 활성영역을 정의하는 단계; 및Etching the charge storage layer, the tunnel insulating layer, the semiconductor layer, and the semiconductor substrate to form an isolation trench in the semiconductor substrate, and defining an active region separated through the isolation trench; And 상기 소자 분리 트렌치 내부에 소자 분리막을 형성하는 단계를 포함하는 플래시 메모리 소자의 제조방법.Forming a device isolation layer in the device isolation trench. 제 4 항에 있어서,The method of claim 4, wherein 상기 반도체막은 실리콘 및 게르마늄 중 적어도 어느 하나를 포함하는 플래시 메모리 소자의 제조방법.And the semiconductor film comprises at least one of silicon and germanium. 제 4 항에 있어서,The method of claim 4, wherein 상기 반도체막은 원자층 증착 방법 또는 물리 기상 증착 방법을 이용하여 형성하는 플래시 메모리 소자의 제조방법.And the semiconductor film is formed using an atomic layer deposition method or a physical vapor deposition method. 제 4 항에 있어서,The method of claim 4, wherein 상기 반도체막은 30Å 내지 100Å의 두께로 형성된 플래시 메모리 소자의 제조방법.The semiconductor film is a method of manufacturing a flash memory device having a thickness of 30 ~ 100Å.
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