CN102054781B - Vertical flash memory structure and manufacturing method thereof - Google Patents
Vertical flash memory structure and manufacturing method thereof Download PDFInfo
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- CN102054781B CN102054781B CN 200910198589 CN200910198589A CN102054781B CN 102054781 B CN102054781 B CN 102054781B CN 200910198589 CN200910198589 CN 200910198589 CN 200910198589 A CN200910198589 A CN 200910198589A CN 102054781 B CN102054781 B CN 102054781B
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Abstract
The invention discloses a vertical flash memory structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a substrate and forming a source region on the substrate; forming a first dielectric layer on a horizontal surface of the source region, wherein the first dielectric layer covers the source region; forming an opening in the first dielectric layer, wherein a part of the source region is exposed by the opening; forming a silicon material layer in the opening to serve as an active region; removing a part of the first dielectric layer in the vertical direction and exposing a vertical surface of the active region; forming a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate on the vertical surface of the active region along the horizontal direction; and forming a drain region on the horizontal surface of the active region. Through the structure and the method, the on resistance of a channel is reduced, and device performance is improved.
Description
Technical field
The present invention relates to semiconductor device and technical field of manufacturing semiconductors, particularly a kind of rectilinear flash memory structure and manufacturing approach thereof.
Background technology
Along with development of semiconductor, flash memory (flash memory) has obtained using widely as a kind of non-volatility memorizer.Flash memory has increased a floating boom and one deck tunnel oxide on traditional M OS transistor arrangement basis, and utilizes floating boom to come stored charge, has realized the non-volatile of memory contents.
The patent No. is that the Chinese patent of ZL03151284.4 discloses a kind of rectilinear flash memory structure and manufacturing approach thereof.Fig. 1 to Fig. 6 has provided the cross-sectional view of above-mentioned rectilinear flash memory structure manufacturing approach.
As shown in Figure 1, semiconductor substrate 2 is provided, etching forms sunk area 4 on said semiconductor substrate 2, injects through ion afterwards to form source electrode and drain region 6 respectively.
As shown in Figure 2, fill insulant 8 in the sunk area 4 on said semiconductor substrate 2, said insulating material 8 covers said sunk area 4 fully, uses chemico-mechanical polishing that leveling is carried out on the surface of said semiconductor substrate 2 afterwards.
As shown in Figure 3, said insulating material 8 is carried out etching exposing part sunk area 4, and residual a part of insulating material is on said semiconductor substrate 2, the thickness of said residual insulating material 8 is about 0.1 micron.
As shown in Figure 4, on the wall of said sunk area 4, form oxide layer 10; The silicon grain 12 that on the vertical surface of said oxide layer 10, forms dispersion shape more afterwards is as floating boom (floating gate); Afterwards, deposition one deck silica silicon nitride (ON) or silica silicon nitride silica (ONO) material film 14 on the vertical surface of said dispersion shape silicon grain 12 as compound medium layer; On the vertical surface of said film 14, form armorphous silicon layer 16 then as control gate (control gate); Deposit an insulating barrier 18 at last in said sunk area 4, and use chemico-mechanical polishing to carry out leveling.
As shown in Figure 5, use selective etch to remove part dispersion shape silicon grain 12 and armorphous silicon layer 16, define suitable channel length (channel length).
As shown in Figure 6, after said dispersion shape silicon grain 12 and armorphous silicon layer 16 are carried out etching,, and use chemico-mechanical polishing to carry out leveling at said etched portions fill insulant 20.
The rectilinear flash memory structure of such scheme manufacturing gained is as shown in Figure 6; Fig. 6 has comprised two rectilinear flash cells; Be respectively flash cell 30 and flash cell 40; Its conducting channel 22 almost with the perpendicular of said semiconductor substrate 2, be example with the flash cell among Fig. 6 30, its conducting channel 22 is extended to the high order end of drain region 6 by the low order end of source region 6.But; Because formation is injected through passing through ion after forming sunk area in etching on the substrate 2 in said source/drain region 6, source electrode does not have region covered each other with drain electrode, makes that said conducting channel 22 is to connect end to end; Said conducting channel 22 is all very little with the contact area of source/drain region 6; Make that effective raceway groove degree of depth in the horizontal direction is more shallow, cause conducting resistance to increase, reduced the reaction rate of device.
Summary of the invention
The problem that the present invention solves has provided a kind of rectilinear flash memory structure and manufacturing approach thereof, has reduced turn resistance, has improved device performance.
The invention provides a kind of rectilinear flash memory making method, comprise the steps:
Substrate is provided, on said substrate, forms the source region;
On the horizontal surface of said source region, form first dielectric layer, said first dielectric layer covers said source region;
In said first dielectric layer, form opening, said opening exposes the part in said source region;
In said opening, form silicon material layer, as active area;
Remove the part of said first dielectric layer, expose the vertical surface of said active area;
Along continuous straight runs forms floating gate dielectric layer, floating boom, control gate dielectric layer and control gate successively on the vertical surface of said active area;
On the horizontal surface of said active area, form the drain region.
Optional, the formation method of active area is selective epitaxial growth (SEG).
Optional, the material of said floating gate dielectric layer is a silica.
Optional, said control gate dielectric layer is nitrogenize silicon/oxidative silicon laminated construction or silicon oxide/silicon nitride/silicon oxide stack structure.
Optional, the material of said floating gate layer and control grid layer is polysilicon or doped amorphous silicon.
Optional, the formation method in said drain region is that selective epitaxial growth or ion inject.
Optional, after etching was removed the part of said first dielectric layer, the thickness of remaining first dielectric layer was 50 dust to 1000 dusts.
Optional, comprise forming floating gate dielectric layer, floating boom, control gate dielectric layer and control gate on the vertical surface of said active area successively: along continuous straight runs forms floating gate dielectric layer, floating gate layer, control gate dielectric layer, control grid layer and second dielectric layer successively on the vertical surface at said active area; Remove part floating gate layer and control grid layer with the vertical direction etching, form floating boom and control gate, and in the groove that etching forms, fill the 3rd dielectric layer; Along continuous straight runs carries out leveling to the surface of said second dielectric layer, the 3rd dielectric layer, floating gate dielectric layer, control gate dielectric layer and active area.
In order to address the above problem, the present invention also provides a kind of rectilinear flash memory structure, comprising:
Substrate;
The source region is formed on the horizontal surface of said substrate;
Active area is formed on the horizontal surface in said source region the source region, cover part;
First dielectric layer covers on the surface in source region of said active area both sides;
Floating gate dielectric layer is formed on the vertical surface of said active area;
Floating boom is formed on the vertical surface of said floating gate dielectric layer;
The control gate dielectric layer is formed on the vertical surface of said floating boom;
Control gate is formed on the vertical surface of said control gate dielectric layer;
The drain region is formed on the horizontal surface of said active area.
Optional, monocrystalline silicon or the amorphous silicon material of said active area for mixing.
Optional, the doping type in said source region and drain region is identical, and opposite with the doping type of said active area.
Optional, the material of said floating gate dielectric layer is a silica.
Optional, said control gate dielectric layer is nitrogenize silicon/oxidative silicon laminated construction or silicon oxide/silicon nitride/silicon oxide stack structure.
Optional, the material of said floating boom and control gate is polysilicon or doped amorphous silicon.
Compared with prior art, above-mentioned disclosed technical scheme has following advantage:
In above-mentioned disclosed rectilinear flash memory structure and the manufacturing approach thereof; At first form the source region; On the horizontal surface in source region, be formed with source region and drain region afterwards, with prior art end to end conducting channel compare, the conducting channel of present technique scheme is the connection of face to face; Reduce the resistance of conducting channel, improved device performance.
Description of drawings
Fig. 1 to Fig. 6 is the cross-sectional view of the rectilinear flash memory system making method of prior art;
Fig. 7 is the schematic flow sheet of the rectilinear flash memory structure manufacturing approach of the embodiment of the invention;
Fig. 8 to Figure 15 is the cross-sectional view of the rectilinear flash memory structure manufacturing approach of the embodiment of the invention.
Embodiment
The invention provides a kind of rectilinear flash memory structure and manufacturing approach thereof, at first form the source region, on the horizontal surface in source region, be formed with source region and drain region afterwards, increased the degree of depth of effective raceway groove, reduced the resistance of conducting channel, improved device performance.
For make method of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 7 has provided the schematic flow sheet of the rectilinear flash memory structure manufacturing approach of the embodiment of the invention.As shown in Figure 7, execution in step S1 provides substrate, on said substrate, forms the source region; Execution in step S2 forms first dielectric layer on the horizontal surface of said source region, said first dielectric layer covers said source region; Execution in step S3 forms opening in said first dielectric layer, said opening exposes the part in said source region; Execution in step S4 forms silicon material layer, as active area in said opening; Execution in step S5 removes the part of said first dielectric layer, exposes the vertical surface of said active area; Execution in step S6, along continuous straight runs forms floating gate dielectric layer, floating boom, control gate dielectric layer and control gate successively on the vertical surface of said active area; Execution in step S7 forms the drain region on the horizontal surface of said active area.
Fig. 8 to Figure 15 is the cross-sectional view of the rectilinear flash memory structure manufacturing approach of the embodiment of the invention, below in conjunction with Fig. 7 embodiments of the invention is elaborated.
Like Fig. 7 and shown in Figure 8, execution in step S1 provides substrate 100, on said substrate 100, forms source region 101.
The material of said substrate 100 can be a kind of in monocrystalline silicon, the amorphous silicon, and the material of said substrate 100 also can be a silicon Germanium compound, and said substrate 100 can also be an epitaxial layer structure on silicon-on-insulator (SOI, SiliconOn Insulator) structure or the silicon.
The formation method in said source region 101 is that ion injects, and according to type of device, if the P type semiconductor device then injects III family element ion, if the N type semiconductor device then injects the V group element ion, injects the degree of depth and be tens to hundreds of dusts.After said source region 101 forms, also comprise said substrate 100 is heat-treated, activate injecting ion, and make that the part diffusion takes place to inject ion.
Like Fig. 7 and shown in Figure 9, execution in step S2 forms first dielectric layer 102 on 101 horizontal surfaces of said source region, and said first dielectric layer 102 covers said source region 101.Execution in step S3 forms opening 103a in said first dielectric layer 102 then, and said opening 103a exposes the part in said source region 101.
The material of said first dielectric layer 102 is an insulating material, like silica, and silicon nitride, carborundum etc., the material of selecting for use in the present embodiment are silica, its formation method is a chemical vapor deposition (CVD).
The deposit thickness of said first dielectric layer 102 is greater than the length of the conducting channel of rectilinear flash memory structure at least.
The formation method of said opening 103a is dry etching or wet etching, and method is a dry etching in the present embodiment.
Like Fig. 7 and shown in Figure 10, execution in step S4 forms silicon material layer, as active area 103 in said opening 103a.Said active area 103 fills up whole opening 103a.
Monocrystalline silicon or the amorphous silicon of the material of said active area 103 for mixing, the ion in its doping type and said source region 101 injects type opposite.
The formation method of said active area 103 is a selective epitaxial growth, and the key reaction thing is silane (SiH4) and the gas that contains said doped chemical.
Like Fig. 7 and shown in Figure 11, execution in step S5 removes the part of said first dielectric layer 102, exposes the vertical surface of said active area 103.In the present embodiment, use dry etching to remove after the part of said first dielectric layer 102, the thickness of the first residual dielectric layer 102a is 50 dust to 1000 dusts, and the thickness of the first residual dielectric layer 102a is 80 dusts described in the present embodiment.As previously mentioned; The thickness of first dielectric layer 102 is greater than the length of conducting channel, and in fact, the vertical surf zone of the said active area 103 that exposes conducting channel as rectilinear flash memory in subsequent process is regional; Therefore; The thickness of said first dielectric layer of removing 102 is substantially equal to channel length, and considers the thickness that needs the first residual dielectric layer 102a, and the gross thickness of said first dielectric layer 102 when forming is that the target length of raceway groove adds 50 dust to 1000 dusts.
Like Fig. 7, Figure 12, Figure 13 and shown in Figure 14, execution in step S6 forms floating gate dielectric layer, floating boom, control gate dielectric layer and control gate successively on the vertical surface of said active area.Be elaborated below in conjunction with Figure 12 to Figure 14.
Shown in figure 12, on the vertical surface of said active area 103, form floating gate dielectric layer 104, floating gate layer 105, control gate dielectric layer 106, control grid layer 107 and second dielectric layer 108 successively.
The material of said floating gate dielectric layer 104 is a silicon dioxide, and its formation method is thermal oxidation method or chemical vapour deposition (CVD), and the method that adopts in the present embodiment is chemical vapour deposition (CVD).The thickness of said floating gate dielectric layer 104 is 80 dust to 120 dusts.
The material of said floating gate layer 105 is polysilicon or doped amorphous silicon, and its formation method is chemical vapour deposition (CVD).
Said control gate medium 106 is the laminated construction of nitrogenize silicon/oxidative silicon or the laminated construction of silicon oxide/silicon nitride/silicon oxide layer by layer, and the formation method of said control grid layer 106 is chemical vapour deposition (CVD).
The material of said control grid layer 107 is polysilicon or doped amorphous silicon, and its formation method is chemical vapour deposition (CVD).
The material of said second dielectric layer 108 is an insulating material, like silica, and silicon nitride, carborundum etc., preferable material is a silica in the present embodiment, its formation method is chemical vapour deposition (CVD).
After said second dielectric layer 108 forms; Upper horizontal surface to said second dielectric layer 108, control grid layer 107, control gate dielectric layer 106, floating gate layer 105 and floating gate dielectric layer 104 is carried out leveling, makes the upper horizontal surface of above-mentioned rete flush with the upper horizontal surface of said active area 103.The method of leveling is chemico-mechanical polishing in the present embodiment.
Shown in figure 13, etching is removed the part of said floating gate layer 105 and control grid layer 107, forms floating boom 105a and control gate 107a.After etching, the part of removing that is etched above said floating boom 105a and the control gate 107a has formed groove.
Said lithographic method is a selective etch; Only etching is removed the part of said floating gate layer 105 and control grid layer 107; Main purpose is the length of said control gate 107a of control and floating boom 105a; Thereby the length of adjustment conducting channel, said conducting channel are positioned at said source region 103 by the part of said floating boom 105a and control gate 107a covering, and the length of the length of said conducting channel and said control gate 107a and floating boom 105a about equally.
Shown in figure 14, in the said groove that etching forms, fill the 3rd dielectric layer 105b and 107b.
The material of said the 3rd dielectric layer 105b, 107b is an insulating material, like silica, and silicon nitride, carborundum etc., preferable material is a silica in the present embodiment, its formation method is chemical vapour deposition (CVD).
After said the 3rd dielectric layer 105b and 107b formation; Upper horizontal surface to said the 3rd dielectric layer 105b and 107b, floating gate dielectric layer 104, control gate dielectric layer 106, second dielectric layer 108 and active area 103 is carried out leveling, and the upper horizontal surface of above-mentioned rete is flushed.In the present embodiment, leveling method is preferably chemico-mechanical polishing.After said leveling process; In vertical direction; The upper horizontal surface of said active area 103 exceeds about tens dusts of upper horizontal surface to hundreds of dusts of said control gate 107a and floating boom 105a; Also be that regional 103a length in vertical direction is tens to hundreds of dusts among Figure 14, said regional 103a is used to form the drain region in subsequent process.
Like Fig. 7 and shown in Figure 15, execution in step S7 forms drain region 109 on the horizontal surface of said active area 103.Thereby accomplish the manufacture process of said rectilinear flash memory structure.
The formation method in said drain region 109 is that ion injects or selective epitaxial growth, and the ionic type that said ion injects or the doping type of selective epitaxial growth are identical with the doping type in said source region 101.The method of selecting for use in the present embodiment is that ion injects, and its injection condition is consistent with the injection condition in said source region 101.After said drain region 109 forms, also comprise said substrate 100 is heat-treated, activate the ion that injects, and its part is diffused in the active area 103 by said floating boom 105a region covered.Simultaneously; In said heat treatment process; And in the thermal process that in the process that forms said floating gate dielectric layer 104, floating gate layer 105, control gate dielectric layer 106, control grid layer 107, second dielectric layer 108 and the 3rd dielectric layer 105b and 107b, relates to; Dopant ion in the said source region 101 all can spread in said active area 103; And have part ion to get in the said active area 103 by in the floating boom 105a region covered, and form the source region 101a that extends, make between source region 101 and drain region 109, can be formed electrical connection by the conducting channel 110 in the floating boom 105a overlay area in the active area 103.
Need to prove, in the process of execution in step S5, simultaneously first dielectric layer 102 of active area 103 both sides is removed in the present embodiment, expose the vertical surface of active area 103 both sides; In the process of execution in step S6, on the vertical surface of said active area 103 both sides, form floating gate dielectric layer, floating boom, control gate dielectric layer and control gate simultaneously respectively.Therefore; Present embodiment is equivalent to form simultaneously two rectilinear flash cells; In other embodiments of the invention, also can only form single rectilinear flash cell, the main distinction is: first dielectric layer 102 of when execution in step S5, only removing active area 103 1 sides; When execution in step S6, only form floating gate dielectric layer, floating boom, control gate dielectric layer and control gate in this side.
The rectilinear flash memory structure that present embodiment forms is shown in figure 15, has comprised two rectilinear flash memory structure unit among Figure 15, for individual unit, mainly comprises: substrate 100; Source region 101 is formed on the horizontal surface of said substrate 100; Active area 103 is formed on the level in said source region 101 source region, cover part 101; First dielectric layer 102 covers on the surface in source region 101 of said active area 103 both sides; Floating gate dielectric layer 104 is formed on the vertical surface of said active area 103; Floating boom 105a is formed on the vertical surface of said floating gate dielectric layer 104; Control gate dielectric layer 106 is formed on the vertical surface of said floating boom 105a; Control gate 107a is formed on the vertical surface of said control gate dielectric layer 106; Drain region 109 is formed on the horizontal surface of said active area 103.
Shown in figure 15, when reading said rectilinear flash memory structure, said active area 103 forms conducting channel 110 near the part of floating gate dielectric layer 104; Make and source region 101a and said source region 101 conductings of said drain region 109 through extending, at first form source region 101 owing in forming process; On source region 101, be formed with source region 103 and drain region 109 afterwards, therefore said drain region 109 is covered on the said source region 101, makes said conducting channel 110 be the connection of face to face; The contact area in itself and said source region 101 and drain region 109 is all bigger; Thereby make conducting channel 110 effective depth in the horizontal direction darker, reduced conducting resistance, improved device performance.
To sum up, the invention provides a kind of rectilinear flash memory structure and manufacturing approach thereof.Compared with prior art, the present invention has reduced the resistance of conducting channel, has improved device performance.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. a rectilinear flash memory making method is characterized in that, comprising:
Substrate is provided, on said substrate, forms the source region;
On the horizontal surface of said source region, form first dielectric layer, said first dielectric layer covers said source region;
In said first dielectric layer, form opening, said opening exposes the part in said source region;
In said opening, form silicon material layer, as active area;
Remove the part of said first dielectric layer, expose the vertical surface of said active area;
Along continuous straight runs forms floating gate dielectric layer, floating boom, control gate dielectric layer and control gate successively on the vertical surface of said active area;
On the horizontal surface of said active area, form the drain region.
2. rectilinear flash memory making method according to claim 1 is characterized in that, the formation method of said active area is a selective epitaxial growth.
3. rectilinear flash memory making method according to claim 1 is characterized in that, the material of said floating gate dielectric layer is a silica.
4. rectilinear flash memory making method according to claim 1 is characterized in that, said control gate dielectric layer is nitrogenize silicon/oxidative silicon laminated construction or silicon oxide/silicon nitride/silicon oxide stack structure.
5. rectilinear flash memory making method according to claim 1 is characterized in that, the material of said floating boom and control gate is polysilicon or doped amorphous silicon.
6. rectilinear flash memory making method according to claim 1 is characterized in that, the formation method in said drain region is that selective epitaxial growth or ion inject.
7. rectilinear flash memory making method according to claim 1 is characterized in that, remove the part of said first dielectric layer after, the thickness of remaining first dielectric layer is 50 dust to 1000 dusts.
8. rectilinear flash memory making method according to claim 1; It is characterized in that comprise forming floating gate dielectric layer, floating boom, control gate dielectric layer and control gate on the vertical surface of said active area successively: along continuous straight runs forms floating gate dielectric layer, floating gate layer, control gate dielectric layer, control grid layer and second dielectric layer successively on the vertical surface at said active area; Remove part floating gate layer and control grid layer with the vertical direction etching, form floating boom and control gate, and in the groove that etching forms, fill the 3rd dielectric layer; Along continuous straight runs carries out leveling to the surface of said second dielectric layer, the 3rd dielectric layer, floating gate dielectric layer, control gate dielectric layer and active area.
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| CN1601726A (en) * | 2003-09-28 | 2005-03-30 | 中芯国际集成电路制造(上海)有限公司 | Structure of vertical fast flasher and its mfg method |
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