KR20100080235A - Cmos image sensor and method of manufacturing the same - Google Patents

Cmos image sensor and method of manufacturing the same Download PDF

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Publication number
KR20100080235A
KR20100080235A KR1020080138882A KR20080138882A KR20100080235A KR 20100080235 A KR20100080235 A KR 20100080235A KR 1020080138882 A KR1020080138882 A KR 1020080138882A KR 20080138882 A KR20080138882 A KR 20080138882A KR 20100080235 A KR20100080235 A KR 20100080235A
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KR
South Korea
Prior art keywords
pmd
layer
pmd layer
metal
contact plug
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KR1020080138882A
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Korean (ko)
Inventor
정성훈
Original Assignee
주식회사 동부하이텍
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Priority to KR1020080138882A priority Critical patent/KR20100080235A/en
Publication of KR20100080235A publication Critical patent/KR20100080235A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A complementary metal-oxide-semiconductor image sensor and a method for manufacturing the same are provided to improve light receiving efficiency by reducing the thickness of pre-metal dielectric(PMD) layer including a metal wiring. CONSTITUTION: A first PMD layer(100) is formed on a semiconductor substrate(10). A first contact plug(200) passes through the first PMD layer and is electrically connected with a semiconductor element. A first metal wiring is formed on the first PMD layer. A second PMD layer(400) is formed on the first PMD layer. A second contact plug(500) passes through the first PMD layer and the second PMD layer and is electrically connected with the semiconductor element. A second metal wiring is formed on the second PMD layer.

Description

CMOS Image Sensor and Method of Manufacturing the same

An embodiment relates to a CMOS image sensor and a method of manufacturing the same.

A CMOS (Complementary Metal Oxide Silicon) image sensor is a semiconductor device that converts an optical signal into an electrical signal and has a unit pixel structure according to the number of transistors. In CMOS image sensors, metal lines transfer electrical signals to transistors to convert light received by a photodiode into electrons and turn them into signals.

In the CMOS image sensor, as the design rule is gradually reduced, the size of the unit pixel may be reduced to reduce light sensitivity. Accordingly, various techniques for improving light receiving efficiency are being studied.

By the way, since the metal wiring formed in the CMOS image sensor is usually composed of three layers, there is a problem that the metal wiring interferes with the optical path of the incident light to reduce the light receiving efficiency.

The embodiment provides a CMOS image sensor capable of simplifying metallization and reducing the thickness of the PMD layer including the metallization to improve light receiving efficiency, and a method of manufacturing the same.

In addition, the embodiment provides a CMOS image sensor and a method of manufacturing the same that can easily form a metal wiring and a PMD layer for improving light reception efficiency.

In an embodiment, the CMOS image sensor may include: a first PMD (Pre-Metal Dielectric) layer formed on a semiconductor substrate on which elements are formed; A first contact plug penetrating the first PMD layer and electrically connected to the device; A first metal wire connected to the first contact plug and formed on the first PMD; A second PMD layer formed on the first PMD layer on which the first metal wiring is formed; A second contact plug penetrating the first PMD layer and the second PMD layer and electrically connected to the device; A second metal wire connected to the second contact plug and formed on the second PMD; And an insulating film formed on the second PMD layer on which the second metal wiring is formed.

In another embodiment, a method of manufacturing a CMOS image sensor includes: forming a first PMD (Pre-Metal Dielectric) layer on a semiconductor substrate on which elements are formed; Planarizing the unevenness of the first PMD due to the device; Forming a first contact plug penetrating the first PMD layer and electrically connected to the device; Forming a first metal wiring connected to the first contact plug on the first PMD; Forming a second PMD layer on the first PMD layer on which the first metal wiring is formed; Forming a second metal film through the first PMD layer and the second PMD layer to form a second contact plug electrically connected to the device; Planarizing the second PMD layer by removing unevenness of the second metal film and the second PMD layer; And forming a second metal wiring connected to the second contact plug on the second PMD.

According to the CMOS image sensor and the method of manufacturing the same, the light receiving efficiency can be improved by simplifying the metal wiring and reducing the thickness of the PMD layer including the metal wiring.

In addition, according to the CMOS image sensor of the embodiment and a manufacturing method thereof, it is possible to easily form a metal wiring and a PMD layer for improving the light receiving efficiency.

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings. However, in describing the embodiments, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

In addition, in describing the embodiments, each layer (film), region, pattern, or structure may be “on” or “under” a substrate, each layer (film), region, pad, or pattern. In the case of being described as being formed "in," "on" and "under" include both "directly" or "indirectly" formed. . Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

1 to 10 are cross-sectional views of the manufacturing process of the CMOS image sensor of the embodiment.

As illustrated in FIG. 1, a first pre-metal dielectric (PMD) layer 100 is formed on a semiconductor substrate 10 on which elements for driving a CMOS image sensor are formed. In this embodiment, a case where the transistor 20 is formed on the semiconductor substrate 10 will be exemplified.

The first PMD layer 100 may be formed of an oxide film material such as EOS and BPSG.

When the first PMD layer 100 is formed, the unevenness 105 of the first PMD layer 100 is formed by the transistor 20 protruding from the semiconductor substrate 10.

As a result, a CMP process is performed to planarize the unevenness 105 of the first PMD layer 100 to planarize the first PMD layer 100 as shown in FIG. 2.

Next, as shown in FIG. 3, the first contact plug 200 is formed to penetrate the first PMD layer 100 and be connected to the transistor 20 such as a transistor formed on the semiconductor substrate 10. After the first metal film 205 is formed, as shown in FIG. 4, the first contact plug 200 may be formed by removing the first metal film 205.

In order to form the first contact plug 200, after forming a photoresist pattern (not shown) on the first PMD layer 100, an etching process using the photoresist pattern as an etching mask may be performed. A contact hole (not shown) for selectively exposing a floating diffusion region or a gate is formed. In addition, the first contact plug 200 may be formed by forming the first metal layer 205 so that a metal material such as tungsten (W) and titanium is filled in the contact hole.

On the inner surface of the contact hole in which the first contact plug 200 is embedded, it is possible to form a barrier layer using Al, Cu, Ta, Ti, W, Au, Ag, Al-based metal, or the like.

When the first contact plug 200 is formed, as shown in FIG. 5, the first metal wiring 300 connected to the first contact plug 200 is formed on the first PMD layer 100.

The first metal wire 300 may be formed of various conductive materials including metals, alloys, or silicides.

The first metal wire 300 is an auxiliary wire that serves as a common bridge among the entire wires, and may be formed to be relatively thinner than the main wire, for example, 1 to 500 kW thick.

The first metal wire 300 may be formed to deposit a metal layer on the first PMD layer 100 and to be connected to the first contact plug 200 by a photo and etching process, and the first metal wire 300 may be It may be connected to the transistor 20 through the first contact plug 200.

As such, this embodiment forms a thin auxiliary wiring that performs a simple connection function to simplify the configuration of the main wiring.

After the first metal wire 300 is formed, as shown in FIG. 6, the second PMD layer 400 is formed.

Since the second PMD layer 400 includes the first metal wiring 300, irregularities 405 due to the first metal wiring 300 are formed on an upper surface thereof. Thus, although it is possible to perform the CMP process to planarize the unevenness 405 of the second PMD layer 400, as shown in FIG. 7 for the convenience of the process, the second contact plug 500 is formed immediately. It is also possible.

Since the first metal wire 300 is formed to a thickness of 1 to 500 kPa, the unevenness 405 of the second PMD layer 400 may also be formed to a thickness of 1 to 500 kPa. In addition, due to the unevenness 405 of the second PMD layer 400, the unevenness 507 may be formed in the second metal film 505.

However, the second contact plug 500 is for connecting the transistor 20 of the semiconductor substrate 10 through the first PMD layer 100 and the second PMD layer 400, and the unevenness of the second PMD layer 400 is limited. 405 does not affect the formation of the second contact plug 500 at all. In addition, the first metal wire 300 is an auxiliary wire that performs a simple bridge function and does not need to be exposed to the upper surface portion.

As a result, the second contact plug 500 is immediately formed in the state where the unevenness 405 of the second PMD layer 400 is not planarized.

In order to form the second contact plug 500, after forming a photoresist pattern (not shown) on the second PMD layer 400, an etching process using the photoresist pattern as an etching mask may be performed. A contact hole (not shown) for selectively exposing a floating diffusion region or a gate is formed. In addition, the second contact plug 500 may be formed by forming the second metal layer 505 so that a metal material such as tungsten (W) and titanium is filled in the contact hole.

On the inner surface of the contact hole in which the second contact plug 500 is embedded, it is possible to form a barrier layer using Al, Cu, Ta, Ti, W, Au, Ag, Al-based metal, or the like.

Next, as shown in FIG. 8, the unevenness 405 of the second metal film 505 and the second PMD layer 400 is removed by a CMP process to be flattened to thereby form the first PMD layer 100 and the second PMD layer. The second contact plug 500 connected to the transistor 20 through the 400 is completed.

In general, when the second metal film 505 is removed through a CMP process, in order to effectively remove the second metal film 505, the upper surface of the PMD layer is also removed to a certain portion, for example, 1 to 300 kPa or more. do.

Therefore, in the embodiment, the second metal film 505 and the second PMD layer 400 are set by setting the removal height of the second PMD layer 400 to 1 to 500 kV in consideration of the unevenness 405 of the second PMD layer 400. The unevenness 405 may be removed to planarize the top surface of the second PMD layer 400.

Next, as shown in FIG. 9, a second metal wiring 600 connected to the second contact plug 500 is formed on the second PMD layer 400.

The second metal wire 600 may be formed of various conductive materials including metals, alloys, or silicides.

The second metal wire 600 is a main wire for performing important functions such as signal transmission and reception, and may be intentionally laid out so as not to block light incident to a photodiode (not shown).

The second metal wire 600 may be formed to deposit a metal layer on the second PMD layer 400 and to be connected to the second contact plug 500 by a photo and etching process, and the second metal wire 600 may be formed on the second PMD layer 400. The second contact plug 500 may be connected to the transistor 20.

After forming the second metal wiring 600, as shown in FIG. 10, an insulating layer 700 including the second metal wiring 600 may be formed.

The insulating layer 700 is an inter-metal dielectric layer (IMD) and may be formed of an oxide film or a nitride film. In addition, the insulating layer 700 including the second metal wiring 600 may be formed of a plurality of layers.

As described above, in this embodiment, by forming a thin auxiliary wiring that performs a simple connection function between the PMD layer, it is possible to simplify the configuration of the main wiring and to reduce the thickness of the PMD layer from 3500 kW to 2000 kW. Accordingly, it is possible to set the metal wiring so as not to block or interfere with the path of the incident light and improve the light transmittance of the image sensor by improving the light transmittance.

In addition, when the auxiliary wiring is formed between the PMD layers, the unevenness of the second PMD layer due to the auxiliary wiring is removed during the CMP process for forming the second contact plug. Thus, the process for the addition of the auxiliary wiring can be simplified.

Although described above with reference to the embodiment is only an example and is not intended to limit the invention, those of ordinary skill in the art to which the present invention does not exemplify the above within the scope not departing from the essential characteristics of this embodiment It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 10 are cross-sectional views of steps in manufacturing the semiconductor device of the embodiment.

Claims (10)

A first PMD (Pre-Metal Dielectric) layer formed on the semiconductor substrate on which the elements are formed; A first contact plug penetrating the first PMD layer and electrically connected to the device; A first metal wire connected to the first contact plug and formed on the first PMD; A second PMD layer formed on the first PMD layer on which the first metal wiring is formed; A second contact plug penetrating the first PMD layer and the second PMD layer and electrically connected to the device; A second metal wire connected to the second contact plug and formed on the second PMD; And an insulating film formed on the second PMD layer on which the second metal wiring is formed. The method of claim 1, The first metal wiring is, A CMOS image sensor formed as thinner than the second metal wiring as an auxiliary wiring to perform a simple connection function. The method of claim 2, The first metal wiring is CMOS image sensor is formed to a thickness of 1 ~ 500Å. The method of claim 1, The device is a CMOS image sensor comprising a transistor. Forming a first pre-metal dielectric (PMD) layer on the semiconductor substrate on which the devices are formed; Planarizing the unevenness of the first PMD due to the device; Forming a first contact plug penetrating the first PMD layer and electrically connected to the device; Forming a first metal wiring connected to the first contact plug on the first PMD; Forming a second PMD layer on the first PMD layer on which the first metal wiring is formed; Forming a second metal film through the first PMD layer and the second PMD layer to form a second contact plug electrically connected to the device; Planarizing the second PMD layer by removing unevenness of the second metal film and the second PMD layer; And forming a second metal wiring connected to the second contact plug on the second PMD. The method of claim 5, Forming a first contact plug penetrating the first PMD layer and electrically connected to the device, Etching the first PMD layer to form a contact hole connected to the device; Forming a first metal layer to fill the contact hole; Removing the first metal layer by a CMP process to planarize the first PMD layer. The method of claim 5, The first metal wiring is, A method for manufacturing a CMOS image sensor formed as thinner than the second metal wiring as an auxiliary wiring to perform a simple connection function. The method of claim 5, The first metal wiring is a manufacturing method of the CMOS image sensor is formed to a thickness of 1 ~ 500Å. The method of claim 8, The planarization of the second PMD layer by removing the unevenness of the second metal layer and the second PMD layer may include: And performing a CMP process by setting the removal height of the second PMD layer to a thickness of 1 to 500 mm. The method of claim 5, And forming an insulating film on the second PMD on which the second metal wiring is formed.
KR1020080138882A 2008-12-31 2008-12-31 Cmos image sensor and method of manufacturing the same KR20100080235A (en)

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