KR20100077593A - Method for manufacturign image sensor - Google Patents

Method for manufacturign image sensor Download PDF

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Publication number
KR20100077593A
KR20100077593A KR1020080135585A KR20080135585A KR20100077593A KR 20100077593 A KR20100077593 A KR 20100077593A KR 1020080135585 A KR1020080135585 A KR 1020080135585A KR 20080135585 A KR20080135585 A KR 20080135585A KR 20100077593 A KR20100077593 A KR 20100077593A
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KR
South Korea
Prior art keywords
silicon
bonding silicon
impurity
bonding
contact hole
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KR1020080135585A
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Korean (ko)
Inventor
김승현
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주식회사 동부하이텍
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Priority to KR1020080135585A priority Critical patent/KR20100077593A/en
Publication of KR20100077593A publication Critical patent/KR20100077593A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation

Abstract

PURPOSE: A method for manufacturing an image sensor is provided to prevent the deterioration of silicon performance by not etching silicon several times in a process of forming a plurality of impurity regions in bonding silicon or post-process. CONSTITUTION: Silicon is bonded on a substrate(100) with a metal wiring. The bonding silicon is formed on the substrate by bonding the silicon. A process of injecting impurities into the bonding silicon is performed several times. A contact hole to expose the part of a metal wiring is formed by etching the bonding silicon and the substrate. A thermal process is performed on the bonding silicon or substrate with the contact hole. A contact plug(130) connected to the metal wiring is formed in the contact hole.

Description

Method for manufacturing an image sensor {Method for manufacturign image sensor}

This embodiment discloses a method of manufacturing an image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS (Complementary Metal Oxide Silicon) image sensor.

The CMOS image sensor forms a photodiode and a MOS transistor in a unit pixel, and sequentially detects an electrical signal of each unit pixel in a switching manner to implement an image.

The conventional CMOS image sensor manufacturing process involves a chemical mechanical polishing process for forming a multilayer including a plurality of metal lines and an insulating layer after photodiode formation.

This causes a decrease in light sensitivity due to an increase in the distance from the photodiode to the color filter or the like and an increase in bad pixels due to an increase in defects.

The present embodiment is divided into a logic chip consisting of an image chip for forming a color filter array and a micro lens after forming a photodiode using two chips, a driver IC for driving the same, and a logic array for providing additional functions. Therefore, a method of manufacturing an image capable of three-dimensional integration of an image chip and a logic chip by using a single pad is proposed.

In addition, by eliminating a plurality of metal lines on the top of the photodiode, by reducing the distance between the photodiode and the micro lens, the optical path is dramatically reduced, thereby providing a method of manufacturing an image sensor that can improve the light sensitivity. .

In addition, a method of manufacturing an image sensor capable of alleviating or removing damage to a silicon substrate that may occur during silicon etching is proposed.

An image sensor according to the present embodiment comprises the steps of bonding silicon on a substrate on which metal wiring is formed; Bonding silicon is formed on the substrate by bonding the silicon, and performing a plurality of processes for implanting impurities into the bonding silicon; Etching the bonding silicon and the substrate to form contact holes exposed by portions of the metal wires; Performing a heat treatment process on the bonded silicon or the substrate on which the contact hole is formed; And forming a contact plug connected to the metal wire in the contact hole.

In addition, the manufacturing method of the image sensor of the embodiment comprises the steps of: bonding silicon on a substrate on which the first metal wiring is formed; Bonding silicon is formed on the substrate by bonding the silicon, and performing a plurality of processes for implanting impurities into the bonding silicon; Etching the bonding silicon and the substrate to form a first contact hole exposed by a portion of the first metal wire; Implanting impurities into the side of the bonding silicon exposed by the first contact hole; Performing a heat treatment process on the bonding silicon in which the first contact hole is formed; Forming a first contact plug connected to the first metal wire in the first contact hole; Forming an interlayer insulating layer on the bonding silicon and forming a second contact hole to etch the interlayer insulating layer to expose a portion of the bonding silicon; And forming a second contact plug connected to an upper surface of the bonding silicon in the second contact hole.

By the manufacturing method of the image sensor of the embodiment as proposed, the impurity region constituting the photodiode formed in the bonding silicon is proposed as a new structure, the plurality of silicon in the process of forming a plurality of impurity regions in the bonding silicon or subsequent processes Since etching is not performed, there is an advantage in preventing deterioration of silicon performance.

And, by reducing the damage that can be applied to the silicon during silicon etching, there is an advantage that can improve the device characteristics.

Hereinafter, with reference to the accompanying drawings for the present embodiment will be described in detail. However, the scope of the idea of the present invention may be determined from the matters disclosed by the present embodiment, and the idea of the invention of the present embodiment may be performed by adding, deleting, or modifying components to the proposed embodiment. It will be said to include variations.

In the following description, the word 'comprising' does not exclude the presence of other elements or steps than those listed. In addition, in the accompanying drawings, the thickness thereof is enlarged in order to clearly express various layers and regions. In addition, the same reference numerals are used for similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only being another part "on top" but also having another part in the middle.

1 is a view showing the configuration of an image sensor according to an embodiment of the present invention.

For reference, the description of the present invention will be described with reference to a part of the pixel region in which the photodiode is formed, and the logic region in which the lower wiring and the upper wiring are formed may be formed on one side of the pixel region, but specifically, It is not shown.

Referring to FIG. 1, the image sensor of the embodiment includes a substrate 100 having a first metal wiring 101, and the substrate in which a computing unit such as a transistor is configured by cleaving c-Si. Bonding to (100) forms a bonding silicon (120) on the substrate (100).

In addition, a photodiode for the first unit pixel and a photodiode for the second unit pixel are formed in the bonding silicon 120 on both sides of the first metal wire 101.

Adjacent unit pixels can be manufactured by the same fabrication process, and the description of the configuration for a single pixel will be described in detail by substituting the configuration for the other adjacent pixels shown.

A photodiode composed of a plurality of impurity regions is formed in the bonding silicon 120, and the photodiode includes a first impurity region in which impurities of a first conductivity type are implanted into a central region of the bonding silicon 120. 121, a second impurity region 122 having a first conductivity type impurity injected into one side of the first impurity region 121, and a second conductivity type impurity on the other side of the first impurity region 121. The implanted third impurity region 123 and a fourth impurity region 124 implanted with a second conductivity type impurity are disposed above the first impurity region 121.

The type of the conductive type injected into the impurity region may be variously applied depending on the embodiment whether electrons or holes are used as an electrical signal of the photodiode.

In the description of the embodiment of the present invention, a case in which electrons are used as a signal of a photodiode will be described. In this case, the first impurity region 121 is made of n-type impurities, and the second The impurity region 122 may be made of n + type impurity, the third impurity region 123 may be made of p0 type impurity, and the fourth impurity region 124 may be made of p + type impurity.

As a result, in the image sensor according to the present exemplary embodiment, the photodiode region formed in the bonding silicon may have the second impurity region 122 and the third impurity region 123 on one side and the other side based on the first impurity region 121. The fourth impurity region 124 is formed on the upper side of the first impurity region 121.

In particular, the first impurity region 121 and the third impurity region 123 form a PN junction in order to enable movement of electrons and holes due to depletion by pn junction when light is received. The second impurity region 122 and the fourth impurity region 124 form a PN junction.

In addition, a first contact plug 130 connected to the first metal wire 101 is formed in the bonding silicon 120, and the first contact plug 130 is formed of the bonding silicon 120 and the substrate. The first metal wire 101 is connected to the first metal wire 101 through 100.

In addition, photodiodes of adjacent unit pixels are formed around the first contact plug 130, and the second impurity regions 122 are formed in the bonding silicon of the region where the first contact plug 130 is formed. .

In addition, an interlayer insulating layer 160 for interlayer insulation is formed on the bonding silicon 120, and a second contact plug 170 for contact with the fourth impurity region 124 is formed in the interlayer insulating layer 160. ) Is formed.

In addition, a second metal wire 180 for electrical connection with the second contact plug 170 is formed on the second contact plug 170 and the interlayer insulating layer 160. Reverse bias is applied between the n + impurity region and the p + impurity region through the first contact plug 130 and the second contact plug 170.

Although not shown, a passivation layer may be further formed on the second metal wire 190, a color filter may be formed on the passivation layer, and light may be received on the color filter. Microlenses are formed.

When light is received by the microlens, electrons move to the n + region, and holes move to the p + region in the impurity regions in the bonding silicon 120. Therefore, the electrons moved to the second impurity region 122 are moved to the first metal wire 101 via the first contact plug 130.

In addition, the holes moved to the fourth impurity region 124 may move to the second metal wire 180 via the second contact plug 170.

Therefore, the plurality of impurity regions formed in the bonding silicon 120 are formed to be PN junctions, and a plurality of silicon etching processes do not have to be performed to form a photodiode in the bonding silicon 120. Defects may be prevented from occurring in the silicon by etching the silicon.

That is, the process of forming the photodiode is easy and the silicon etching can be minimized, thereby preventing the deterioration of the performance of the bonded silicon.

Hereinafter, a manufacturing method of an image sensor having the above structure will be described.

2 to 11 are views for explaining a manufacturing method of an image sensor according to an embodiment of the present invention.

First, referring to FIG. 2, the substrate 100 including the first metal wiring 101 is prepared, and c-Si is cleaved on the substrate 100 so that the computing unit is configured. Bonding to (100) to form a bonding silicon (120).

Next, referring to FIG. 3, a plurality of impurity implantation processes are performed in the bonding silicon 120 to form impurity regions that form a PN junction for separation and movement of electrons or holes during light reception.

In detail, an ion implantation mask (not shown) is formed in a region other than a position where the first impurity region 121 is to be formed in the bonding silicon 120, and then an n-type impurity is implanted as a first conductivity type impurity. Do this.

In this case, as shown, a first impurity region 121 made of n-type impurities is formed in the bonding silicon 120. The impurity implantation process for forming the first impurity region 121 is performed together with the first unit pixel 3A and the second unit pixel 3B adjacent to the first unit pixel, and the third impurity region ( An ion implantation mask is formed on 123, and then impurities of a first conductivity type are implanted into the bonding silicon 120.

After the first impurity region 121 is formed, an impurity implantation process for forming the second impurity region 122 in a region between the first impurity regions 121 is performed, and the second impurity region is performed. The impurity for forming the 122 is implanted with the same conductivity type impurity as the first impurity region.

That is, the second impurity region 122 is formed by implanting n + type impurities into one side of the first impurity region 121.

The second impurity region 122 may be performed after forming an ion implantation mask on the first and third impurity regions 121 and 123, and is formed by implanting n + type impurities. The second impurity region 122 is preferably positioned vertically upward with respect to the first metal wiring 101 formed in the substrate 100, and the first unit pixel 3A is formed by the second impurity region 122. ) And the second unit pixel 3B are formed.

Next, a third impurity region 123 is formed on the other side of the first impurity region 121 by implanting a second conductivity type impurity into the other side of the first impurity region 121. Accordingly, the second impurity region 122 and the third impurity region 123 are formed with the first impurity region 121 interposed therebetween.

In the impurity implantation process for forming the third impurity region 123, a process of implanting an impurity after forming an ion implantation mask in a region other than the third impurity region 123 may be performed. The third impurity region 123 is made of p0 type impurity, so that a PN junction is formed with the first impurity region 121.

Next, referring to FIG. 4, after the third impurity region 123 is formed, a process of injecting impurities into the entire surface of the bonding silicon 120 is further performed. The energy is smaller than the implantation energy when the first to third impurity regions 121, 122, and 123 are formed.

Therefore, the fourth impurity region 124 is formed around the surface of the bonding silicon 120. That is, the ion implantation process for forming the fourth impurity region 124 may use a p + type impurity, and the fourth impurity region 124 is formed on the upper side in the bonding silicon.

As a result, a fourth impurity region 124 for forming a PN junction with the first impurity region 121 is formed.

For the plurality of ion implantation steps, the first and second impurity regions made of the impurity of the first conductivity type are formed, followed by the formation of the third and fourth impurity regions made of the impurity of the second conductivity type. However, the impurity implantation process may form various impurity regions according to the amount of impurity and the amount of implantation energy thereof, and is not necessarily limited to the order of ion implantation as described above.

Next, referring to FIG. 5, a heat treatment process is performed on the plurality of impurity regions 121, 122, 123, and 124 formed in the bonding silicon 120. It is preferable that the heat treatment process be performed locally with respect to the bonding silicon 120, because the metal wiring is formed under the substrate 100.

The heat treatment process may use rapid thermal processing (RTP) or laser annealing, and the impurity regions in the bonding silicon 120 may be activated by the heat treatment process.

Next, referring to FIG. 6, a first interlayer insulating layer 140 is formed on the bonding silicon 120, and a portion of the first interlayer insulating layer 140 and the bonding silicon 120 is etched to form the first interlayer insulating layer 140. A portion of the metal wiring 101 is exposed.

That is, after depositing a first interlayer insulating film 140 on the bonding silicon 120, and then applying a photoresist pattern on the first interlayer insulating film 140, using the photoresist pattern as an etching mask The interlayer insulating layer 140, the bonding silicon 120, and the substrate 100 are etched to form the first contact hole 127.

By the etching process, a first contact hole 127 penetrating through the bonding silicon 120 is formed, and a portion of the first metal wire 101 is exposed.

The second impurity region 122 of the bonding silicon 120 is formed around the contact hole 127, which is an ion implantation process for forming the second impurity region 122. Because it has been performed with respect to the vertical upward direction.

In the process of etching the bonding silicon 120, damage may be applied to the second impurity region 122 located at both sides of the contact hole 127 and the bonding silicon adjacent thereto.

As a method for reducing or canceling damage that may be caused by etching of silicon, two embodiments may be performed.

That is, as illustrated in FIG. 7, a process of injecting P-type impurities into the contact hole 127 may be performed. In this case, the P-type impurity implantation may be inclined at a predetermined angle so that the P-type impurity may be effectively injected into the bonding silicon that is damaged on both sides of the contact hole 127.

After performing the P-type impurity implantation process, as shown in FIG. 8, an RTP or laser annealing process may be performed on the contact hole 127. The heat treatment process, such as the RTP or laser annealing process here may be performed for the diffusion of the implanted P-type impurities after performing the P-type impurity process as shown in FIG.

In another embodiment, damage may be alleviated by performing a heat treatment process such as RTP or laser annealing on the damaged bonded silicon without injecting P-type impurities as shown in FIG. 7.

Therefore, in the application of this embodiment, it may be appropriately used depending on the degree of damage to the bonding silicon.

Meanwhile, after mitigating or offsetting the damage that may occur due to etching of the bonding silicon, as shown in FIG. 9, a gap-filled metal such as tungsten is filled in the first contact hole 127. Then, the planarization process is performed to form a first contact plug 130 filling the first contact hole 127.

The first contact plug 130 may be a path through which electrons generated during application and reception of a reverse bias move to the first metal wire 101. For this purpose, the first contact plug 130 may include the first contact plug 130. It is connected to the metal wiring 101.

Next, referring to FIG. 10, an insulating film is deposited on the bonding silicon 120 to form a second interlayer insulating film 160.

Here, after the first contact plug 130 is formed in the above step, an etching process for removing the first interlayer insulating layer 140 may be further performed, and the first interlayer insulating layer 140 may be further removed. The second interlayer insulating layer 160 may be formed while being formed.

Although the first interlayer insulating layer 140 is not illustrated in FIGS. 9 and 10, the second interlayer insulating layer 160 may be formed on the first interlayer insulating layer, according to an exemplary embodiment.

Meanwhile, after the photoresist is applied and patterned on the second interlayer insulating layer 160, the second interlayer insulating layer 180 is etched to form a second contact hole 161 for forming the second contact plug 170. do.

Next, referring to FIG. 11, a second contact plug 170 is formed in the second contact hole 161. The process for forming the second contact plug 170 may also be performed by a known gap fill method and a planarization method.

In particular, the second contact plug 170 is formed to be connected to the fourth impurity region 124 in the photodiode region of the bonding silicon 120. This is to apply a reverse bias to the photodiode so that the hole generated when receiving the light is moved.

In addition, a second metal wire 180 to be electrically connected to the second contact plug 170 is formed on the second interlayer insulating layer 160. Regarding the formation of the second metal wire 180, various well-known techniques may be applied and thus a detailed description thereof will be omitted.

Although not shown, a process for forming a protective film may be further performed on the second metal wire 180, and a process of forming a color filter layer on the protective film, and applying a photoresist on the color filter layer to form a micro The process of forming the stove is further performed.

By this process, the image sensor according to the embodiment of the present invention is manufactured in the form as shown in FIG.

By the image sensor of the embodiment and a method of manufacturing the same, the impurity region constituting the photodiode formed in the bonding silicon is proposed as a new structure, and in the process of forming a plurality of impurity regions in the bonding silicon or subsequent processes, Since etching is not performed a plurality of times, there is an advantage of preventing deterioration of silicon performance.

In addition, there is an advantage in that the characteristics of the image sensor may be prevented from being lowered due to damage that may occur during etching of the bonding silicon.

1 is a view showing the configuration of an image sensor according to an embodiment of the present invention.

2 to 11 are views for explaining a manufacturing method of an image sensor according to an embodiment of the present invention.

Claims (9)

Bonding silicon onto the substrate on which the metal wiring is formed; Bonding silicon is formed on the substrate by bonding the silicon, and performing a plurality of processes for implanting impurities into the bonding silicon; Etching the bonding silicon and the substrate to form contact holes exposed by portions of the metal wires; Performing a heat treatment process on the bonded silicon or the substrate on which the contact hole is formed; And And forming a contact plug connected to the metal wire in the contact hole. The method of claim 1, Performing the heat treatment process, A method of manufacturing an image sensor performing an RTP or laser annealing process on the contact hole. The method of claim 1, Prior to performing the heat treatment, the method of manufacturing an image sensor further comprises the step of injecting impurities into the contact hole. The method of claim 3, wherein The implanting of the impurity into the contact hole, the manufacturing method of the image sensor for implanting the P-type impurities. Bonding silicon onto the substrate on which the first metal wiring is formed; Bonding silicon is formed on the substrate by bonding the silicon, and performing a plurality of processes for implanting impurities into the bonding silicon; Etching the bonding silicon and the substrate to form a first contact hole exposed by a portion of the first metal wire; Implanting impurities into the side of the bonding silicon exposed by the first contact hole; Performing a heat treatment process on the bonding silicon in which the first contact hole is formed; Forming a first contact plug connected to the first metal wire in the first contact hole; Forming an interlayer insulating layer on the bonding silicon and forming a second contact hole to etch the interlayer insulating layer to expose a portion of the bonding silicon; And And forming a second contact plug connected to an upper surface of the bonding silicon in the second contact hole. The method of claim 5, And implanting impurities into the side surfaces of the bonding silicon exposed by the first contact hole, and implanting P-type impurities at a predetermined inclination angle. The method of claim 5, The step of injecting a ball impurities into the bonding silicon may include forming a first impurity region using impurities of a first conductivity type, and forming a first impurity region on one side of the first impurity region using impurities of the first conductivity type. Forming a second impurity region, forming a third impurity region on the other side of the first impurity region using a second conductivity type impurity, and using the second conductivity type impurity And forming a fourth impurity region on the image sensor. The method of claim 7, wherein The impurity of the first conductivity type is an N-type impurity, and the impurity of the second conductivity type is a P-type impurity. The method of claim 7, wherein The forming of the first contact plug may include performing the first contact plug through the second impurity region of the bonding silicon.
KR1020080135585A 2008-12-29 2008-12-29 Method for manufacturign image sensor KR20100077593A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101270859B1 (en) * 2012-09-18 2013-06-10 (재) 전북테크노파크 Precision alignment method and apparatus for cmos image sensors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101270859B1 (en) * 2012-09-18 2013-06-10 (재) 전북테크노파크 Precision alignment method and apparatus for cmos image sensors

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