KR20100079281A - Grid calibration method for semiconductor mask pattern - Google Patents

Abstract

PURPOSE: A method for calibrating a grid of a mask pattern for a semiconductor is provided to improve the accuracy of a pattern by calibrating pattern with off grid to on grid through partial sizing. CONSTITUTION: Mask patterns on the same mask are classified into a plurality of design group according to the position of mask patterns(S2). The patterns in a specific design group applied with a fine design rule are partially sized among the classified design groups(S6). Different grid arrangements are formed between the mask patterns in the specific design group and the mask patterns in the adjacent design group(S8).

Description

Grid calibration method for semiconductor mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grid correction method for a mask pattern for semiconductors, and more particularly, to maintain a constant gap between mask patterns for semiconductors and to prevent off grid phenomenon caused by grid spacing. A grid correction method for a mask pattern for semiconductors capable of improving resolution and precision.

Semiconductor photolithography technology allows for precise control of the mask design, allowing the amount of light projected onto the mask to be properly controlled. In particular, such technologies include the development of new photosensitizers, the development of scanners equipped with high numerical aperture lenses, and the development of modified mask technology to overcome the technical limitations of manufacturing devices.

In addition, the optical proximity correction technology has helped to overcome the technical limitations of the conventional optical exposure manufacturing apparatus, and contributes to the cost reduction of the DRAM development as well as the foundry market. It provided the crucial motivation to accelerate competition.

Products with non-repetitive and irregular pattern geometries, such as logic devices, have overcome the optical resolution limits and at the same time enable very fine patterning in a short time. This effectively overcomes the optical distortion phenomenon while improving the processing ability of the ultra fine pattern, it is possible to compensate for the distortion of light contained in the optical exposure apparatus.

Recently, the development of a chemically amplified resist having excellent photosensitivity to light of far ultraviolet wavelength (248 nm or 194 nm Wavelength) has emerged a practical technology that can further increase the resolution. In particular, the optical proximity compensation technique was published by John L. Nistler et al., "Large area optical design rule checker for Logic PSM application", SPIE Vol. 2254 Photomask and X-Ray Mask Technology (1994), Has been verified.

In particular, a factor influencing the resolution of the pattern is the optimization of the pattern suitable for the exposure apparatus. In realizing this pattern optimization, the precision of the design drawing is very important, which is closely related to the volume of the design data.

1 is a layout diagram illustrating a mask pattern including a pattern shifted by a conventional off grid, and FIG. 2 is a view illustrating a photosensitive pattern appearing on a wafer when exposure is performed using the mask pattern of FIG. 1. The layout diagram shown.

Referring to FIG. 1, among the mask patterns 2, 3, 4 and 5 formed on the semiconductor mask 1, the mask patterns 3 and 4 below the grid 6 and 7, which are the minimum scales at the time of design, are When present, mask patterns 3 and 4 transitioned by off-grid are present in addition to mask patterns 2 and 5 that are normally aligned.

Here, if the address size of the off-grid mask (E-beam writer) for fabricating the mask (1) does not match an integer multiple of the grid (6,7) on the semiconductor circuit design DB, the original The mask pattern edge surface 8 is not located on the intended grid 6, 7 and a portion of the mask pattern 3, 4 is strung on the grid 6, 7 or a gap as shown in FIG. 1. ) Is formed and transition of the mask patterns 3 and 4 occurs.

Referring to FIG. 2, when the photosensitive patterns 12, 13, 14, and 15 are formed on the wafer 10 using the mask 1 designed according to FIG. 1, the mask patterns 2 and 5 normally aligned. Normal photosensitive patterns 12 and 15 are obtained from the photoresist pattern. However, gaps are generated between the off-grid mask patterns 3 and 4 by the gap between the normal grid 7a and the photosensitive pattern edge surface 18. Patterns 13 and 14 are obtained.

This off grid phenomenon causes problems such as poor contact covering, miss alignment due to partial loss of the pattern, and thus, there is a problem in that the fidelity of the pattern is degraded.

The present invention has been made to solve the above problems, the mask pattern for the semiconductor to improve the pattern resolution by improving the pattern fidelity by correcting the mask pattern generated off-grid phenomenon to the on-grid state to improve the pattern fidelity Its purpose is to provide a grid correction method.

The grid correction method of the mask pattern for a semiconductor of the present invention for realizing the above object comprises: a first step of classifying mask patterns existing on the same mask into a plurality of design groups for each position; and the classified plurality of Performing a selective sizing of patterns in a specific design group to which a fine design rule is applied among the design groups, and forming a different grid arrangement between mask patterns in the specific design group and mask patterns in an adjacent design group It characterized in that it comprises a step.

In the second step, when the edge surface of the outermost mask pattern among the mask patterns included in the specific design group is formed outside the grid, the reduction surface sizing is performed so that the edge surface of the outermost mask pattern matches the grid. If the edge surface of the mask pattern located at the outermost side of the mask patterns included in the specific design group is formed inside the grid, the enlarged sizing is performed so that the edge surface of the outermost mask pattern matches the grid. do.

In the case of the reduced sizing, it is made in the range of 70% or more and less than 100% of the original pattern, and in the case of the enlarged sizing, it is made in the range of more than 100% and less than 140% of the original pattern.

Between the first step and the second step is a step of expanding the mask pattern of the entire design group in the range of 150 ~ 200% of the original pattern, and after the second step sized design group and other design groups It characterized in that it further comprises the step of reducing the mask pattern of the entire design group including the same ratio.

According to the grid correction method of a mask pattern for a semiconductor according to the present invention, the resolution of the pattern by improving the pattern fidelity by correcting to the on-grid state by performing a partial sizing for the pattern generated off-grid phenomenon in the pattern generation process And there is an advantage to improve the precision.

Hereinafter, the configuration and operation of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, the same reference numerals will be used for the same components as the prior art.

3A to 3C are layout views of mask patterns showing the steps of the grid correction method for semiconductor mask patterns according to the present invention, and FIG. 4 is a process flow chart showing the steps of the grid correction method for semiconductor mask patterns according to the present invention. .

First, as shown in FIG. 3A, the first and second design groups 20 and 30 are classified according to the positions of the mask patterns 21, 22, 31, and 32 (S 2).

Here, the first design group 20 is a relatively less finely designed region (Non-Critical design group), for example, a region designed in a grid of at least 5 nm, the second design group 30 is a layout In the smallest area (critical design group) is designed to the smallest line width in, for example, a region designed in a grid of at least 1 nm unit, such as a transistor.

In this case, the mask patterns 21, 22, 31, and 32 are drawn by 150% to 200% enlarged than the original patterns 2, 3, 4, and 5 shown in FIG.

The reason why the mask patterns 21, 22, 31, and 32 are enlarged in advance is to adjust various line widths as will be described later.

Next, selective sizing is performed on the mask patterns 31 and 32 in the second design group 30 which are minute regions (S6).

Although FIG. 3B illustrates an example in which enlarged sizing is performed on the mask patterns 31 and 32 included in the second design group 30, reduction sizing is performed in some cases.

When there are a plurality of mask patterns 31 and 32 included in the second design group 30, which are specified as minute regions, the reduction sizing is best when the edge surface of the outermost mask pattern is formed outside of the grid. The edge of the outer mask pattern is corrected to match the grid, and the enlarged sizing is to correct the edge of the outermost mask pattern to match the grid when the edge of the outermost mask pattern is formed inside the grid. It is for.

In the case of reduced sizing, the range is set to 70% or more and less than 100% of the original pattern (31,32). desirable.

By performing such selective sizing, the sized mask patterns 31a and 32a in the second design group 30 have a different grid arrangement than the mask patterns 21 and 22 in the adjacent first design group 20 ( S 8).

In this case, the different grid arrangement between the first design group 20 and the second design group 30 may be assigned an additional address in the E-beam writer, or may be a data type of the layer separately. It is possible by setting.

Next, as illustrated in FIG. 3C, shrinking is performed at the same ratio with respect to the entire mask patterns 21, 22, 31a, and 32a included in the first design group 20 and the second design group 30. (S10), the final mask patterns 21b, 22b, 31b, and 32b are formed (S12).

Here, the reduction ratios for the entire mask patterns 21, 22, 31a and 32a need not be set at the same ratio as in the expansion step S4, and various line widths can be designed according to the reduction ratios.

Through the above steps, the grid patterns 21b, 22b, 31b, and 32b, which are finally completed, can be kept separate from each other, thereby minimizing off-grid problems, and varying line widths by performing selective sizing at various ratios. Can be implemented precisely.

It is apparent to those skilled in the art that the present invention is not limited to the above embodiments and can be practiced in various ways without departing from the technical spirit of the present invention. will be.

1 is a layout diagram illustrating a mask pattern including a pattern shifted by a conventional off grid;

FIG. 2 is a layout diagram illustrating a photosensitive pattern appearing on a wafer when exposure is performed using the mask pattern of FIG. 1.

3A to 3C are layout views of mask patterns showing steps of a grid correction method for a mask pattern for a semiconductor according to the present invention;

4 is a process flowchart showing steps of a grid correction method for a mask pattern for a semiconductor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: mask 2,3,4,5: mask pattern

6,7: Grid 8: Pattern Edge Ground

10 wafer 12,13,14,15 photosensitive pattern

18: photosensitive pattern edge 20: first design group

30: second design group 21, 22, 31, 32: enlarged mask pattern

31a, 32a: sized mask pattern 21b, 22b, 31b, 32b: reduced mask pattern

Claims (4)

A first step of classifying mask patterns existing on the same mask into a plurality of design groups by positions; and Selective sizing of patterns in a specific design group to which a fine design rule is applied among the classified plurality of design groups is performed to generate a different grid arrangement between mask patterns in the specific design group and mask patterns in an adjacent design group. The second step of forming to have; grid correction method of a mask pattern for a semiconductor comprising a. The method of claim 1, In the second step, when the edge surface of the outermost mask pattern among the mask patterns included in the specific design group is formed outside the grid, the reduction surface sizing is performed so that the edge surface of the outermost mask pattern matches the grid. If the edge surface of the mask pattern located at the outermost side of the mask patterns included in the specific design group is formed inside the grid, the enlarged sizing is performed so that the edge surface of the outermost mask pattern matches the grid. The grid correction method of the mask pattern for semiconductors. The method of claim 2, The reduction sizing is in the range of 70% or more and less than 100% of the original pattern, the enlarged sizing is in the range of more than 100% and less than 140% of the original pattern grid correction method of the semiconductor pattern . The method of claim 1, Between the first step and the second step is a step of expanding the mask pattern of the entire design group in the range of 150 ~ 200% of the original pattern, and after the second step sized design group and other design groups The grid pattern correction method of a mask pattern for a semiconductor, characterized in that further comprising the step of reducing the mask pattern of the entire design group including the same.

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