KR20100079173A - Pad for package of semiconductor device and fabrication method thereof - Google Patents

Pad for package of semiconductor device and fabrication method thereof Download PDF

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Publication number
KR20100079173A
KR20100079173A KR1020080137589A KR20080137589A KR20100079173A KR 20100079173 A KR20100079173 A KR 20100079173A KR 1020080137589 A KR1020080137589 A KR 1020080137589A KR 20080137589 A KR20080137589 A KR 20080137589A KR 20100079173 A KR20100079173 A KR 20100079173A
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KR
South Korea
Prior art keywords
metal
support
interlayer insulating
metals
contacts
Prior art date
Application number
KR1020080137589A
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Korean (ko)
Inventor
신용욱
Original Assignee
주식회사 동부하이텍
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Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080137589A priority Critical patent/KR20100079173A/en
Publication of KR20100079173A publication Critical patent/KR20100079173A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A pad for a semiconductor device package and a manufacturing method thereof are provided to prevent lifting phenomenon between a metal and an insulation oxide layer by physically connecting a second metal to a semiconductor substrate with a support structure. CONSTITUTION: A plurality of first metals(412) are connected to a substrate through a plurality of first contacts(408) formed inside a first interlayer insulation layer(406) which buries a metal wiring(404) and a field oxide layer. A second metal(418) is formed on a second interlayer metal insulation layer which fills a plurality of first metals. A third metal(424) is connected to the second metal through a plurality of second contacts formed inside the third interlayer insulation layer formed on the second metal.

Description

Pad for semiconductor device package and manufacturing method therefor {PAD FOR PACKAGE OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF}

The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to a structure of a pad suitable for packaging a semiconductor device in a circuit upder pad (CUP) method and a manufacturing method thereof.

As is well known, a semiconductor package provides a function of protecting a semiconductor chip from an external environment and a function of allowing a semiconductor chip to be electrically connected to a printed circuit board smoothly, which requires a pad for a package.

1 is a plan view of a conventional pad for a semiconductor device package, Figure 2 is a cross-sectional view of a conventional pad for a semiconductor device package cut along the line AA 'of FIG.

Referring to FIG. 2, a metal interlayer 204 is formed on a semiconductor substrate 202 having a logic circuit, a field oxide film, etc. formed therein, and a first interlayer insulating layer 206 formed in a form of filling the metal interconnect 204. A plurality of first contacts 208 are formed therein. Here, the metal wiring 204 can be, for example, a gate or the like.

In addition, a first metal 210 is formed on each first contact 208, and the first metal 210 is buried in the second interlayer insulating film 212, and the second metal is buried in the second interlayer insulating film 212. Metal 214 is formed.

Next, a plurality of second contacts 218 are formed in the third interlayer insulating film 216 formed on the second metal 214, respectively, which are connected to the third metal 214, respectively. 3 metal 220 is formed.

That is, the pad is conventionally formed using the upper 2-3th metal and the insulating oxide film (interlayer insulating film).

As is well known, as the integration of various functions into a single chip is progressing, it is a general trend that the thickness of the metal at the top of the pad gradually becomes thinner.

However, the above-described conventional pad structure using the upper 2-3rd metal and the insulating oxide film, the uppermost metal is not supported when the package is bonded, so that the bonded metal is held or raised for high integration. There is a problem in that the metal of the formed thin film (falling phenomenon between the metal and the insulating oxide film) occurs, which is a factor that reduces the reliability of the semiconductor device.

According to an aspect of the present disclosure, a plurality of first metals connected to the semiconductor substrate through a plurality of first contacts formed in a first interlayer insulating layer filling a metal wiring and a field oxide film formed on the semiconductor substrate may be provided. A plurality of second metals formed on the second interlayer insulating layer filling the first metal of the first metal; and a plurality of second metals formed on the first and second interlayer insulating layers to physically connect an upper portion of the field oxide layer and a lower portion of the second metal layer. A pad for a semiconductor device package includes a support structure and a third metal connected to the second metal through a plurality of second contacts formed in a third interlayer insulating layer formed on the second metal.

According to another aspect of the present invention, there is provided a process of forming a metal wiring and a plurality of first supporting metals on a semiconductor substrate, forming a first interlayer insulating film thereon, and a plurality of connected to the semiconductor substrate in the interlayer insulating film. Forming a plurality of first support contacts connected to a first contact and the plurality of first support metals, forming a plurality of first metals on the plurality of first contacts, and forming the plurality of first support contacts Forming a plurality of second support metals on the surface; forming a second interlayer insulating film on the plurality of first metals and the plurality of second support metals; and the plurality of second interlayers in the second interlayer insulating film. Forming a plurality of second support contacts respectively connected to the support metal, and forming a second metal connected to the plurality of second support contacts on the second interlayer insulating film, and thereafter, forming a third interlayer insulation thereon. A method of manufacturing a pad for a semiconductor device package includes forming a film, and forming a third metal connected to the second metal through a plurality of second contacts on the third interlayer insulating film.

The present invention can prevent the lifting phenomenon between the metal and the insulating oxide film by forming a supporting structure of the support metal and the support contact on the field oxide film that insulates the elements to physically connect the second metal and the semiconductor substrate. As a result, the reliability of the semiconductor device may be improved.

The technical gist of the present invention is different from the above-described conventional method of forming a pad by using the upper 2-3th metal and an insulating oxide film (interlayer insulating film), and a supporting metal on the field oxide film insulating the elements (transistors). By forming a support structure made of a support contact to physically connect the second metal and the semiconductor substrate, the present invention can effectively solve the problems in the conventional manner through such technical means.

Here, the field oxide film on which the support metal is formed may be, for example, a shallow trench isolation film (STI) that insulates between devices (transistors, etc.).

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a plan view of a pad for a semiconductor device package according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a pad for a semiconductor device package according to an embodiment of the present invention cut along the line BB ′ of FIG. 3.

Referring to FIG. 4, a field oxide film 402a, a metal wiring 404, and a first support metal 404a are respectively formed on a semiconductor substrate 402 having a logic circuit or the like formed therein, and a buried first layer is formed. An interlayer insulating film 406 is formed.

Here, the field oxide film 402a may be, for example, a shallow trench isolation film STI, and the first support metal 404a may be simultaneously formed in the process of forming the metal wiring 404.

In addition, a plurality of first metals 412 and a plurality of second support metals 412a are formed on the first interlayer insulating layer 406, and the plurality of first metals 412 may include a plurality of first contacts 408. A plurality of second support metals 412a are respectively connected to respective corresponding first support metals 404a through a plurality of first support contacts 408a. do.

A second interlayer insulating film 414 is formed to fill a plurality of first metals 412 and a plurality of second supporting metals 412a, and a plurality of second supports are formed in the second interlayer insulating film 414. A plurality of second contacts 416a are respectively connected to the metal 412a.

Next, a second metal 418 is formed on the second interlayer insulating film 414 having a plurality of second support contacts 416a formed therein, and a plurality of second contacts 422 formed thereon. A third interlayer insulating film 420 is formed, and a third metal 424 connected to the second metal 418 through a plurality of second contacts 422 is formed on the third interlayer insulating film 420. Here, the third metal 424 may be formed in a tubular pattern unlike the first and second metals 412 and 418 having a narrow bar shape.

That is, in the pad structure for a semiconductor device package of the present invention, a plurality of support structures for physically connecting a semiconductor substrate (field oxide film) and a second metal are formed. Each of the support structures includes a first support metal 404a to a first. The support contact 408a-the second support metal 412a-the second support contact 416a.

Next, a series of processes for manufacturing the pad structure for a semiconductor device package of the present invention having the structure as described above will be described.

5A through 5G are flowcharts illustrating main processes of manufacturing a pad for a semiconductor device package according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, a metal wiring 404 and a plurality of first supporting metals are formed on a semiconductor substrate 402 having a field oxide film 402a formed therein by sequentially performing a deposition process and a selective etching process of a metal material. A plurality of first supporting metals 404a may be simultaneously formed on the field oxide film 402a during the formation process of the metal wiring 404, and the field oxide film 402a may be formed, for example, by shading. A low trench isolation film (STI).

Next, a first interlayer insulating film 406 of a thick film is formed on the entire surface of the semiconductor substrate 402 on which the metal wiring 404 and the plurality of first supporting metals 404a are formed by sequentially performing a deposition process, a planarization process, and the like. And a plurality of first contact holes and a plurality of first supports exposing an upper portion of the semiconductor substrate 402 by selectively removing a portion of the first interlayer insulating layer 406 through an etching process using a mask pattern (not shown). By forming a plurality of first support contact holes that expose the upper portion of the metal 404a, and performing a deposition process and an etching process of a metal material, for example, as shown in FIG. 5B, the plurality of first contacts A plurality of first contacts 408 and a plurality of first support contacts 408a are respectively formed in the first interlayer insulating film 406, in which holes are filled with a metal material and a plurality of first support contact holes are filled with a metal material. do.

Subsequently, by performing a deposition process and selective etching of a metal material, as shown in FIG. 5C as an example, respectively corresponding to the plurality of first contacts 408 and the plurality of first support contacts 408a, respectively. A plurality of first metals 412 and a plurality of first supporting metals 412a are formed, respectively.

The second interlayer insulating film 414 of the thick film is formed on the entire surface of the semiconductor substrate 402 on which the plurality of first metals 412 and the plurality of first supporting metals 412a are formed. And a plurality of second support contacts each exposing top portions of the plurality of second support metals 412a by selectively removing a portion of the second interlayer insulating film 414 through an etching process using a mask pattern (not shown). By forming a hole and performing a deposition process, an etching process, or the like of a metal material, as shown in FIG. 5D, for example, a plurality of second support contacts in which a plurality of second support contact holes are filled with a metal material ( 416a are formed in the second interlayer insulating film 414, respectively.

Next, by sequentially performing a deposition process and a selective etching process of a metal material, as shown in FIG. 5E as an example, through a plurality of second support contacts 416a on the second interlayer insulating film 414. A second metal 418 is physically connected to the plurality of second support metals 412a.

Subsequently, a deposition process, a planarization process, and the like are sequentially performed to form a third interlayer insulating film 420 of a thick film on the entire surface of the semiconductor substrate 402 on which the second metal 418 is formed, and etching using a mask pattern (not shown). By selectively removing a portion of the third interlayer insulating film 420 through the process to form a plurality of second contact holes exposing the upper portion of the second metal 418, and performing a deposition process and an etching process of a metal material For example, as illustrated in FIG. 5F, a plurality of second contacts 422 having a plurality of second contact holes filled with a metal material are formed in the third interlayer insulating layer 420, respectively.

Finally, by performing a deposition process of a metal material such as sputtering or the like, as shown in FIG. 5G, the second metal (eg, through a plurality of second contacts 422 on the third interlayer insulating film 420) may be formed. A third metal 424 is physically connected to 418.

In the above description, the present invention has been presented and described with reference to preferred embodiments. However, the present invention is not necessarily limited thereto, and a person having ordinary skill in the art to which the present invention pertains can make various modifications without departing from the technical spirit of the present invention. It will be readily appreciated that branch substitutions, modifications and variations are possible.

1 is a plan view of a pad for a conventional semiconductor device package,

2 is a cross-sectional view of a conventional pad for a semiconductor device package;

3 is a plan view of a pad for a semiconductor device package according to an embodiment of the present invention;

4 is a cross-sectional view of a pad for a semiconductor device package according to an embodiment of the present invention;

Figures 5a to 5g is a process flow diagram showing the main process for manufacturing a pad for a semiconductor device package according to an embodiment of the present invention.

Description of the Related Art

402: semiconductor substrate 402a: field oxide film

404: metal wiring 404a: first supporting metal

406: first interlayer insulating film 408: first contact

408a: first support contact 412: first metal

412a: second support metal 414: second interlayer insulating film

416a: second support contact 418: second metal

420: Third interlayer insulating film 422: Second contact

424: third metal

Claims (8)

A plurality of first metals connected to the semiconductor substrate through a plurality of first contacts formed in the first interlayer insulating layer filling the metal wiring and the field oxide film formed on the semiconductor substrate; A second metal formed on the second interlayer insulating film to fill the plurality of first metals; A plurality of support structures formed in the first and second interlayer insulating films to physically connect an upper portion of the field oxide layer and a lower portion of the second metal; A third metal connected to the second metal through a plurality of second contacts formed in a third interlayer insulating layer formed on the second metal Pad for semiconductor device package comprising a. The method of claim 1, Each of the plurality of support structures, A first support metal formed on the field oxide film; A first support contact formed in the first interlayer insulating film and connected to the first support metal; A second support metal formed on the first support contact; A second support contact formed in the second interlayer insulating film and connected to the second support metal Pad for a semiconductor device package comprising a. The method of claim 2, The field oxide film is STI, characterized in that the pad for a semiconductor device package. 4. The method according to any one of claims 1 to 3, The third metal is a pad for a semiconductor device package, characterized in that formed in a cylindrical pattern. Forming a metal wiring and a plurality of first supporting metals on the semiconductor substrate, and forming a first interlayer insulating film thereon; Forming a plurality of first contacts connected to the semiconductor substrate and a plurality of first support contacts connected to the plurality of first support metals in the interlayer insulating film; Forming a plurality of first metals on the plurality of first contacts, and forming a plurality of second support metals on the plurality of first support contacts; Forming a second interlayer insulating film on the plurality of first metals and the plurality of second supporting metals; Forming a plurality of second support contacts respectively connected to the plurality of second support metals in the second interlayer insulating film; Forming a second metal layer on the second interlayer insulating layer, the second metal being connected to the plurality of second supporting contacts, and then forming a third interlayer insulating layer thereon; Forming a third metal connected to the second metal through a plurality of second contacts on the third interlayer insulating film Method for manufacturing a pad for a semiconductor device package comprising a. The method of claim 5, The first supporting metal is formed at the same time as the metal wiring, the manufacturing method of the pad for a semiconductor device package. The method of claim 5, The said field oxide film is STI, The manufacturing method of the pad for semiconductor element packages characterized by the above-mentioned. The method according to any one of claims 5 to 7, The third metal wiring is formed in a tubular pattern, characterized in that the pad for a semiconductor device package.
KR1020080137589A 2008-12-30 2008-12-30 Pad for package of semiconductor device and fabrication method thereof KR20100079173A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206506A (en) * 2016-08-08 2016-12-07 武汉华星光电技术有限公司 The preparation method of display device, terminal and terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206506A (en) * 2016-08-08 2016-12-07 武汉华星光电技术有限公司 The preparation method of display device, terminal and terminal

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