KR20100078716A - Method for forming micropattern in semiconductor device - Google Patents

Method for forming micropattern in semiconductor device Download PDF

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Publication number
KR20100078716A
KR20100078716A KR1020080137058A KR20080137058A KR20100078716A KR 20100078716 A KR20100078716 A KR 20100078716A KR 1020080137058 A KR1020080137058 A KR 1020080137058A KR 20080137058 A KR20080137058 A KR 20080137058A KR 20100078716 A KR20100078716 A KR 20100078716A
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KR
South Korea
Prior art keywords
hard mask
pattern
forming
etching
layer
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KR1020080137058A
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Korean (ko)
Inventor
정태우
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주식회사 하이닉스반도체
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Priority to KR1020080137058A priority Critical patent/KR20100078716A/en
Publication of KR20100078716A publication Critical patent/KR20100078716A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

The present invention is to provide a method for forming a micropattern of a semiconductor device that can reduce the manufacturing cost by simplifying the manufacturing process, for this purpose, the present invention comprises a first hard on a substrate including a cell region and a pad region, the etching layer is formed Forming a mask, an etch wall layer, and a second hard mask made of the same material as the first hard mask, and etching the second hard mask of the cell region using a first photoresist pattern to form a second hard mask pattern. Forming a spacer; forming a spacer on both sidewalls of the second hard mask pattern; forming a third hard mask made of the same material as the first hard mask to cover the spacer; The third hard mask, the second hard mask pattern, and the etch field using the second photoresist pattern formed on the spacer layer and the spacer of the cell region as an etch mask. It provides a fine pattern formation method of a semiconductor device including the step of sequentially etching the in-situ (in-situ) - layer, the first hard mask and of the etching layer.

Description

METHOD FOR FORMING MICROPATTERN IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to peninsula manufacturing technology, and more particularly, to a method of forming a fine pattern of a semiconductor device.

Recently, as semiconductor devices have been highly integrated, lines and spaces of 40 nm or less (hereinafter, referred to as LS) are required. However, it is very difficult to form 'LS' of 60 nm or less due to the limitations of the exposure equipment currently developed and commercialized.

Accordingly, in order to realize fine 'LS' of 60 nm or less while using commercially available exposure equipment as it is, a double patterning technology (DPT) and a spacer patterning technology (hereinafter referred to as SPT) processes are performed. Proposed.

1A to 1H are cross-sectional views illustrating a process of the SPT according to the prior art. 1A to 1H, 'A' is a cell region in which a cell is to be formed, and 'B' is a region showing a part of a peripheral circuit region, and specifically, a pad region in which a pad is to be formed is illustrated.

First, as shown in FIG. 1A, an etching target layer 102 is formed on the substrate 100 on which the gate conductive film 101 is formed. In this case, the etching target layer 102 serves as a hard mask during an etching process for etching the gate conductive film 101 and is formed of a laminated film of an oxide film and a nitride film.

Subsequently, the polysilicon film 103 and the amorphous carbon film 104 are sequentially formed on the etched layer 101.

Subsequently, a silicon oxynitride film (SiON) 105 is formed on the amorphous carbon film 104.

Subsequently, a photosensitive film pattern 106 is formed on the silicon oxynitride film 105.

Subsequently, as illustrated in FIG. 1B, the silicon oxynitride film 105 (see FIG. 1A) and the amorphous carbon film 104 (see FIG. 1A) are etched using the photoresist pattern 106. As a result, the silicon oxynitride film pattern 105A and the amorphous carbon film pattern 104A are formed on the polysilicon film 103.

Subsequently, as illustrated in FIG. 1C, an oxide film 107 is formed on the polysilicon film 103 along the stepped surface of the silicon oxynitride film pattern 105A and the amorphous carbon film pattern 104A.

Subsequently, as illustrated in FIG. 1D, the oxide film 107 is etched to form spacers 107A on both sidewalls of the amorphous carbon film pattern 104A. In this process, the silicon oxynitride film pattern 105A (see FIG. 1C) is removed.

Subsequently, as shown in FIG. 1E, a spin on carbon film 108 is formed on the polysilicon film 103 to cover the amorphous carbon film pattern 104A and the spacer 107A.

Subsequently, a multi function hard mask (MFHM) 109 is formed on the spin-on carbon film 108.

Subsequently, a pad forming photosensitive film pattern 110 is formed on the multifunctional hard mask 109.

Subsequently, as shown in FIG. 1F, the multifunctional hard mask 109 (see FIG. 1E) and the spin-on carbon film 108 (see FIG. 1E) are etched using the photoresist pattern 110 as an etching mask. As a result, the multifunctional hard mask pattern 109A and the spin-on carbon film pattern 108A are formed. In this process, the spacer 107B is also partially etched.

Next, the amorphous carbon film pattern 104A (see FIG. 1E) is removed.

Next, the polysilicon film 103 (see FIG. 1E) is etched using the spacer 107B and the multifunctional hard mask pattern 109A as an etching mask. As a result, the polysilicon film pattern 103A is formed.

Subsequently, as illustrated in FIG. 1G, an etching process and a cleaning process are performed to remove the multi-functional hard mask pattern 109A and the spin-on-carbon film pattern 108A, and then the etching layer 102 (see FIG. 1F) is etched. Each layer pattern 102A is formed. In this process, the polysilicon layer pattern 103B used as an etching mask is partially etched.

Subsequently, as shown in FIG. 1H, the remaining polysilicon film pattern 103B is removed.

However, in the method of forming a fine pattern of a semiconductor device applying the SPT process according to the prior art, as shown in FIGS. 1E to 1G, a spion carbon film, an amorphous carbon film, and a polysilicon film are etched, which is difficult to combine the etching gas. Since a fine pattern must be formed, an etching process must be performed several times using an ex-situ process. As a result, the process is somewhat complicated, and the production cost increases.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a method for forming a fine pattern of a semiconductor device, which can simplify the process and lower the manufacturing cost.

According to an aspect of the present invention, a first hard mask, an etch wall layer, and a second hard material made of the same material as the first hard mask are formed on a substrate including a cell region and a pad region and having an etched layer formed thereon. Forming a mask, etching the second hard mask of the cell region using a first photoresist pattern, and forming a second hard mask pattern; forming spacers on both sidewalls of the second hard mask pattern; Forming a third hard mask made of the same material as the first hard mask so as to cover the spacer, and using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. A step of sequentially etching a third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask, and the etched layer in-situ A method of forming a fine pattern of a semiconductor device including a system is provided.

According to the present invention having the above-described configuration, the films required for etching the etched layer are formed by stacking the films required to be etched into the same material or materials having similar etching characteristics to each other, including the etched layer, thereby forming them in the same equipment. It is possible to proceed with the etching process in-situ, it is possible to simplify the process to lower the manufacturing cost.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described.

In the drawings, the widths, thicknesses, and spacings of layers (films, regions) are exaggerated for clarity and convenience of explanation, and should be understood within the scope if the scope is set forth in the specification. In addition, the parts denoted by the same reference numerals represent the same layer, and when the reference numerals include English, it means that the same layer is partially modified through the process.

2A to 2H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention. Here, a method of forming a fine pattern of a semiconductor device using a hard mask formed on the gate electrode as an etched layer will be described. 2A to 2H, 'A' is a cell region in which a cell is to be formed, and 'B' is a region showing a part of a peripheral circuit region, and specifically, a pad region in which a pad is to be formed is illustrated.

First, as shown in FIG. 2A, an etching target layer 202, which is a hard mask, is formed on the semiconductor substrate 200 on which the gate electrode 201 is formed. In this case, the etched layer 202 may be formed of any one selected from materials having a high etching selectivity with the gate electrode 201. For example, the etched layer 202 is formed of a laminated film in which an oxide film and a nitride film are laminated. Specifically, the oxide film is formed of TEOS (Tetra Ethyle Ortho Silicate). The etched layer 202 is formed to a thickness of 1500 to 2500 kPa, preferably 1950 kPa.

The gate electrode 201 may be formed of a transition metal, a polycrystalline silicon film, a metal silicide layer, or a laminated film in which the gate electrode 201 is stacked. In this case, as the transition metal, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg are used. In addition, the metal silicide layer is formed through the reaction of the above-described transition metal and silicon, for example, a tungsten silicide layer.

Subsequently, a first hard mask 203 is formed on the etched layer 202. In this case, the first hard mask 203 may be formed of any one selected from heterogeneous materials having an etching selectivity with the etched layer 202. Preferably, the first hard mask 203 is formed of a spin-on carbon film. Further, the first hard mask 203 is formed to a thickness of 2000 to 3000 kPa, preferably 2500 kPa.

Subsequently, an etch barrier layer 204 is formed on the first hard mask 203. In this case, the etch barrier layer 204 may be formed of any one selected from heterogeneous materials having an etching selectivity with the first hard mask 203. Preferably, it is formed of a silicon oxide film (SiO 2 ) or a silicon oxynitride film (SiON). The etching barrier layer 204 is formed to a thickness of 300 ~ 500 kPa, preferably 400 kPa.

Subsequently, a second hard mask 205 is formed on the etch barrier layer 204. In this case, the second hard mask 205 is formed of the same material as the first hard mask 203. Preferably, the second hard mask 205 is formed of a spin-on carbon film. The second hard mask 205 is formed to a thickness of 100 kHz to 1300 얇은, preferably 1200 Å, thinner than the first hard mask 203.

Subsequently, a first anti-reflection film 206 may be formed on the second hard mask 205. In this case, the first antireflection film 206 is formed of a silicon oxynitride film (SiON) which is an interferometer antireflection film.

Subsequently, the photoresist pattern 207 is formed on the first anti-reflection film 206 in the cell region A. FIG.

Subsequently, as shown in FIG. 2B, the first anti-reflection film 206 (see FIG. 2A) and the second hard mask 205 (see FIG. 2A) are etched using the photoresist pattern 207 (see FIG. 2A). At this time, the etching process may be performed by a dry or wet etching process, it is preferable to perform the dry etching process to obtain a vertical profile (vertical profile). Through the etching process, the first anti-reflection film pattern 206A and the second hard mask pattern 205A are formed.

Subsequently, as illustrated in FIG. 2C, a sacrificial layer 208 is formed on the etch barrier layer 204 along the stepped surface of the second hard mask pattern 205A and the first reflective film forming pattern 206A. At this time, the sacrificial film 208 is formed of a low temperature oxide (LTO) deposited in a temperature range of 0 ~ 200 ℃.

Subsequently, as illustrated in FIG. 2D, the sacrificial layer 208 (see FIG. 2C) is etched to form spacers 208A on both sidewalls of the second hard mask pattern 205A. In this case, the etching process is preferably formed by a dry etching process, and more preferably carried out by an etchback process.

Subsequently, as illustrated in FIG. 2E, a third hard mask 209 is formed to cover the spacer 208A and the second hard mask pattern 205A. In this case, the third hard mask 209 is formed of the same material as the first hard mask 203. Preferably, it is formed of a spin-on carbon film. The third hard mask 209 is formed thicker by about 400 to 600 microns from the upper surface of the spacer 208A. Preferably it is formed thicker about 500 mm3. As a result, a thickness of 1800-2200 mm 3 and a thickness of 2000 mm 3 is formed from an upper surface of the etching barrier layer 204.

Subsequently, a second anti-reflection film 210 may be formed on the third hard mask 209. In this case, the second antireflection film 210 is formed of a silicon oxynitride film (SiON). The second antireflection film 210 is formed to a thickness of 200 ~ 400Å. Preferably it is formed to a thickness of 300 kPa.

Subsequently, a second photoresist film pattern 211 is formed on the second anti-reflection film 210 in the pad area B. FIG.

Subsequently, as shown in FIG. 2F, the second anti-reflection film 210, the third hard mask 209, the etch barrier layer 204, and the second photoresist film pattern 211 shown in FIG. 2E are etched. One hard mask 203 is sequentially etched. In this process, the second hard mask pattern 205A made of the same material as the third hard mask 209 is also etched and removed. Thus, the etch barrier layer pattern 204A and the first hard mask pattern 203A are formed in the cell region A, and the first and third hard mask patterns 203A and 209A and the etch barrier are formed in the pad region B. Layer pattern 204A is formed.

Subsequently, as shown in FIG. 2G, in the cell region A, the spacer 208B, the etch barrier layer pattern 204A, and the first hard mask pattern 203A shown in FIG. 2F are etch masks, and the pad region is etched. In (B), the etching target layer 202 is etched using the third hard mask pattern 209A, the etching barrier layer pattern 204A, and the first hard mask pattern 203A as an etching mask. As a result, the etched layer pattern 202A is formed.

The etching process performed in FIGS. 2F and 2G may be performed in-situ as a dry etching process in the same equipment. The reason for this is that the first and third hard masks 203 and 209 are formed of the same material, and the etching target layer 202 and the etching barrier layer 204 are formed of the same or similar etching characteristics, so that even in the same equipment. Gas combinations are possible. Of course, the process of removing the first hard mask pattern 203B to be performed in FIG. 2H may also be performed in-situ. As a result, it is possible to obtain an advantage of simplifying the etching process and lowering the manufacturing cost.

The etching process performed in FIGS. 2F and 2G is used as an ICP (Inductively Coupled Plasma) equipment.

For example, the etching process for forming the first and third hard mask patterns 203A and 209A uses at least one gas selected from the group consisting of HBr, Cl 2 or CH 4 as the main gas, and O as the additive gas. At least one gas selected from the group consisting of 2 , N 2 , CO or Ar is used. Etching process for forming the etching barrier layer pattern 204A is CH 4 , CHF 3 And O 2 gas. The etching process for forming the etched layer pattern 202A is main gas CH 4 , CHF 3 And CH 2 F 2 , and either gas of C 4 F 6 or C 4 F 8 is used as the additive gas.

Next, as shown in FIG. 2H, the first hard mask pattern 203B shown in FIG. 2G is removed.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, the present invention can be applied to a method for forming a gate electrode fine pattern of a DRAM memory device or a FLASH memory device. As such, those skilled in the art will appreciate that various embodiments are possible within the scope of the inventive idea.

1A to 1H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device to which the SPT process according to the prior art is applied.

2A to 2H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device to which an SPT process is applied according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200 substrate 201 gate electrode

202: etched layer 202A: etched layer pattern

203: First Hard Mask 203A: First Hard Mask Pattern

204: etching barrier layer 204A: etching barrier layer pattern

205: second hard mask 205A: second hard mask pattern

206: first antireflection film 206A: first antireflection film pattern

207: first photosensitive film pattern 208: sacrificial film

208A, 208B: Spacer 209: Third Hard Mask

209A: Third hard mask pattern 210: Second antireflection film

211: second photosensitive film pattern

Claims (12)

Forming a first hard mask, an etch wall layer, and a second hard mask made of the same material as the first hard mask on a substrate including a cell region and a pad region and having an etched layer formed thereon; Etching the second hard mask of the cell region using a first photoresist pattern to form a second hard mask pattern; Forming spacers on both sidewalls of the second hard mask pattern; Forming a third hard mask made of the same material as the first hard mask to cover the spacers; And The third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask and the etched layer are formed by using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. Etching sequentially in-situ Method of forming a fine pattern of a semiconductor device comprising a. The method of claim 1, The first to third hard masks are formed with a spinon carbon film. The method of claim 1, The etching barrier layer is formed of a silicon oxynitride film or a silicon oxide film fine pattern forming method of a semiconductor device. The method of claim 1, The spacer is a fine pattern forming method of a semiconductor device formed of an oxide film. The method of claim 1, The etching pattern layer is a fine pattern forming method of a semiconductor device formed of a laminated film in which an oxide film and a nitride film are laminated. The method of claim 1, The third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask and the etched layer are formed by using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. Etching sequentially in-situ, A method of forming a fine pattern of a semiconductor device by using ICP (Inductively Coupled Plasma) equipment. The method of claim 2, The third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask and the etched layer are formed by using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. In the step of sequentially etching in-situ, At least one gas selected from the group consisting of HBr, Cl 2 or CH 4 is used as the main gas, and at least one gas selected from the group consisting of O 2 , N 2 , CO or Ar is used as the additive gas. A method of forming a fine pattern of a semiconductor device for etching the first and third hard masks. The method of claim 3, wherein The third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask and the etched layer are formed by using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. In the step of sequentially etching in-situ, CH 4 , CHF 3 And forming a fine pattern of the semiconductor device by etching the etching barrier layer using O 2 . The method of claim 4, wherein The third hard mask, the second hard mask pattern, the etch barrier layer, the first hard mask and the etched layer are formed by using the second photoresist pattern formed on the pad region and the spacer of the cell region as an etch mask. In the step of sequentially etching in-situ, Main gas furnace CH 4 , CHF 3 And CH 2 F 2 , and etching the etched layer using any one of C 4 F 6 or C 4 F 8 as an additive gas. The method of claim 1, After the forming of the second hard mask, And forming a first anti-reflection film on the second hard mask. The method of claim 10, After forming the third hard mask, And forming a second anti-reflection film on the third hard mask. The method of claim 11, The first and the second anti-reflection film is a silicon oxynitride film is a fine pattern forming method of a semiconductor device.
KR1020080137058A 2008-12-30 2008-12-30 Method for forming micropattern in semiconductor device KR20100078716A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9349952B1 (en) 2014-12-08 2016-05-24 Sony Corporation Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
US9589964B1 (en) 2015-06-24 2017-03-07 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US11651962B2 (en) 2020-07-02 2023-05-16 SK Hynix Inc. Method of forming patterns using reverse patterns

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9349952B1 (en) 2014-12-08 2016-05-24 Sony Corporation Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
WO2016092741A1 (en) * 2014-12-08 2016-06-16 Sony Corporation Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
US10096772B2 (en) 2014-12-08 2018-10-09 Sony Semiconductor Solutions Corporation Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
US9589964B1 (en) 2015-06-24 2017-03-07 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US11651962B2 (en) 2020-07-02 2023-05-16 SK Hynix Inc. Method of forming patterns using reverse patterns

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