KR20100078468A - Overlay mark and measuring method thereby - Google Patents

Overlay mark and measuring method thereby Download PDF

Info

Publication number
KR20100078468A
KR20100078468A KR1020080136740A KR20080136740A KR20100078468A KR 20100078468 A KR20100078468 A KR 20100078468A KR 1020080136740 A KR1020080136740 A KR 1020080136740A KR 20080136740 A KR20080136740 A KR 20080136740A KR 20100078468 A KR20100078468 A KR 20100078468A
Authority
KR
South Korea
Prior art keywords
overlay
box
boxes
outer box
scribe line
Prior art date
Application number
KR1020080136740A
Other languages
Korean (ko)
Inventor
강석주
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080136740A priority Critical patent/KR20100078468A/en
Publication of KR20100078468A publication Critical patent/KR20100078468A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Abstract

PURPOSE: An overlay mark and a method for measuring an overlay using the same are provided to reduce the size of a scribe line by vertically arranging overlay boxes and reducing the horizontal axis size of the overlay boxes. CONSTITUTION: A plurality of overlay boxes includes inner boxes(120) and outer boxes(100) with rectangular shapes. The inner boxes are formed in a scribe line. The inner boxes and the outer boxes are spaced apart by constant intervals. The horizontal axises are shorter than the vertical axises of the inner boxes and the outer boxes. The overlay boxes are arranged in a vertical direction.

Description

Overlay mark and overlay measurement method using the same {OVERLAY MARK AND MEASURING METHOD THEREBY}

The present invention relates to a semiconductor device, and more particularly, to an overlay mark and an overlay measuring method using the same.

In general, the manufacturing process of a semiconductor device is to form a specific pattern on the wafer. In particular, in the lithography process using a pattern transfer mechanism such as a light source and a mask, the semiconductor device can be realized only when the alignment between the pattern formed in the previous process and the pattern formed in the subsequent process is precisely performed. In the lithography process, the overlay box is used to check the alignment between the patterns of the before and after process. By measuring the alignment of the overlay box generated in the before and after process, the degree of alignment of the before and after process can be determined. .

The overlay box is formed around the chip of the wafer and in a scribe line that is cut and discarded after the wafer process is completed.

In this case, an overlay box is drawn on the mask used in each step, and the overlay box formed in the previous process, that is, the outer box becomes the mother of the reference key, and the overlay box formed in the later process, that is, the inner box ) Becomes the son of the measurement key.

Such an overlay box has a problem in that the overlay boxes of shots corresponding to the left and right sides of the striving line are parallel to each other, so that the striving line is inevitably increased to decrease the efficiency of the entire wafer.

An object of the present invention is to provide an overlay mark and an overlay measuring method using the same for reducing the scribe line size and maximizing wafer efficiency.

The overlay mark according to an embodiment of the present invention for achieving the above object is formed in the scribe line and the inner box formed in the previous step of the semiconductor process, a plurality of overlay box consisting of the outer box formed in the later step, The inner box and the outer box are formed at regular intervals from each other, characterized in that the horizontal axis is formed in a rectangular shape shorter than the vertical axis.

An overlay measuring method according to an embodiment of the present invention for achieving the above object is the step of forming an outer box in the scribe line at all stages of the semiconductor process, forming an inner box in the outer box, and the outer And measuring an alignment of the inner box so that extension lines connecting both ends of the box meet at the intermediate point.

A method of manufacturing a semiconductor device according to an embodiment of the present invention has the following effects.

By aligning the overlay boxes vertically and slimming down the horizontal axis size of the overlay box, the scribe line size can be reduced and the wafer efficiency can be maximized.Also, alignment measurement can be performed even if the box is not in the form of a box, thereby maximizing productivity. .

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

1 is a diagram illustrating a general overlay mark.

The overlay mark of FIG. 1 is an alignment element of a wafer component and a shot component by measuring positions of an inner box 20 and an outer box 10 having a square shape. To prevent misalignment.

However, such an overlay box is formed around the chip of the wafer and is formed in a scribe line that is cut and discarded after the wafer process is completed. Since the overlay boxes are parallel to each other, the streaking lines are inevitably increased, which reduces the efficiency of the entire wafer.

2 is a view showing an overlay mark according to the present invention.

Here, although four overlay marks are made, only one overlay mark will be described, for example.

As shown in FIG. 2, the overlay box generated in the actual scribe line is changed from the existing horizontal arrangement to the vertical arrangement, and the horizontal size of the overlay box, that is, the inner box 120 and the outer box 100 is shown. To form a rectangular shape.

Each of the inner box 120 and the outer box 100 is formed in the shape of a picture frame with a central opening.

Here, the longitudinal length A of the outer side of the outer box 100 is 22 μm, the longitudinal length B of the inner side is 18 μm, and the width C of the outer box 100 is 2 μm. The longitudinal length D of the outer side of the inner box 120 is 10 μm, the longitudinal length F of the inner side is 6 μm, and the width G of the inner box is 2 μm. The distance E between the outer box 100 and the inner box 120, that is, the distance between the inner surface of the outer box 100 and the outer surface of the inner box 120 is 4 μm.

However, the value of the overlay box is not limited to this.

Here, the outer box 100 becomes the mother of the reference key, and the overlay box formed in a later step, that is, the inner box 120, becomes the son of the measurement key.

When the overlay box is measured, the overlay measuring device calculates the data of the points corresponding to the midpoints of the imaginary line connecting the mother or son, and calculates the arrangement of the layer before and after. have.

Measuring the degree of alignment of the layer before and after actually measuring the degree of deviation of the inner box 120 from the outer box 100 is measured by the overlay box drawn on the mask of the layer before and after the actual layer. It is possible to measure even if the horizontal size of the overlay box, that is, the inner box 120 and the outer box 100 is reduced.

Even if the overlay mark is not in the form of a box as shown in FIG. 3, when the center point connecting the end and the center of the outer box line 100 is the origin, the son, that is, the inner box 120 generated in a subsequent layer, is formed. The alignment of can be measured.

By vertically arranging the overlay boxes in a conventional manner and then reducing the horizontal axis size of the overlay box, as the scribe line size is reduced, more devices can be produced in the same area of the wafer, thereby maximizing wafer efficiency. ,

In addition, since the alignment can be measured even if the box is not in the form, it is possible to maximize the productivity.

In this way, the overlay mark arrangement and the slim design are not limited to the box shape, but are applicable to the trench, mesa type, bar, chain type, and the like.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a diagram illustrating a general overlay mark.

2 is a view showing an overlay mark according to the present invention.

3 is a view showing a method of measuring the degree of alignment of the outer box and the inner box according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: outer box 120: inner box

Claims (4)

A plurality of overlay boxes formed on the scribe line and formed of an inner box formed at a previous stage of the semiconductor process, an outer box formed at a later stage, The inner box and the outer box are formed at regular intervals from each other, the overlay mark, characterized in that formed in a rectangular shape whose horizontal axis is shorter than the vertical axis. The method of claim 1, And overlay boxes arranged in a vertical direction. Forming an outer box on the scribe line at all stages of the semiconductor process; Forming an inner box in the outer box; And measuring an alignment of the inner box such that extension lines connecting both ends of the outer box meet at an intermediate point. The method of claim 3, wherein The overlay box measuring method, characterized in that arranged in the vertical direction.
KR1020080136740A 2008-12-30 2008-12-30 Overlay mark and measuring method thereby KR20100078468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080136740A KR20100078468A (en) 2008-12-30 2008-12-30 Overlay mark and measuring method thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080136740A KR20100078468A (en) 2008-12-30 2008-12-30 Overlay mark and measuring method thereby

Publications (1)

Publication Number Publication Date
KR20100078468A true KR20100078468A (en) 2010-07-08

Family

ID=42639680

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080136740A KR20100078468A (en) 2008-12-30 2008-12-30 Overlay mark and measuring method thereby

Country Status (1)

Country Link
KR (1) KR20100078468A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11537041B2 (en) 2019-11-04 2022-12-27 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11537041B2 (en) 2019-11-04 2022-12-27 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
CN101644898B (en) Method for measuring alignment precision among lithography machines with different magnifications
US20130120739A1 (en) Structure for critical dimension and overlay measurement
SG150396A1 (en) Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
JP2010278041A (en) Method of forming template for imprinting and imprinting method using the template
US20140254916A1 (en) Methods for measuring overlays
CN103065929B (en) Manufacture method of alignment mark protective layer
TW201640228A (en) Overlay mark pattern and method of correcting overlay error
US9054113B1 (en) Box-in-box overlay mark
KR20100078468A (en) Overlay mark and measuring method thereby
CN105740540A (en) Method for searching characteristic graphs of layouts in mask design
CN105321799B (en) Asymmetry compensation method for photoetching overlay manufacture craft
CN203720532U (en) Photoetching marking structure
CN103681624B (en) Overlay marks and forming method thereof
CN102034736B (en) Photoetching method of contact hole
TW201327028A (en) Mask production method for maximizing the number of chips on a wafer
JP2012164811A (en) Method of manufacturing semiconductor device, method of determining shipping of exposure mask and method of manufacturing exposure mask
US20160126194A1 (en) Measurement mark structure and manufacturing method thereof
US11587889B2 (en) Reduced pattern-induced wafer deformation
KR100906050B1 (en) Alginment mark
KR20040003936A (en) Align mark in semiconductor device
KR20070073052A (en) Method for forming semiconductor device
KR100608385B1 (en) Overlay measurement pattern for semiconductor device manufacture
CN104752408B (en) Test structure for contact hole and grid alignment precision in measuring circuit device
CN204029841U (en) Light-emitting diode chip for backlight unit
US20150276382A1 (en) Measurement mark structure

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination