KR20100078336A - Fabrication method for bump of a semiconductor device - Google Patents

Fabrication method for bump of a semiconductor device Download PDF

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KR20100078336A
KR20100078336A KR1020080136570A KR20080136570A KR20100078336A KR 20100078336 A KR20100078336 A KR 20100078336A KR 1020080136570 A KR1020080136570 A KR 1020080136570A KR 20080136570 A KR20080136570 A KR 20080136570A KR 20100078336 A KR20100078336 A KR 20100078336A
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layer
bump
silver
bumps
semiconductor device
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KR1020080136570A
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Korean (ko)
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권산무
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE: A method for forming the bumps of a semiconductor device is provided to simplify the manufacturing process of the bumps by forming silver bumps through one photolithography process. CONSTITUTION: A passivation layer(204) is applied on the metal pad of a semiconductor substrate. A pad contact(206) is formed on the passivation layer to expose the metal pad. A titanium tungsten(TiW) layer is applied on the passivation including the pad contact. A silver bump layer(210) is applied on the titanium tungsten layer. A silver seed layer and a silver bulk layer are successively stacked to form the silver bump layer. The silver bump layer is patterned to form silver bumps on the upper side of the pad contact. After the silver bump layer is patterned, the exposed titanium tungsten layer is etched.

Description

반도체 소자의 범프 형성방법{Fabrication method for bump of a semiconductor device}Fabrication method for bumps of semiconductor devices

본 발명은 반도체 소자의 범프(bump)의 형성방법으로서, 특히 플립 칩 기술을 이용하여 반도체 소자를 직접 인쇄회로기판에 접속하여 실장하는데 이용되는 Au 범프를 형성하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a bump of a semiconductor device, and more particularly, to a method of forming an Au bump used to directly connect and mount a semiconductor device to a printed circuit board using flip chip technology.

반도체 소자의 고집적화에 따라 반도체 소자의 패키징 기술도 고기능 및 고밀도 실장에 대한 요구가 증대되고 있다. 따라서 종래의 선 접속(wire bonding)으로는 이러한 요구를 충족시키지 못하며 이에 따라 플립 칩 기술이 새롭게 각광을 받고 있다. 플립 칩 기술이란, 기존의 단일 칩 패키지 구조에서와 같은 리드 프레임을 없애고 베어 칩(bare chip) 자체를 인쇄회로기판에 직접 접속하는 방식을 말한다. 이러한 플립 칩 기술은 칩 크기가 곧 패키기 크기로 축소되므로 시스템의 소형화, 경량화에 매우 적합하며 전송속도 또한 칩 밑면에 많은 입출력 핀을 설정할 수 있기 때문에 기존의 선 접속 패키지에 비해 약 20~30배 빠른 것으로 알려져 있다. 이러한 플립 칩 기술에서는 반도체 소자와 인쇄회로기판을 서로 연결하는 범프(bump)의 제조방법이 핵심기술 중의 하나이다. 종래부터 널리 사용되는 범프의 제조방법은 금(Au)를 전기도금법으로 형성하는 것이었다. 도 1a 내지 도 1g 에는 종래의 Au 범프를 형성하는 방법이 도시되어 있다. BACKGROUND With the high integration of semiconductor devices, the demand for high-performance and high-density packaging technology has increased. Therefore, the conventional wire bonding does not meet this requirement, and thus the flip chip technology is emerging. Flip chip technology refers to a method in which a bare chip itself is directly connected to a printed circuit board by eliminating a lead frame as in a conventional single chip package structure. Since the chip size is reduced to the package size, this flip chip technology is very suitable for the system's miniaturization and light weight, and the transmission speed is also about 20 to 30 times that of the existing wiring package because many input / output pins can be set at the bottom of the chip. It is known to be fast. In such flip chip technology, a method of manufacturing a bump that connects a semiconductor device and a printed circuit board to each other is one of core technologies. Conventionally, a widely used method for producing bumps has been to form Au by electroplating. 1A to 1G illustrate a method of forming a conventional Au bump.

도 1a에 도시된 바와 같이, 반도체 기판(100) 상에 신호 전달을 위해 형성되는 금속패드(102), 일예로 알루미늄 패드를 형성한 후 반도체 소자를 외부로부터 보호하기 위한 패시베이션층(104), 일예로 실리콘 질화막을 도포한 후 상기 금속패드(102)를 외부로 노출시키는 패드콘택(106)을 형성한다. 다음, 도 1b에 도시된 바와 같이, 배리어층으로 TiW 층(108)을 도포하고 그 상부에 범프의 전기도금을 위한 시드(seed)층으로 Au 층(110)을 형성한다. 이때 TiW 층 및 Au 층은 모두 스퍼터링법(sputtering)으로 형성될 수 있다. 다음, 도 1c에 도시된 바와 같이, 감광막(112)을 도포한 후 노광 및 현상 공정을 이용하여 도 1d와 같이 패터닝하여 범프가 형성될 영역의 감광막을 제거한다. 다음으로 도 1e에 도시된 것과 같이, Au를 전기도금법을 이용하여 도금층(114)을 형성하며, 이때 Au는 시드층이 드러난 영역에만 도금되게 된다. 다음 도 1f와 같이, 감광막(112)을 제거하고 감광막 제거로 인해 드러난 Au 시드층(110) 및 TiW 배리어층(108)을 순차적으로 식각해 냄으로서 도 1g와 같은 Au 범프를 형성하게 된다. As shown in FIG. 1A, a metal pad 102 formed on the semiconductor substrate 100 for signal transmission, for example, an passivation layer 104 for protecting an semiconductor device from the outside after forming an aluminum pad, for example After applying a silicon nitride film to form a pad contact 106 to expose the metal pad 102 to the outside. Next, as shown in FIG. 1B, a TiW layer 108 is applied as a barrier layer and an Au layer 110 is formed as a seed layer for electroplating bumps thereon. In this case, both the TiW layer and the Au layer may be formed by sputtering. Next, as shown in FIG. 1C, the photoresist film 112 is coated and then patterned as shown in FIG. 1D using an exposure and development process to remove the photoresist film in the region where the bump is to be formed. Next, as illustrated in FIG. 1E, Au is plated by using an electroplating method, and the Au is plated only in the region where the seed layer is exposed. Next, as shown in FIG. 1F, the Au seed layer 110 and the TiW barrier layer 108 exposed by the photoresist removal are sequentially etched to form Au bumps as illustrated in FIG. 1G.

그러나 이러한 종래의 Au 범프의 형성방법은 Au 시드층을 형성하고 감광막을 패터닝한 후 다시 Au를 전기도금법으로 형성하게 되므로 감광막을 제거하여 범프의 형상을 완성한 경우라도 그 하부의 Au 시드층 및 TiW 배리어층을 다시 식각하는 공 정을 거쳐야 하는 번거로움이 존재하였다. However, in the conventional Au bump forming method, the Au seed layer is formed, the photoresist film is patterned, and then Au is formed by electroplating. Thus, even when the photoresist film is removed to form the bumps, the Au seed layer and the TiW barrier underneath are formed. The hassle has to go through the process of etching the layers again.

　　　

본 발명은 상술한 것과 같은 플립 칩 기술에 사용되는 범프를 제작하는 과정에서 Au 층에 대하여 한번의 사진식각공정만을 적용함으로써 범프를 형성할 수 있는 보다 단순화된 범프의 형성방법의 제공을 목적으로 한다. An object of the present invention is to provide a method for forming a simpler bump that can form a bump by applying only one photolithography process to an Au layer in manufacturing a bump used in a flip chip technique as described above. .

상술한 본 발명의 목적를 달성하기 위하여 본 발명은 반도체 기판 상의 금속패드 위에 패시베이션층을 도포하고 상기 금속패드를 노출시키는 패드콘택을 형성하는 단계와 상기 패드콘택이 형성된 패시베이션층 상에 TiW 층을 도포하는 단계와 상기 TiW 층 상에 Au 범프층을 도포하는 단계와 상기 패드콘택의 상부에 Au 범프가 형성되도록 상기 Au 범프층을 사진식각공정으로 패터닝하는 단계와 상기 TiW 층 중 상기 Au 범프층의 패터닝 후 드러난 부분을 식각하여 제거하는 단계를 포함하는 반도체 소자의 범프 형성방법을 제공한다. In order to achieve the above object of the present invention, the present invention is to apply a passivation layer on the metal pad on the semiconductor substrate and to form a pad contact that exposes the metal pad and to apply a TiW layer on the passivation layer formed with the pad contact After the step of applying an Au bump layer on the TiW layer, patterning the Au bump layer by a photolithography process to form Au bumps on top of the pad contact and patterning the Au bump layer of the TiW layer Provided is a method of forming a bump of a semiconductor device, including etching and removing exposed portions.

이때 상기 Au 범프층은 Au 시드층과 Au 벌크층이 순차적으로 적층하여 형성될 수 있으며, 상기 Au 시드층은 스퍼터링 방법으로 형성하고 상기 Au 벌크층은 전기도금으로 형성할 수 있다.The Au bump layer may be formed by sequentially stacking an Au seed layer and an Au bulk layer. The Au seed layer may be formed by a sputtering method, and the Au bulk layer may be formed by electroplating.

본 발명에 의할 시, Au 범프층을 형성함에 있어서 시드층과 벌크층을 연속적으로 진행한 후 한번의 사진식각공정에 의해 Au 범프를 형성하게 되므로 공정이 단순화 되어 종래와 같이 감광막을 제거하여 범프를 형성한 후 다시 시드층 및 배리어층을 식각 해내는 번잡함을 제거할 수 있다. In the present invention, in forming the Au bump layer, the seed layer and the bulk layer are continuously formed, and then the Au bump is formed by one photolithography process, thus simplifying the process to remove the bumps as in the prior art. After the formation of the oxide, the seed layer and the barrier layer may be removed to remove the complexity.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다. 아울러 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

도 2a 내지 도 2f는 본 발명에 따른 범프 형성방법을 도시한 것이다. 2A to 2F illustrate a bump forming method according to the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(200) 상에 형성된 금속패드(202) 위에 패시베이션층(204)를 도포하고 상기 금속패드(202)의 일부를 노출시키는 패드콘택(206)을 형성한다. 이때 금속패드(202)는 알루미늄층을 도포한 후 사진식각공정을 이용하여 형성할 수 있다.As shown in FIG. 2A, a passivation layer 204 is applied on the metal pad 202 formed on the semiconductor substrate 200, and a pad contact 206 is formed to expose a portion of the metal pad 202. In this case, the metal pad 202 may be formed using a photolithography process after coating the aluminum layer.

다음 도 2b에 도시된 바와 같이, 패드콘택(206)이 형성된 패시베이션층 상(204)에 배리어층으로 TiW 층(208)를 스퍼터링 방법으로 증착한다. 이때 패시베이션층은 반도체 기판에 형성된 각종 반도체 단위 소자를 외부로부터 보호하는 층으로서 화학기상증착법(chemical vapor deposition)을 이용한 실리콘 질화막이나 실리콘 산화막으로 형성할 수 있다. 경우에 따라서는 실리콘 질화막의 강한 스트레스를 감소시키기 위하여 실리콘 산화막 상에 실리콘 질화막을 연속 적층하는 2중층 구조로 형성할 수 있다. Next, as shown in FIG. 2B, the TiW layer 208 is deposited by a sputtering method on the passivation layer 204 on which the pad contact 206 is formed as a barrier layer. In this case, the passivation layer may be formed of a silicon nitride film or a silicon oxide film using chemical vapor deposition as a layer for protecting various semiconductor unit devices formed on a semiconductor substrate from the outside. In some cases, in order to reduce the strong stress of the silicon nitride film, it may be formed in a double layer structure in which a silicon nitride film is continuously laminated on the silicon oxide film.

다음 도 2c와 같이 Au로 이루어진 범프층(214)을 형성한다. 이때 범프층(214)은 Au 시드층(210)과 Au 벌크층(212)이 연속적으로 형성된 구조를 갖는다. 상기 Au 시드층(210)은 스퍼터링 방법과 같은 박막제조 공정에 의해 형성되며 후속하는 Au 벌크층(212)을 전기도금법으로 형성할 시 시드를 제공하는 역할을 수행한다. 여기서 시드를 제공한다는 것은 Au를 전기도금으로 형성하는 초기에 Au 전기도금층이 원활하게 형성되어 성장할 수 있는 자리를 제공한다는 것을 의미한다. Next, as illustrated in FIG. 2C, a bump layer 214 made of Au is formed. In this case, the bump layer 214 has a structure in which the Au seed layer 210 and the Au bulk layer 212 are continuously formed. The Au seed layer 210 is formed by a thin film manufacturing process such as a sputtering method, and serves to provide a seed when the subsequent Au bulk layer 212 is formed by electroplating. Providing the seed here means that the Au electroplating layer is formed smoothly in the initial formation of the electroplating Au to provide a place to grow.

한편, 상기 Au 벌크층(212)은 상기 Au 시드층(210) 상부에 전기도금법에 의해 형성된다. 이때 Au 시드층(210)이 TiW 층(206)에 전면 도포되어 있으므로 후속되는 Au 벌크층(212)도 시드층(210) 상부의 전 면적에서 도금이 되어 전면 도포되는 양상을 나타내게 된다. Meanwhile, the Au bulk layer 212 is formed on the Au seed layer 210 by an electroplating method. At this time, since the Au seed layer 210 is entirely coated on the TiW layer 206, the subsequent Au bulk layer 212 may also be plated on the entire area of the seed layer 210 to be completely coated.

다음, 도 2d에 도시된 바와 같이, 감광막을 도포하고 노광 및 현상 단계를 통해 감광막(216)을 패턴닝한다. 이때 패터닝된 감광막(216)은 범프층(214) 중 범프로 사용된 부분을 제외하고 모두 노출되는 형태로 패터닝 된다. Next, as shown in FIG. 2D, the photoresist film is applied and the photoresist 216 is patterned through the exposure and development steps. In this case, the patterned photoresist 216 is patterned in such a manner that all of the bump layer 214 is exposed except for the portion used as the bump.

다음 도 2e에 도시된 바와 같이, 상기 패터닝된 감광막(216)을 마스크로 하는 식각공정을 통해 범프층을 식각한다. Next, as shown in FIG. 2E, the bump layer is etched through an etching process using the patterned photoresist 216 as a mask.

다음 도 2f에 도시된 바와 같이, 배리어층인 TiW 층(208)을 식각한 후 잔존하는 감광막을 제거함으로써 범프를 완성할 수 있다.  Next, as illustrated in FIG. 2F, the bump may be completed by etching the TiW layer 208 as a barrier layer and removing the remaining photoresist layer.

이때 한번의 식각과정을 통하여 Au 벌크층(212)와 시드층(210)이 동시에 식각될 수 있다. 또한 경우에 따라서는 한번의 식각과정을 통해 Au 벌크층(212)과 시드층(210) 및 TiW 층(208)을 연속적으로 식각 할 수 있으므로 공정 단순화가 가능하다. In this case, the Au bulk layer 212 and the seed layer 210 may be simultaneously etched through one etching process. In some cases, the Au bulk layer 212, the seed layer 210, and the TiW layer 208 may be continuously etched through one etching process, thereby simplifying the process.

앞서 언급한 실시예는 본 발명을 한정하는 것이 아니라 예증하는 것이며, 이 분야의 당업자라면 첨부한 청구항에 의해 정의된 본 발명의 범위로부터 벗어나는 일 없이, 많은 다른 실시예를 설계할 수 있다. 또한 본 발명의 기술이 당업자에 의하여 용이하게 변형 실시될 가능성이 자명하며, 이러한 변형된 실시 예들은 본 발명의 특허청구범위에 기재된 기술사상에 포함된다고 하여야 할 것이다. The above-mentioned embodiments are illustrative rather than limiting on the present invention, and those skilled in the art can design many other embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, it will be apparent that the technology of the present invention can be easily modified by those skilled in the art, such modified embodiments will be included in the technical spirit described in the claims of the present invention.

도 1a 내지 도 1g는 종래의 반도체 소자의 범프 형성과정을 도시한 것이다. 1A to 1G illustrate a bump forming process of a conventional semiconductor device.

도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 범프 형성과정을 도시한 것이다. 2A to 2G illustrate a bump formation process of a semiconductor device according to the present invention.

<도면의 주요 부호에 대한 간략한 설명> <Brief description of the major symbols in the drawings>

200 : 반도체 기판　 202 : 금속패드 200: semiconductor substrate # 202: metal pad

204 : 패시베이션층 206 : 패드콘택 204: passivation layer 206: pad contact

208 : TiW 층 210 : Au 시드층208 TiW layer 210 Au seed layer

212 : Au 벌크층 214 : Au 범프층212 Au bulk layer 214 Au bump layer

216 : 감광막216 photosensitive film

Claims (3)

반도체 기판 상의 금속패드 위에 패시베이션층을 도포하고 상기 금속패드를 노출시키는 패드콘택을 형성하는 단계와 Applying a passivation layer over the metal pad on the semiconductor substrate and forming a pad contact exposing the metal pad; 상기 패드콘택이 형성된 패시베이션층 상에 TiW 층을 도포하는 단계와 Applying a TiW layer on the passivation layer on which the pad contact is formed; 상기 TiW 층 상에 Au 범프층을 도포하는 단계와 Applying an Au bump layer on the TiW layer; 상기 패드콘택의 상부에 Au 범프가 형성되도록 상기 Au 범프층을 사진식각공정으로 패터닝하는 단계와 Patterning the Au bump layer by a photolithography process to form Au bumps on the pad contacts; 상기 TiW 층 중 상기 Au 범프층의 패터닝 후 드러난 부분을 식각하여 제거하는 단계 Etching and removing portions of the TiW layer that are exposed after the Au bump layer is patterned 를 포함하는 반도체 소자의 범프 형성방법.Bump forming method of a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 Au 범프층은 Au 시드층과 Au 벌크층이 순차적으로 적층하여 형성하는 반도체 소자의 범프 형성방법.The Au bump layer is a bump forming method of a semiconductor device formed by sequentially stacking the Au seed layer and the Au bulk layer. 제 2 항에 있어서, The method of claim 2, 상기 Au 시드층은 스퍼터링 방법으로 형성하고 상기 Au 벌크층은 전기도금으 로 형성하는 반도체 소자의 범프 형성방법.Wherein the Au seed layer is formed by a sputtering method and the Au bulk layer is formed by electroplating.
KR1020080136570A 2008-12-30 2008-12-30 Fabrication method for bump of a semiconductor device KR20100078336A (en)

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