KR20100076738A

KR20100076738A - Flash memory device and data erase method thereof

Info

Publication number: KR20100076738A
Application number: KR1020080134876A
Authority: KR
Inventors: 이용중
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-12-26
Filing date: 2008-12-26
Publication date: 2010-07-06

Abstract

Disclosed is a flash memory device which performs subdivision by word line, that is, page unit by subdividing more than a cell block unit. The flash memory device may include a cell block including a plurality of cell strings in which a plurality of cells are connected in series, and a plurality of word lines sharing gates of cells constituting the cell string on the same row; A plurality of word line switches for switching each word line of the cell block to a predetermined voltage level; And a controller configured to receive an erase command and a row address to control turn-on and turn-off of each word line switch. The improved device eliminates the need to move the entire data from one block to another if only a few pages of data are modified when building a system using flash memory. That is, more expandability can be provided in the use of flash memory devices.

Description

Flash memory device and its data erasing method {FLASH MEMORY DEVICE AND DATA ERASE METHOD THEREOF}

As a technology related to a flash memory device, a NAND type flash memory device that can be erased in word line units in the same cell block is disclosed.

In general, a NAND-type flash memory device includes a plurality of cell blocks. One cell block (also referred to as 'sector') includes a plurality of cell strings in which a plurality of cells are connected in series, and wordlines connected to gates of cells on the same row. A drain select transistor is provided at one end of the cell string for connection with a bit line, and a source select transistor is provided at the other end of the cell string for connection with a common source line. On the other hand, a plurality of memory cells sharing one word line constitutes one page, and all cells in the cell block share a well (usually a P well).

The NAND type flash memory device configured as described above is performed in page units during program and read operations, whereas erasing is performed in cell block units because all cells share a P well. do.

As described above, the conventional NAND type flash memory device that erases cell units has restrictions in updating data. In order to modify some data, it is necessary to transfer the data of all cells in the same block to another. In other words, 64 or 128 pages generally constitute one cell block. In this case, 64 or 128 pages may be modified even when only a part of data is modified when a system is constructed using NAND flash memory due to a difference between an erase operation and a program operation. It is necessary to erase 128 pages and move the data to another cell block.

Therefore, if the erasable unit can be further subdivided than the block unit, more expandability will be provided in the use of the NAND type flash memory device.

The present invention has been proposed to satisfy the above requirements, and an object thereof is to provide a nonvolatile memory device capable of performing cell erase by subdividing into blocks.

A flash memory device for achieving the above object comprises: a cell block comprising a plurality of cell strings in which a plurality of cells are connected in series and a plurality of word lines sharing gates of cells constituting the cell string on the same row; A plurality of word line switches for switching each word line of the cell block to a predetermined voltage level; And a controller configured to receive an erase command and a row address to control turn-on and turn-off of each word line switch.

In this case, the controller turns on only the word line switch selected by the row address to erase only the cells shared in the word line. In the erase operation, the well receives an erase voltage having a potential difference from the voltage level. In addition, memory cells sharing one word line form a page, and cells in the cell block share one well.

In addition, an improved data erasing method in a flash memory is a method of driving a flash memory device having a plurality of word lines that share gates of cells on the same row in one block. Receiving a plurality of word lines, and biasing some of the word lines to a predetermined voltage level. In this case, the predetermined voltage level may be a ground voltage level.

The improved flash memory device divides an erasable unit into more than block units and performs word line units (page units).

That is, when a word block includes a plurality of word lines that share gates of cells on the same row in one block, an erase command and a row address are input to bias some of the word lines to a predetermined voltage level. Only the cells of the biased word line are erased.

This eliminates the need to move the entire data from one block to another when modifying only a few pages of data when building a system using flash memory. That is, more expandability can be provided in the use of flash memory devices.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a block diagram of an improved NAND type flash memory device.

Referring to FIG. 1, an improved NAND type flash memory device includes a cell block 110, a switching unit 130, and a controller 150.

The cell block 110 includes a cell string provided corresponding to m bit lines BL0 to BLm. Looking at the configuration through the cell string provided corresponding to the bit line BLm, the drain select transistor DSTm, the plurality of memory cells CTm0 to CTmn, and the source select transistor SSTm are connected in series.

In addition, the cell block includes a plurality of row lines. The row line includes word lines WL0 to WLn sharing the gates of the memory cells CT constituting each string.

Multiple memory cells that share one word line constitute one page.

And all the cells and select transistors in block 110 share a P well. During the erase operation, the erase voltage VEr is applied to the P well in the block. In the present embodiment, the well is described as a P type, but the type of the well may be different from the type of the transistor constituting the cell string.

The drain select transistors DSTs of each cell string share their drain select line DSL. In addition, the source select transistors SST of each cell string have their source end sharing a common source line CSL, and their gate end sharing the source select line SSL.

The drain select line DSL, the source select line SSL, and the common source line CSL become another row line.

The improved NAND flash memory may perform erasing on a page basis in the cell block 110 described above. That is, the erase is performed in units of word lines. In the present embodiment, the word line switching unit 130 and the control unit 150 are used for page-by-page erasing.

The word line switching unit 130 includes a plurality of word line switches for switching the word lines WL0 to WLn, the drain select line DSL, and the source select line SSL to the ground voltage OV level. At this time, even if the ground voltage level is not the voltage level having a sufficient potential difference with the erase voltage VEr applied to the P well during erasing.

That is, each word line WL0 to WLn in the page unit can be connected to a pre-ground level through a corresponding switch.

In the present embodiment, each switch is composed of an NMOS transistor, but can be implemented as other switching elements.

The controller 150 controls the turn-on and turn-off of each switch by receiving the erase command ERA and the row address ADDR, so that only the switch of the selected word line is turned on so that the selected word line has a ground voltage level.

The erase operation of the improved flash memory device having the configuration of FIG. 1 will be described in detail.

The controller 150 receives the erase command ERA and the address ADDR and turns on only the switch connected to the word line WL1 of page 110A to be erased. As a result, only the word line WL1 becomes the ground level and floats to the remaining word line, the drain select line, and the source select line.

In this state, when the erase voltage VEr is applied to the P well, the potential difference of the erase voltage VEr is generated between the word line WL1 and the P well of the selected page, and the erase is performed according to the F-N tunneling principle.

Meanwhile, in the case of the unselected page, when the P well rises to the erase voltage VEr, the voltage of the unselected word line is equal to the erase voltage VEr due to the coupling effect due to the capacitance of the corresponding word line and the capacitance between the word line and the P well. As a result, the voltage difference between the word line and the P well is small, so that the erasure is not performed. At this time, the bit lines BL0 to BLm and the common source line CSL maintain a floating state.

As a result, the improved flash memory device may perform erase in units of desired word lines. In the embodiment, only one word line is selected and erase is performed only in a cell shared with the word line. However, the controller 150 may be configured to simultaneously turn on a plurality of word line switches in the block 110. As a result, the block may be erased in units of word lines in a specific group.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a flash memory device according to a preferred embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

110: cell block

130: word line switching unit

150: control unit

Claims

A cell block including a plurality of cell strings in which a plurality of cells are connected in series and a plurality of word lines sharing gates of cells constituting the cell string on the same row;

A plurality of word line switches for switching each word line of the cell block to a predetermined voltage level; And

And a controller configured to receive an erase command and a row address to control turn-on and turn-off of each word line switch.

Flash memory device.

The method of claim 1,

The controller turns on only the word line switch selected by the row address to erase only the cells shared in the word line.

Flash memory device.

The method of claim 1,

Memory cells that share a wordline form a page

Flash memory device.

The method of claim 1,

The cells in the cell block share one well

Flash memory device.

The method of claim 4, wherein

In erasing, the well receives an erase voltage having a potential difference from the voltage level.

Flash memory device.

A method of driving a flash memory device having a plurality of word lines sharing a gate of cells on a same row in a block,

Receiving an erase command and a row address, and biasing a portion of the word lines to a predetermined voltage level among the plurality of word lines;

Data erasing method.

The method of claim 6,

The predetermined voltage level is a ground voltage level

Data erasing method.