KR20100076554A - Method for manufacturing electrostatic discharge protection device - Google Patents

Method for manufacturing electrostatic discharge protection device Download PDF

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Publication number
KR20100076554A
KR20100076554A KR1020080134651A KR20080134651A KR20100076554A KR 20100076554 A KR20100076554 A KR 20100076554A KR 1020080134651 A KR1020080134651 A KR 1020080134651A KR 20080134651 A KR20080134651 A KR 20080134651A KR 20100076554 A KR20100076554 A KR 20100076554A
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KR
South Korea
Prior art keywords
region
forming
electrostatic discharge
trench
discharge protection
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Application number
KR1020080134651A
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Korean (ko)
Inventor
이민영
이인찬
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080134651A priority Critical patent/KR20100076554A/en
Publication of KR20100076554A publication Critical patent/KR20100076554A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The present invention is a method of manufacturing an electrostatic discharge protection device that can improve the operating reliability of the device by preventing the leakage current increases in this region by the boron dopant accumulated in the contact area between the halo region and the device isolation film during the halo region formation process To this end, the present invention is to form a device isolation layer in the substrate to define an active region and an inactive region, forming a gate electrode crossing the active region in one direction on the substrate, and Forming a halo region in an active region, forming a source and a drain region in the active region exposed to both sides of the gate electrode, and recessing a portion at which the device isolation layer and the halo region are in contact with a predetermined depth Method of manufacturing an electrostatic discharge protection device comprising the step of forming a to provide.

Description

Manufacturing method of electrostatic discharge protection device {METHOD FOR MANUFACTURING ELECTROSTATIC DISCHARGE PROTECTION DEVICE}

The present invention relates to a peninsula manufacturing technology, and more particularly to a method of manufacturing an electrostatic discharge protection device connected between the internal circuit and the pad to protect the internal circuit.

In general, electrostatic discharge (ESD) protection circuits are designed between semiconductor circuits and pads connected to internal circuits and external input / output pins (hereinafter referred to as 'input and output pads') to prevent product damage and degradation due to static electricity. Refers to a circuit installed on.

1 is a circuit diagram showing a general electrostatic discharge protection circuit having a simple configuration.

Referring to FIG. 1, a general electrostatic discharge protection circuit includes an NMOS transistor functioning as a capacitor 10, a resistor 20, and an electrostatic discharge protection device 30. When an electrostatic pulse is generated, an alternating current flows through the capacitor 10 at the high frequency electrostatic pulse. At this time, the gate voltage of the NMOS transistor is higher than the ground voltage VSS so that the NMOS transistor is turned on so that an electrostatic current flows through the channel of the NMOS transistor. Through this process, the input electrostatic pulse is discharged to the ground terminal.

FIG. 2 is a plan view of the electrostatic discharge protection device 30 shown in FIG. 1, and FIGS. 3 and 4 are cross-sectional views taken along the line II ′ and II-II ′ of FIG. 2, respectively.

2 to 4, the electrostatic discharge protection device 30 according to the prior art is made of an NMOS transistor. The electrostatic discharge protection device 30 includes a gate electrode 39 and source and drain regions 34 and 35. Further, in order to lower the operating voltage of the electrostatic discharge protection device 30, a halo region 36 having a conductivity type opposite to those regions is further included.

In order to lower the operating voltage of the electrostatic discharge protection device 30, the halo region 36 is doped in a conductive area opposite to the drain region 35 in a predetermined region where the device isolation layer 33 and the drain region 35, which are inactive regions, are in contact with each other. It is formed by a so-called counter doping technique. This halo region 36 provides excellent Band To Band Tunneling (BTBT).

Halo region 36 is typically formed by implanting boron B into well 32 of substrate 31. A portion of the boron implanted at this time is accumulated in the device isolation layer 33 having a shallow trench isolation (STI) structure in contact with the halo region 36. The boron accumulated in the device isolation film 33 acts as a source of leakage current to increase the amount of leakage current in these regions A and B. As a result, the leakage current is caused at the input / output pad.

5 is a simulation diagram showing that the boron dopant is accumulated in the electrostatic discharge protection device according to the prior art. As shown in FIG. 5, it can be seen that a large amount of boron dopant is accumulated at an interface between the device isolation layer and the active region, that is, the halo region.

FIG. 6 is a diagram illustrating that a deep power down (DPD) current increases according to a leakage current of a DQ pin. As shown in FIG. 6, as the amount of leakage current increases due to the boron dopant, a leakage current is induced in the DQ pin, thereby increasing the DPD current.

Accordingly, the present invention has been proposed to solve the problems according to the prior art, and prevents the leakage current from increasing at this region by the boron dopant accumulated in the region where the halo region and the device isolation layer are in contact during the halo region formation process. It is an object of the present invention to provide a method of manufacturing an electrostatic discharge protection device that can improve the operation reliability of the.

According to an aspect of the present invention, a device isolation layer is formed in a substrate to define an active region and an inactive region, and a gate electrode is formed on the substrate to cross the active region in one direction. And forming a halo region in the active region, forming a source and a drain region in the active region exposed to both sides of the gate electrode, and removing a portion of the contact portion between the device isolation layer and the halo region at a predetermined depth. It provides a method of manufacturing an electrostatic discharge protection device comprising the step of forming a trench.

According to the present invention having the above-described configuration, during the halo region forming process, the portions of the halo region and the device isolation layer are in contact with each other to be etched to a certain depth to remove the boron dopants accumulated in these sites, thereby removing the boron from the portion where the halo region and the element separator are in contact with each other. It is possible to prevent the leakage current from increasing due to the dopant, thereby improving the operation reliability of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described.

In the drawings, the thicknesses and spacings of layers (areas) are exaggerated for ease of explanation and clarity, and when referred to as being on another layer or substrate 'top' it may be a different layer or It may be formed directly on the substrate, or a third layer may be interposed therebetween without departing from the technical spirit of the present invention. In addition, the parts denoted by the same reference numerals represent the same layer, and if the reference numerals include English, it means that the same layer is partially modified through an etching or polishing process.

In addition, in the electrostatic discharge protection device according to the embodiment of the present invention, the drain region is connected to the input / output pad, the gate grounded NMOS (GGNMOS) and the drain region are connected to the input / output pad having a source region and a gate electrode connected to ground, The region and gate electrodes include both gate positive (powered) PMOS (GPPMOS), each connected to a power source.

Example

7 is a plan view illustrating an electrostatic discharge protection device 100 according to an embodiment of the present invention, and FIGS. 8 to 15 illustrate a method of manufacturing the electrostatic discharge protection device 100 according to an embodiment of the present invention. The process cross section shown. 8, 10, 12, and 14 are cross-sectional views taken along the line II ′ of FIG. 7, and FIGS. 9, 11, 13, and 15 are II shown in FIG. 7. Process sectional drawing along the II 'line | wire.

First, as shown in FIGS. 7, 8, and 9, the substrate 101 is prepared. The substrate 101 is a semiconductor substrate and is formed of any one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In addition, the substrate 101 has a P type or an N type.

Subsequently, an ion implantation process is performed in the substrate 101 to form the well 102. The well 102 is formed in a P type for a GGNMOS device and an N type for a GPPMOS device.

Subsequently, although not shown, wells of different conductivity types may be formed in the well 102.

Subsequently, an isolation layer 103 is formed in the substrate 101 to define an active region and an inactive region. As shown in FIG. 7, the active region is defined as a square, and is formed to be surrounded by the device isolation layer 103, that is, the inactive region. The device isolation layer 103 is formed by a LOCOS (LOCal Oxidation of Silicon) process or a STI (Shallow Trench Isolation) process. It is preferably formed by an STI process which is advantageous for high integration. The element isolation film 103 is formed of an insulating film. For example, in order to round the etched surface of the trench, the device isolation layer 103 performs an oxidation process on the inner surface of the trench to form a sidewall oxide layer, and a liner oxide layer or a liner nitride layer is formed on the trench. It is formed of an HDP (High Density Plasma) film having excellent embedding characteristics so as to be completely embedded.

Subsequently, the gate electrode 106 is formed on the substrate 101. The gate electrode 106 is formed to cross the active region in one direction as shown in FIG. 7. More preferably, it is formed to cross the short axis direction of the active region. The gate electrode 106 has a stacked structure of the gate insulating film 104 and the gate conductive film 105. For example, the gate insulating film 104 is formed of a silicon oxide film. In addition, the gate conductive film 105 is formed in a structure in which a polysilicon film, a metal silicide layer, and a metal nitride film are appropriately combined and stacked.

Next, as shown in FIGS. 10 and 11, a halo region 107 is formed in the substrate 101 exposed to both side walls of the gate electrode 106. As shown in FIG. 7, the width W1-1 of the hollow region 107 extends in the direction in which the gate electrode 106 extends, that is, in the short axis direction of the active region, and the width W1-of the source and drain regions 109 and 110. It is formed larger than 2), and the width W2-1 is formed smaller than the width W2-2 of the source and drain regions 109 and 110 in the direction parallel to the gate electrode 106. FIG. In the above, the widths W1-1 and W2-1 of the halo region 107 are defined, but this is an example, and the widths W1-1 and W2-1 may be appropriately adjusted according to the characteristics of the device.

Like the source and drain regions 109 and 110, the halo region 107 is formed symmetrically with respect to the gate electrode 106, and extends from one side of the gate electrode 106 to the device isolation layer 103. Can be formed. That is, one side of the halo region 107 may be formed to overlap one side of the gate electrode 106, and the other side may be in contact with the device isolation layer 103. In addition, the halo region 107 is formed to be shallower than the source and drain regions 109 and 110.

The halo region 107 is formed in a different conductivity type from the source and drain regions 109 and 110 to be formed through subsequent processes. Preferably, the halo region 107 is formed in a P type in the case of a GGNMOS device, and formed in an N type in the case of a GPPMOS device. For example, in the case of a GGNMOS device, the halo region 107 may be formed with a dose of 1 × 10 12 to 2 × 10 15 atoms / cm 2 using a boron dopant. In addition, it is formed to a depth shallower than the source and drain regions (109, 110).

Subsequently, spacers 108 are formed on both sidewalls of the gate electrode 106, and then source and drain regions 109 and 110 are formed in the active region exposed to both sidewalls of the spacer 108. Subsequently, a spacer 108 is formed. The spacer 108 may be formed in a stacked structure (oxide film / nitride film) or an opposite structure (nitride film / oxide film) of an oxide film and a nitride film.

The source and drain regions 109 and 110 are formed by a counter doping process which is formed in the opposite conductivity type to the halo region 107. Preferably, the source and drain regions 109 and 110 are formed in an N type for a GGNMOS device and a P type for a GPPMOS device. For example, the source and drain regions 109 and 110 are formed with a dose of 1 × 10 12 to 2 × 10 15 atoms / cm 2 .

Next, as illustrated in FIGS. 7, 12, and 13, the trench 111 is formed by recessing a portion where the device isolation layer 103A and the halo region 107A contact each other at a predetermined depth. As shown in '112-1' of FIG. 7, the trench 111 may remove the boron dopant accumulated in the device isolation layer 103A during the process of forming the halo region 107A and the device isolation layer 103A and the halo region 107A. ) Is formed in a direction orthogonal to the gate electrode 106 so as to be partially etched. In addition, the trench 111 is formed to be spaced apart from the source and drain regions 109 and 110. The width W3 of the trench 111 is not limited in the direction in which the gate electrode 106 extends, and may be appropriately selected in consideration of the protection characteristic and the leakage current characteristic.

The trench 111 may be applied to both a dry etching process and a wet etching process. Preferably, the etching is carried out by a dry etching process which is easy to control etching. The dry etching process uses fluorocarbon as the main gas and oxygen (O 2 ) gas as the additive gas. For example, any one gas selected from the group consisting of C 2 F 6 , C 2 F 8 , CHF 3 and CF 4 is used as the fluorocarbon. Wet etching is performed using HF, HNO 3 and H 2 O.

Next, as illustrated in FIGS. 7, 14, and 15, the insulating layer 112 is formed to fill the trench 111. In this case, the insulating layer 112 is formed of the same oxide film-based material as the device isolation layer 103A. For example, it may be formed of HDP, PSG (PhosphoSilicate Glass), TEOS (Tetra Ethyle Ortho Silicate) or BPSG (BoroPhosphoSilicate Glass).

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not for the purpose of limitation. As such, those skilled in the art may understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a circuit diagram showing a general electrostatic discharge protection circuit having a simple configuration.

2 is a plan view of the electrostatic discharge protection device shown in FIG.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4 is a cross-sectional view taken along the line II-II 'of FIG. 2;

5 is a simulation showing that the boron dopant is stored in the electrostatic discharge protection device according to the prior art.

6 is a diagram illustrating an increase in DPD current according to a leakage current of a DQ pin.

7 is a plan view showing an electrostatic discharge protection device according to an embodiment of the present invention.

8 to 15 are cross-sectional views showing a method of manufacturing an electrostatic discharge protection device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: electrostatic discharge protection element

101: substrate

102: Well

103, 103A: device isolation film

104: gate insulating film

105: gate conductive film

106: gate electrode

107: halo area

108: spacer

109: source region

110: drain region

111: trench

112: insulating film

Claims (12)

Forming an isolation layer in the substrate to define an active region and an inactive region; Forming a gate electrode crossing the active region in one direction on the substrate; Forming a halo region in the active region; Forming a source and a drain region in the active region exposed to both sides of the gate electrode; And Forming a trench by recessing a portion of the device isolation layer and the halo region to a predetermined depth; Method of manufacturing an electrostatic discharge protection device comprising a. The method of claim 1, And forming the trench deeper than the halo region. The method of claim 1, And forming the trench in a direction orthogonal to the gate electrode. The method of claim 1, And forming the trench to be spaced apart from the source and drain regions. The method of claim 1, The halo region is formed to have a width larger than the source and drain regions in the extending direction of the gate electrode, and a width smaller than the source and drain regions in the direction parallel to the gate electrode. Manufacturing method. The method of claim 1, And the halo region is formed to be shallower than the source and drain regions. The method of claim 1, Forming the trench, A method of manufacturing an electrostatic discharge protection device formed by partially recessing the device isolation layer and the halo region. The method of claim 1, And the halo region is formed to have a different conductivity type from the source and drain regions. The method of claim 8, The halo region is a P-type manufacturing method of the electrostatic discharge protection element. The method of claim 1, The trench is a method of manufacturing an electrostatic discharge protection device formed by a dry etching process or a wet etching process. The method of claim 1, After forming the trench, And forming an insulating film so that the trench is buried. The method of claim 11, And the insulating film is formed of the same material as the device isolation film.
KR1020080134651A 2008-12-26 2008-12-26 Method for manufacturing electrostatic discharge protection device KR20100076554A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8242565B2 (en) 2009-04-30 2012-08-14 Hynix Semiconductor Inc. Electrostatic discharge protection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8242565B2 (en) 2009-04-30 2012-08-14 Hynix Semiconductor Inc. Electrostatic discharge protection device

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