KR20100076305A - Method for forming patterns of a semiconductor device - Google Patents

Method for forming patterns of a semiconductor device Download PDF

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Publication number
KR20100076305A
KR20100076305A KR1020080134316A KR20080134316A KR20100076305A KR 20100076305 A KR20100076305 A KR 20100076305A KR 1020080134316 A KR1020080134316 A KR 1020080134316A KR 20080134316 A KR20080134316 A KR 20080134316A KR 20100076305 A KR20100076305 A KR 20100076305A
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KR
South Korea
Prior art keywords
etching
pattern
layer
auxiliary
semiconductor device
Prior art date
Application number
KR1020080134316A
Other languages
Korean (ko)
Inventor
권혜진
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080134316A priority Critical patent/KR20100076305A/en
Publication of KR20100076305A publication Critical patent/KR20100076305A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

PURPOSE: A pattern formation method of a semiconductor device is provided to form an etching sub pattern which has narrower width than the width of a photoresist pattern by etching a sidewall of the etching sub pattern of the lowermost layer. CONSTITUTION: An etching object film(103) is formed on the top of a semiconductor substrate(101). The first etching sub-layer and the second etching sub-layer are laminated on the top of the etching object film. A photoresist pattern is formed on the top of the second etching sub-layer. The first and the second etching sub-layer are etched so that a first etching sub pattern(105a) and a second etching sub pattern(107a) are formed. The sidewall of the first etching sub pattern is etched.

Description

Method for forming patterns of a semiconductor device

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a pattern of a semiconductor device capable of forming a pattern having a width smaller than the resolution of an exposure apparatus.

In general, a pattern forming process of a semiconductor device forms a photoresist pattern on a predetermined etching film (for example, a silicon film, an insulating film, or a conductive film) for forming a pattern, and then uses the photoresist pattern as an etching barrier. The etching target is etched to form a desired pattern.

On the other hand, as a high integration of semiconductor devices is applied to a design rule of a small CD (Critical Dimension) of 40 nm or less, a numerical aperture (Numerical Aperture) NA of 1.35 or more is required. When the numerical aperture is increased, the width of the photoresist pattern may be reduced. However, as the numerical aperture is increased, the depth of focus (DOF) decreases, so the thickness of the photoresist pattern should be made thinner. When the thickness of the photoresist pattern is formed thin, the photoresist pattern does not remain during the etching process and is removed, making it difficult to serve as an etching barrier. In addition, even if the exposure equipment is improved, the width of the pattern patterned by using the photoresist pattern as an etching barrier is defined by the pattern defined in the reticle and the width of the photoresist pattern subject to the resolution limitation of the exposure equipment. There is a limit to this.

The present invention provides a method of forming a pattern of a semiconductor device capable of forming a pattern having a width smaller than the resolution of exposure equipment.

In the method of forming a pattern of a semiconductor device according to the present invention, forming an etching target layer on an upper portion of the semiconductor substrate, stacking the first and second etching auxiliary layers on the etching target layer, a photoresist pattern on the second etching auxiliary layer Forming a first and a second etching auxiliary layer by etching the first and second etching auxiliary layers by an etching process using the photoresist pattern as an etching barrier, and etching sidewalls of the first etching auxiliary pattern. And etching the etching target layer by an etching process using the first etching assistant pattern as an etching barrier.

After etching the sidewalls of the first etching assistant pattern, the width of the first etching assistant pattern is smaller than the width of the second etching assistant pattern.

The etching target film is formed using an oxide film, the first etching auxiliary film is formed using a polysilicon film, and the second etching auxiliary film is formed using an amorphous carbon film.

Etching the sidewalls of the first etching assistant pattern may be performed using a dry etching process using an etching gas in which HBr gas, O 2 gas, and He gas are mixed.

HBr gas is injected at a flow rate of 100 sccm to 200 sccm.

O 2 gas is injected at a flow rate of 5 sccm to 15 sccm.

He gas is injected at a flow rate of 200 sccm to 400 sccm.

The dry etching process is carried out at a pressure of 50mT to 70mT.

The present invention forms an etching auxiliary pattern by etching the etching auxiliary layers on the etching target layer by an etching process using the photoresist pattern as an etching barrier. Thereafter, the sidewalls of the lowermost layer of the etching assistant pattern may be etched using the difference in the etching selectivity of the etching assistant patterns to form an etching assistant pattern having a width narrower than that of the photoresist pattern subject to the resolution limitation of the exposure apparatus. As described above, the etching target layer may be etched by using the lowermost etching assistant pattern that overcomes the limitation of the resolution of the exposure apparatus as an etching barrier to overcome the limitation of the exposure process, thereby forming a hard mask pattern having a fine width. When the pattern of the semiconductor device is patterned using the hard mask pattern as an etching barrier, a pattern having a fine width that overcomes the limitation of the exposure resolution may be formed.

The present invention can form a pattern having a fine width without increasing the numerical aperture of the exposure equipment. As described above, the present invention can use an exposure apparatus having a small numerical aperture, thereby securing a margin of focus (DOF), so that the photoresist pattern can be formed to a sufficient thickness.

Since the photoresist pattern can be formed to a sufficiently high thickness, the photoresist pattern can sufficiently serve as an etching barrier, thereby lowering the height of the etching target layer used as an etching auxiliary layer or hard mask layer under the photoresist pattern. Can be.

Since the etching process is performed using the difference in the etching selectivity, the height of the etching target layer used as the hard mask layer may not be lowered during the etching process of each layer, so the height of the etching target layer used as the hard mask layer may be lowered. have.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, an etch target layer 103, a first etch auxiliary layer 105, a second etch auxiliary layer 107, and a bottom anti-reflective coating layer (BARC) are formed on the semiconductor substrate 101. ) 111 are stacked. A SiON layer 109 may be further formed between the second etching auxiliary layer 107 and the lower antireflection layer 111. The photoresist pattern 113 is formed on the lower anti-reflection film 111.

The etching target film 103 may be a hard mask for use as an etching barrier in an etching process, and an insulating film for an interlayer insulating film or a conductive film for metal wiring may be further formed between the etching target film 103 and the semiconductor substrate 101. Can be formed. The etching target film 103 is preferably formed using an oxide film.

The first etching auxiliary layer 105 is formed using a material in consideration of the etching selectivity with respect to the etching target layer 103 and the etching selectivity with respect to the second etching auxiliary layer 107. In more detail, during the process of etching the second etching auxiliary layer 105, the first etching auxiliary layer 105 should not be removed and the etching process targeting the first etching auxiliary layer 105 is performed. In some embodiments, the etching target layer 103 and the second etching auxiliary layer 107 should not be removed. To this end, the second etching auxiliary layer 107 is preferably formed using an amorphous carbon layer (ACL), and the first etching auxiliary layer 105 is preferably formed using polysilicon. .

The lower anti-reflection film 111 and the SiON film 109 are formed to improve the profile of the photoresist pattern 113 by preventing diffuse reflection of light during the exposure process for forming the photoresist pattern 113. On the other hand, the lower anti-reflection film 111 and the SiON film 109 serves to alleviate the step difference in the lower portion. The lower anti-reflection film 111 may include C or F as an organic material.

The photoresist pattern 113 is formed for use as an etching barrier when etching the first and second etching auxiliary films 105 and 107 in a subsequent process.

Referring to FIG. 1B, a second etching assistant layer 107 and a first etching assistant layer 105 are etched by an etching process using the photoresist pattern 113 and the SiON layer 109 as an etching barrier. The pattern 107a and the first etching assistant pattern 105a are formed. While the first and second etch assist patterns 105a and 107a are formed, the photoresist pattern 113 and the lower anti-reflection film 111 may be removed, and the SiON film 109 may be formed by the photoresist pattern 113. SiON pattern 109a may be formed. In this case, the widths of the first and second etching auxiliary patterns 105a and 107a are defined by the widths of the photoresist patterns 113, and thus are formed according to the limitation of the exposure resolution. In this case, the first and second etch assist patterns 105a and 107a have the same width. To this end, the second etching auxiliary layer is etched by flowing the gas mixed with H2 and N2 at a high flow rate of 200sccm or more. In addition, the first etching auxiliary layer is etched using a gas in which HBr, O 2 , and He are mixed.

Referring to FIG. 1C, the sidewall of the first etching assistant pattern 105a is further etched. Accordingly, the width W2 of the first etching assistant pattern 105a is smaller than the width of the second etching assistant pattern 107a. When the etching process is performed by targeting the first etching auxiliary pattern 105a, the first etching auxiliary pattern 105a is compared with the etching target layer 105 to prevent the exposed etching target layer 103 from being etched. It is preferable to use an etching process using a material which is rapidly etched. In more detail, the etching process targeting the first etching auxiliary pattern 105a may be performed using a dry etching process using an etching gas in which HBr gas, O 2 gas, and He gas are mixed. At this time, HBr gas is preferably injected at a flow rate of 100sccm to 200sccm, O 2 gas is preferably injected at a flow rate of 5sccm to 15sccm, He gas is preferably injected at a flow rate of 200sccm to 400sccm. In addition, when performing the dry etching process, the pressure is preferably 50mT to 70mT to prevent the etching of the etching target layer 103 and to target the first etching auxiliary pattern 105a.

As the width of the first etching assistant pattern 105a is narrowed by the above-described process, the width W2 of the first etching assistant pattern 105a is smaller than the resolution of the exposure apparatus.

Referring to FIG. 1D, the second etching assistant pattern 107a remaining on the first etching assistant pattern 105a is removed.

Referring to FIG. 1E, a hard mask pattern 103a is formed by etching the etch target layer 103 by an etching process using the first etching auxiliary pattern 105a having a width narrower than that of an exposure apparatus as an etching barrier. The hard mask pattern 103a may be used as an etch barrier for patterning metal lines, word lines, or gate lines.

Subsequently, although not shown in the drawing, the semiconductor substrate 100 exposed between the hard mask patterns 103a may be etched to form trenches for device isolation layers.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: semiconductor substrate 103: etching target film

105: first etching auxiliary film 107: second etching auxiliary film

109: SiON film 111: lower antireflection film

113: photoresist pattern 109a: SiON pattern

107a: second etching auxiliary pattern 105a: second etching auxiliary pattern

103a: hard mask pattern

Claims (8)

Forming an etching target layer on the semiconductor substrate; Stacking first and second etching auxiliary layers on the etching target layer; Forming a photoresist pattern on the second etching auxiliary layer; Etching the first and second etching auxiliary layers by an etching process using the photoresist pattern as an etching barrier to form first and second etching auxiliary patterns; Etching sidewalls of the first etching assistant pattern; And And etching the etching target layer by an etching process using the first etching assistant pattern as an etching barrier. The method of claim 1, After etching the sidewalls of the first etching assistant pattern, The width of the first etching auxiliary pattern is a pattern forming method of a semiconductor device narrower than the width of the second etching auxiliary pattern. The method of claim 1, The etching target layer is formed using an oxide film, The first etching auxiliary layer is formed using a polysilicon layer, The second etching auxiliary layer is a pattern forming method of a semiconductor device formed using an amorphous carbon film. The method of claim 3, wherein Etching the sidewalls of the first etching auxiliary pattern using a dry etching process using an etching gas including HBr gas, O 2 gas, and He gas. The method of claim 4, wherein The HBr gas is a pattern forming method of a semiconductor device is injected at a flow rate of 100sccm to 200sccm. The method of claim 4, wherein The O 2 gas is a pattern forming method of a semiconductor device is injected at a flow rate of 5sccm to 15sccm. The method of claim 4, wherein The He gas is a pattern forming method of a semiconductor device is injected at a flow rate of 200sccm to 400sccm. The method of claim 4, wherein The dry etching process is a pattern forming method of a semiconductor device performed at a pressure of 50mT to 70mT.
KR1020080134316A 2008-12-26 2008-12-26 Method for forming patterns of a semiconductor device KR20100076305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080134316A KR20100076305A (en) 2008-12-26 2008-12-26 Method for forming patterns of a semiconductor device

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Application Number Priority Date Filing Date Title
KR1020080134316A KR20100076305A (en) 2008-12-26 2008-12-26 Method for forming patterns of a semiconductor device

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KR20100076305A true KR20100076305A (en) 2010-07-06

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