KR20100074772A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

 The present invention provides a semiconductor device and a method of manufacturing the same, which can prevent an increase in resistance even if the gate width is reduced by forming conductive layers on top and sidewalls of the gate electrode. In an embodiment, a semiconductor device and a method of manufacturing the same may include forming a gate electrode on a semiconductor substrate, forming a conductive layer on an entire surface including the gate electrode, and etching the conductive layer. And forming a gate pattern on top and both sidewalls of the gate layer surrounded by the conductive layer.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of increasing a yield in manufacturing a highly integrated semiconductor device and a technology related to the method.

In general, semiconductor memory devices store information such as data and program instructions, and semiconductor memory devices are largely divided into DRAM and SRAM. Here, DRAM (DRAM) is a memory that can read stored information and store other information, and can read and write information, but periodically during a period of time when power is supplied. If you do not rewrite the memory, the memory will be lost. As described above, DRAM needs to continue refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the density can be increased.

Here, a metal-oxide semiconductor field effect transistor (hereinafter abbreviated as " MOSFET ") mainly used for memory, logic, and the like of a DRAM is a gate oxide film or a polysilicon film on a semiconductor substrate. After depositing the gate metal and the gate hard mask, the gate is stacked to form a channel by a mask / etch process. At this time, as the semiconductor devices are highly integrated, the planar area occupied by the MOSFETs in the cell region gradually decreases, and thus the length of the channel is shortened. These channel lengths cause problems due to short channels, such as fluctuations in threshold voltage and punch-through leakage current. Therefore, as semiconductor devices become more highly integrated in recent years, there is a limitation in solving the above-described problems with the conventional structure, and there are many difficulties in securing a layout and area for implementing the device in response to high integration.

On the other hand, the conventional MOSFET has performed an operation for transferring the signal between the source / drain by the signal transmitted through the gate. Transistors that perform a limited function have a relatively simple configuration consisting of a source / drain and a gate, and in the case of reducing the layout area, reducing the gate width is a typical method. After the gate is formed, the gate line width is reduced to complete the transistor through subsequent processes such as ion implantation and heat treatment, and the channel length of the MOSFET depending on the gate line width can be further reduced through the subsequent process. As a result, various adverse effects such as punch-through phenomenon, drain-induced barrier lowering (DIBL), and gate-induced drain leakage (GIDL) appear.

In addition, as the size of the semiconductor device becomes smaller, the space between the gates decreases as the gate size decreases. As the space between these gates becomes smaller, the resistance of the same kind as the metal layer increases on the gate polysilicon layer. This increase in resistance has a problem that adversely affects the speed of the semiconductor device.

In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device and a method of manufacturing the same, which can prevent an increase in resistance even if the gate width is reduced by forming conductive layers on the top and sidewalls of the gate electrode.

The present invention provides a method of forming a gate electrode on a semiconductor substrate, forming a conductive layer on an entire surface including the gate electrode, and etching the conductive layer to surround top and both sidewalls of the gate electrode with the conductive layer. It provides a method of manufacturing a semiconductor device comprising the step of forming a gate pattern.

Preferably, the forming of the gate pattern may include forming a hard mask layer on the conductive layer, patterning the hard mask layer by an exposure process, and using the patterned hard mask layer as an etch mask. Etching the conductive layer.

Preferably, the method further includes forming a gate oxide film on the semiconductor substrate.

Preferably, the gate electrode is characterized in that the polysilicon layer.

Preferably, the conductive layer is formed of any one selected from the group consisting of titanium, tungsten, aluminum and combinations thereof.

Preferably, the spacer may be further formed on sidewalls of the gate pattern.

Preferably, the method may further include performing ion implantation after forming the spacer.

The present invention also provides a semiconductor device including a gate electrode formed on a semiconductor substrate, a conductive layer surrounding upper and sidewalls of the gate electrode, a spacer formed on both sides of the conductive layer, and a source / drain formed on the semiconductor substrate.

The present invention has the advantage of preventing the increase in resistance even if the gate width is reduced by forming a conductive layer on the top and sidewalls of the gate electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and where it is mentioned that the layer is on another layer or substrate, it may be formed directly on another layer or substrate, or A third layer may be interposed between them.

Also, the same reference numerals throughout the specification represent the same components.

1A to 1H are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

1A and 1B, a gate oxide film 110 is formed on a semiconductor substrate 100. The gate electrode 120 is formed on the gate oxide film 110. In this case, the gate electrode 120 is preferably formed of a polysilicon layer.

1C and 1D, after forming a photoresist film on the gate electrode 120, the photoresist pattern 130 is formed by an exposure and development process using a gate mask. The gate electrode 120 is etched using the photoresist pattern 130 as a mask to form the gate electrode pattern 125.

Referring to FIG. 1E, after removing the photoresist pattern 130, the conductive layer 140 is formed on the entire surface including the gate electrode pattern 125. At this time, the conductive layer 140 is preferably formed of any one selected from the group consisting of titanium (Ti), tungsten (W) and aluminum (Al) and combinations thereof.

1F and 1G, a hard mask nitride film 150 is formed on the conductive layer 140. Thereafter, the hard mask nitride layer 150 is patterned by an exposure process, and then the conductive layer 140 and the gate oxide layer 110 are exposed until the semiconductor substrate 100 is exposed using the patterned hard mask nitride layer 150 as an etch mask. The gate pattern 160 is formed by etching. In this case, the upper and both sidewalls of the gate electrode pattern 125 may be surrounded by the conductive layer 140.

Referring to FIG. 1H, a low concentration source / drain region 180 is formed in the semiconductor substrate 100 of the edge region of the gate pattern 160 by performing an impurity ion implantation process on the semiconductor substrate 100. . This is called lightly doped drain (LDD).

Subsequently, after forming an insulating film on the entire surface including the gate pattern 160, the insulating film is etched back to form a spacer 170 on the sidewall of the gate pattern 160. At this time, the insulating film is preferably formed of an oxide film or a nitride film. The source / drain region 190 is formed by performing an impurity ion implantation process to form a junction in the semiconductor substrate 100.

The present invention provides a method of forming a gate electrode on a semiconductor substrate, forming a conductive layer on an entire surface including the gate electrode, and etching the conductive layer to surround top and both sidewalls of the gate electrode with the conductive layer. Forming a gate pattern. That is, by forming metal layers on the top and sidewalls of the gate conductive layer, an increase in resistance can be prevented even if the gate width is reduced.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1H are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Claims (8)

Forming a gate electrode on the semiconductor substrate; Forming a conductive layer on the entire surface including the gate electrode; And Etching the conductive layer to form a gate pattern in which upper and both sidewalls of the gate electrode are surrounded by the conductive layer Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming the gate pattern Forming a hard mask layer on the conductive layer; Patterning the hard mask layer by an exposure process; And And etching the conductive layer using the patterned hard mask layer as an etching mask. The method of claim 1, And forming a gate oxide film on the semiconductor substrate. The method of claim 1, The gate electrode is a manufacturing method of a semiconductor device, characterized in that the polysilicon layer. The method of claim 1, The conductive layer is a method of manufacturing a semiconductor device, characterized in that formed by any one selected from the group consisting of titanium, tungsten, aluminum and combinations thereof. The method of claim 1, And forming a spacer on sidewalls of the gate pattern. The method of claim 6, And forming ion spacers, and then performing ion implantation. A gate electrode formed on the semiconductor substrate; A conductive layer surrounding upper and sidewalls of the gate electrode; Spacers formed on both sides of the conductive layer; And Source / drain formed on the semiconductor substrate Semiconductor device comprising a.

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